1package xiangshan.backend.decode 2 3import chisel3._ 4import chisel3.util._ 5import freechips.rocketchip.rocket.DecodeLogic 6import xiangshan.backend.decode.Instructions._ 7import xiangshan.{FPUCtrlSignals, XSModule} 8 9class FPDecoder extends XSModule{ 10 val io = IO(new Bundle() { 11 val instr = Input(UInt(32.W)) 12 val fpCtrl = Output(new FPUCtrlSignals) 13 }) 14 15 def X = BitPat("b?") 16 def N = BitPat("b0") 17 def Y = BitPat("b1") 18 val s = BitPat(S) 19 val d = BitPat(D) 20 val i = BitPat(I) 21 22 val default = List(X,X,X,N,N,N,X,X,X) 23 24 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 25 val single: Array[(BitPat, List[BitPat])] = Array( 26 FMV_W_X -> List(N,s,d,Y,N,Y,N,N,N), 27 FCVT_S_W -> List(N,s,s,Y,Y,Y,N,N,Y), 28 FCVT_S_WU-> List(N,s,s,Y,Y,Y,N,N,Y), 29 FCVT_S_L -> List(N,s,s,Y,Y,Y,N,N,Y), 30 FCVT_S_LU-> List(N,s,s,Y,Y,Y,N,N,Y), 31 FMV_X_W -> List(N,d,i,N,N,N,N,N,N), 32 FCLASS_S -> List(N,s,i,N,N,N,N,N,N), 33 FCVT_W_S -> List(N,s,i,N,Y,N,N,N,Y), 34 FCVT_WU_S-> List(N,s,i,N,Y,N,N,N,Y), 35 FCVT_L_S -> List(N,s,i,N,Y,N,N,N,Y), 36 FCVT_LU_S-> List(N,s,i,N,Y,N,N,N,Y), 37 FEQ_S -> List(N,s,i,N,Y,N,N,N,N), 38 FLT_S -> List(N,s,i,N,Y,N,N,N,N), 39 FLE_S -> List(N,s,i,N,Y,N,N,N,N), 40 FSGNJ_S -> List(N,s,s,N,N,Y,N,N,N), 41 FSGNJN_S -> List(N,s,s,N,N,Y,N,N,N), 42 FSGNJX_S -> List(N,s,s,N,N,Y,N,N,N), 43 FMIN_S -> List(N,s,s,N,Y,Y,N,N,N), 44 FMAX_S -> List(N,s,s,N,Y,Y,N,N,N), 45 FADD_S -> List(Y,s,s,N,Y,Y,N,N,N), 46 FSUB_S -> List(Y,s,s,N,Y,Y,N,N,N), 47 FMUL_S -> List(N,s,s,N,Y,Y,N,N,N), 48 FMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 49 FMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 50 FNMADD_S -> List(N,s,s,N,Y,Y,N,N,N), 51 FNMSUB_S -> List(N,s,s,N,Y,Y,N,N,N), 52 FDIV_S -> List(N,s,s,N,Y,Y,Y,N,N), 53 FSQRT_S -> List(N,s,s,N,Y,Y,N,Y,N) 54 ) 55 56 57 // isAddSub tagIn tagOut fromInt wflags fpWen div sqrt fcvt 58 val double: Array[(BitPat, List[BitPat])] = Array( 59 FMV_D_X -> List(N,d,d,Y,N,Y,N,N,N), 60 FCVT_D_W -> List(N,d,d,Y,Y,Y,N,N,Y), 61 FCVT_D_WU-> List(N,d,d,Y,Y,Y,N,N,Y), 62 FCVT_D_L -> List(N,d,d,Y,Y,Y,N,N,Y), 63 FCVT_D_LU-> List(N,d,d,Y,Y,Y,N,N,Y), 64 FMV_X_D -> List(N,d,i,N,N,N,N,N,N), 65 FCLASS_D -> List(N,d,i,N,N,N,N,N,N), 66 FCVT_W_D -> List(N,d,i,N,Y,N,N,N,Y), 67 FCVT_WU_D-> List(N,d,i,N,Y,N,N,N,Y), 68 FCVT_L_D -> List(N,d,i,N,Y,N,N,N,Y), 69 FCVT_LU_D-> List(N,d,i,N,Y,N,N,N,Y), 70 FCVT_S_D -> List(N,d,s,N,Y,Y,N,N,Y), 71 FCVT_D_S -> List(N,s,d,N,Y,Y,N,N,Y), 72 FEQ_D -> List(N,d,i,N,Y,N,N,N,N), 73 FLT_D -> List(N,d,i,N,Y,N,N,N,N), 74 FLE_D -> List(N,d,i,N,Y,N,N,N,N), 75 FSGNJ_D -> List(N,d,d,N,N,Y,N,N,N), 76 FSGNJN_D -> List(N,d,d,N,N,Y,N,N,N), 77 FSGNJX_D -> List(N,d,d,N,N,Y,N,N,N), 78 FMIN_D -> List(N,d,d,N,Y,Y,N,N,N), 79 FMAX_D -> List(N,d,d,N,Y,Y,N,N,N), 80 FADD_D -> List(Y,d,d,N,Y,Y,N,N,N), 81 FSUB_D -> List(Y,d,d,N,Y,Y,N,N,N), 82 FMUL_D -> List(N,d,d,N,Y,Y,N,N,N), 83 FMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 84 FMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 85 FNMADD_D -> List(N,d,d,N,Y,Y,N,N,N), 86 FNMSUB_D -> List(N,d,d,N,Y,Y,N,N,N), 87 FDIV_D -> List(N,d,d,N,Y,Y,Y,N,N), 88 FSQRT_D -> List(N,d,d,N,Y,Y,N,Y,N) 89 ) 90 91 val table = single ++ double 92 93 val decoder = DecodeLogic(io.instr, default, table) 94 95 val ctrl = io.fpCtrl 96 val sigs = Seq( 97 ctrl.isAddSub, ctrl.typeTagIn, ctrl.typeTagOut, 98 ctrl.fromInt, ctrl.wflags, ctrl.fpWen, 99 ctrl.div, ctrl.sqrt, ctrl.fcvt 100 ) 101 sigs.zip(decoder).foreach({case (s, d) => s := d}) 102 ctrl.typ := io.instr(21, 20) 103 ctrl.fmt := io.instr(26, 25) 104 ctrl.rm := io.instr(14, 12) 105 106 val fmaTable: Array[(BitPat, List[BitPat])] = Array( 107 FADD_S -> List(BitPat("b00"),N), 108 FADD_D -> List(BitPat("b00"),N), 109 FSUB_S -> List(BitPat("b01"),N), 110 FSUB_D -> List(BitPat("b01"),N), 111 FMUL_S -> List(BitPat("b00"),N), 112 FMUL_D -> List(BitPat("b00"),N), 113 FMADD_S -> List(BitPat("b00"),Y), 114 FMADD_D -> List(BitPat("b00"),Y), 115 FMSUB_S -> List(BitPat("b01"),Y), 116 FMSUB_D -> List(BitPat("b01"),Y), 117 FNMADD_S-> List(BitPat("b11"),Y), 118 FNMADD_D-> List(BitPat("b11"),Y), 119 FNMSUB_S-> List(BitPat("b10"),Y), 120 FNMSUB_D-> List(BitPat("b10"),Y) 121 ) 122 val fmaDefault = List(BitPat("b??"), N) 123 Seq(ctrl.fmaCmd, ctrl.ren3).zip( 124 DecodeLogic(io.instr, fmaDefault, fmaTable) 125 ).foreach({ 126 case (s, d) => s := d 127 }) 128} 129