1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.fu.vector.Bundles.VType 33import yunsuan.VpermType 34 35import scala.collection.Seq 36 37trait VectorConstants { 38 val MAX_VLMUL = 8 39 val FP_TMP_REG_MV = 32 40 val VECTOR_TMP_REG_LMUL = 32 // 32~38 -> 7 41} 42 43class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 44 val enq = new Bundle { val staticInst = Input(new StaticInst) } 45 val vtype = Input(new VType) 46 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 47 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 48 val readyFromRename = Input(Vec(RenameWidth, Bool())) 49 val deq = new Bundle { 50 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 51 val isVset = Output(Bool()) 52 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 53 val validToRename = Output(Vec(RenameWidth, Bool())) 54 val complexNum = Output(UInt(3.W)) 55 } 56 val csrCtrl = Input(new CustomCSRCtrlIO) 57} 58 59/** 60 * @author zly 61 */ 62class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 63 val io = IO(new DecodeUnitCompIO) 64 65 val maxUopSize = MaxUopSize 66 //input bits 67 val staticInst = Wire(new StaticInst) 68 69 staticInst := io.enq.staticInst 70 71 val src1 = Cat(0.U(1.W), staticInst.instr(19, 15)) 72 val src2 = Cat(0.U(1.W), staticInst.instr(24, 20)) 73 val dest = Cat(0.U(1.W), staticInst.instr(11, 7)) 74 75 //output bits 76 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 77 val validToRename = Wire(Vec(RenameWidth, Bool())) 78 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 79 val complexNum = Wire(UInt(3.W)) 80 81 //output of DecodeUnit 82 val decodedInsts_u = Wire(new DecodedInst) 83 val isVset_u = Wire(Bool()) 84 85 //pre decode 86 val simple = Module(new DecodeUnit) 87 simple.io.enq.ctrlFlow := staticInst 88 simple.io.enq.vtype := io.vtype 89 simple.io.csrCtrl := io.csrCtrl 90 decodedInsts_u := simple.io.deq.decodedInst 91 isVset_u := simple.io.deq.decodedInst.isVset 92 when(isVset_u) { 93 when(dest === 0.U && src1 === 0.U) { 94 decodedInsts_u.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 95 }.elsewhen(src1 === 0.U) { 96 decodedInsts_u.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 97 } 98 when(io.vtype.illegal){ 99 decodedInsts_u.flushPipe := true.B 100 } 101 } 102 //Type of uop Div 103 val typeOfDiv = decodedInsts_u.uopSplitType 104 105 //LMUL 106 val lmul = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(4.W), Array( 107 "b001".U -> 2.U, 108 "b010".U -> 4.U, 109 "b011".U -> 8.U 110 )) 111 val numOfUopVslide = MuxLookup(simple.io.enq.vtype.vlmul, 1.U(log2Up(maxUopSize+1).W), Array( 112 "b001".U -> 3.U, 113 "b010".U -> 10.U, 114 "b011".U -> 36.U 115 )) 116 //number of uop 117 val numOfUop = MuxLookup(typeOfDiv, 1.U(log2Up(maxUopSize+1).W), Array( 118 UopSplitType.VEC_0XV -> 2.U, 119 UopSplitType.DIR -> Mux(dest =/= 0.U, 2.U, 120 Mux(src1 =/= 0.U, 1.U, 121 Mux(VSETOpType.isVsetvl(decodedInsts_u.fuOpType), 2.U, 1.U))), 122 UopSplitType.VEC_VVV -> lmul, 123 UopSplitType.VEC_EXT2 -> lmul, 124 UopSplitType.VEC_EXT4 -> lmul, 125 UopSplitType.VEC_EXT8 -> lmul, 126 UopSplitType.VEC_VVM -> lmul, 127 UopSplitType.VEC_VXM -> (lmul +& 1.U), 128 UopSplitType.VEC_VXV -> (lmul +& 1.U), 129 UopSplitType.VEC_VVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 130 UopSplitType.VEC_WVW -> Cat(lmul, 0.U(1.W)), // lmul <= 4 131 UopSplitType.VEC_VXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 132 UopSplitType.VEC_WXW -> Cat(lmul, 1.U(1.W)), // lmul <= 4 133 UopSplitType.VEC_WVV -> Cat(lmul, 0.U(1.W)), // lmul <= 4 134 UopSplitType.VEC_WXV -> Cat(lmul, 1.U(1.W)), // lmul <= 4 135 UopSplitType.VEC_SLIDE1UP -> (lmul +& 1.U), 136 UopSplitType.VEC_FSLIDE1UP -> lmul, 137 UopSplitType.VEC_SLIDE1DOWN -> Cat(lmul, 0.U(1.W)), 138 UopSplitType.VEC_FSLIDE1DOWN -> (Cat(lmul, 0.U(1.W)) -1.U), 139 UopSplitType.VEC_VRED -> lmul, 140 UopSplitType.VEC_SLIDEUP -> (numOfUopVslide + 1.U), 141 UopSplitType.VEC_ISLIDEUP -> numOfUopVslide, 142 UopSplitType.VEC_SLIDEDOWN -> (numOfUopVslide + 1.U), 143 UopSplitType.VEC_ISLIDEDOWN -> numOfUopVslide, 144 UopSplitType.VEC_M0X -> (lmul +& 1.U), 145 UopSplitType.VEC_MVV -> (Cat(lmul, 0.U(1.W)) -1.U), 146 UopSplitType.VEC_M0X_VFIRST -> 2.U, 147 )) 148 149 //uop div up to maxUopSize 150 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 151 csBundle.map { case dst => 152 dst := decodedInsts_u 153 dst.firstUop := false.B 154 dst.lastUop := false.B 155 } 156 157 csBundle(0).numUops := numOfUop 158 csBundle(0).firstUop := true.B 159 csBundle(numOfUop - 1.U).lastUop := true.B 160 161 switch(typeOfDiv) { 162 is(UopSplitType.DIR) { 163 when(isVset_u) { 164 when(dest =/= 0.U) { 165 csBundle(0).fuType := FuType.vsetiwi.U 166 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInsts_u.fuOpType) 167 csBundle(0).flushPipe := false.B 168 csBundle(0).rfWen := true.B 169 csBundle(0).vecWen := false.B 170 csBundle(1).ldest := VCONFIG_IDX.U 171 csBundle(1).rfWen := false.B 172 csBundle(1).vecWen := true.B 173 }.elsewhen(src1 =/= 0.U) { 174 csBundle(0).ldest := VCONFIG_IDX.U 175 }.elsewhen(VSETOpType.isVsetvli(decodedInsts_u.fuOpType)) { 176 csBundle(0).fuType := FuType.vsetfwf.U 177 csBundle(0).srcType(0) := SrcType.vp 178 csBundle(0).lsrc(0) := VCONFIG_IDX.U 179 }.elsewhen(VSETOpType.isVsetvl(decodedInsts_u.fuOpType)) { 180 csBundle(0).srcType(0) := SrcType.reg 181 csBundle(0).srcType(1) := SrcType.imm 182 csBundle(0).lsrc(1) := 0.U 183 csBundle(0).ldest := FP_TMP_REG_MV.U 184 csBundle(0).fuType := FuType.i2f.U 185 csBundle(0).rfWen := false.B 186 csBundle(0).fpWen := true.B 187 csBundle(0).vecWen := false.B 188 csBundle(0).fpu.isAddSub := false.B 189 csBundle(0).fpu.typeTagIn := FPU.D 190 csBundle(0).fpu.typeTagOut := FPU.D 191 csBundle(0).fpu.fromInt := true.B 192 csBundle(0).fpu.wflags := false.B 193 csBundle(0).fpu.fpWen := true.B 194 csBundle(0).fpu.div := false.B 195 csBundle(0).fpu.sqrt := false.B 196 csBundle(0).fpu.fcvt := false.B 197 csBundle(0).flushPipe := false.B 198 csBundle(1).fuType := FuType.vsetfwf.U 199 csBundle(1).srcType(0) := SrcType.vp 200 csBundle(1).lsrc(0) := VCONFIG_IDX.U 201 csBundle(1).srcType(1) := SrcType.fp 202 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 203 csBundle(1).ldest := VCONFIG_IDX.U 204 } 205 } 206 } 207 is(UopSplitType.VEC_VVV) { 208 for (i <- 0 until MAX_VLMUL) { 209 csBundle(i).lsrc(0) := src1 + i.U 210 csBundle(i).lsrc(1) := src2 + i.U 211 csBundle(i).lsrc(2) := dest + i.U 212 csBundle(i).ldest := dest + i.U 213 csBundle(i).uopIdx := i.U 214 } 215 } 216 is(UopSplitType.VEC_EXT2) { 217 for (i <- 0 until MAX_VLMUL / 2) { 218 csBundle(2 * i).lsrc(1) := src2 + i.U 219 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 220 csBundle(2 * i).ldest := dest + (2 * i).U 221 csBundle(2 * i).uopIdx := (2 * i).U 222 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 223 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 224 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 225 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 226 } 227 } 228 is(UopSplitType.VEC_EXT4) { 229 for (i <- 0 until MAX_VLMUL / 4) { 230 csBundle(4 * i).lsrc(1) := src2 + i.U 231 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 232 csBundle(4 * i).ldest := dest + (4 * i).U 233 csBundle(4 * i).uopIdx := (4 * i).U 234 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 235 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 236 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 237 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 238 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 239 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 240 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 241 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 242 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 243 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 244 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 245 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 246 } 247 } 248 is(UopSplitType.VEC_EXT8) { 249 for (i <- 0 until MAX_VLMUL) { 250 csBundle(i).lsrc(1) := src2 251 csBundle(i).lsrc(2) := dest + i.U 252 csBundle(i).ldest := dest + i.U 253 csBundle(i).uopIdx := i.U 254 } 255 } 256 is(UopSplitType.VEC_0XV) { 257 /* 258 FMV.D.X 259 */ 260 csBundle(0).srcType(0) := SrcType.reg 261 csBundle(0).srcType(1) := SrcType.imm 262 csBundle(0).lsrc(1) := 0.U 263 csBundle(0).ldest := FP_TMP_REG_MV.U 264 csBundle(0).fuType := FuType.i2f.U 265 csBundle(0).rfWen := false.B 266 csBundle(0).fpWen := true.B 267 csBundle(0).vecWen := false.B 268 csBundle(0).fpu.isAddSub := false.B 269 csBundle(0).fpu.typeTagIn := FPU.D 270 csBundle(0).fpu.typeTagOut := FPU.D 271 csBundle(0).fpu.fromInt := true.B 272 csBundle(0).fpu.wflags := false.B 273 csBundle(0).fpu.fpWen := true.B 274 csBundle(0).fpu.div := false.B 275 csBundle(0).fpu.sqrt := false.B 276 csBundle(0).fpu.fcvt := false.B 277 /* 278 vfmv.s.f 279 */ 280 csBundle(1).srcType(0) := SrcType.fp 281 csBundle(1).srcType(1) := SrcType.vp 282 csBundle(1).srcType(2) := SrcType.vp 283 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 284 csBundle(1).lsrc(1) := 0.U 285 csBundle(1).lsrc(2) := dest 286 csBundle(1).ldest := dest 287 csBundle(1).fuType := FuType.vppu.U 288 csBundle(1).fuOpType := VpermType.dummy 289 csBundle(1).rfWen := false.B 290 csBundle(1).fpWen := false.B 291 csBundle(1).vecWen := true.B 292 } 293 is(UopSplitType.VEC_VXV) { 294 /* 295 FMV.D.X 296 */ 297 csBundle(0).srcType(0) := SrcType.reg 298 csBundle(0).srcType(1) := SrcType.imm 299 csBundle(0).lsrc(1) := 0.U 300 csBundle(0).ldest := FP_TMP_REG_MV.U 301 csBundle(0).fuType := FuType.i2f.U 302 csBundle(0).rfWen := false.B 303 csBundle(0).fpWen := true.B 304 csBundle(0).vecWen := false.B 305 csBundle(0).fpu.isAddSub := false.B 306 csBundle(0).fpu.typeTagIn := FPU.D 307 csBundle(0).fpu.typeTagOut := FPU.D 308 csBundle(0).fpu.fromInt := true.B 309 csBundle(0).fpu.wflags := false.B 310 csBundle(0).fpu.fpWen := true.B 311 csBundle(0).fpu.div := false.B 312 csBundle(0).fpu.sqrt := false.B 313 csBundle(0).fpu.fcvt := false.B 314 /* 315 LMUL 316 */ 317 for (i <- 0 until MAX_VLMUL) { 318 csBundle(i + 1).srcType(0) := SrcType.fp 319 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 320 csBundle(i + 1).lsrc(1) := src2 + i.U 321 csBundle(i + 1).lsrc(2) := dest + i.U 322 csBundle(i + 1).ldest := dest + i.U 323 csBundle(i + 1).uopIdx := i.U 324 } 325 } 326 is(UopSplitType.VEC_VVW) { 327 for (i <- 0 until MAX_VLMUL / 2) { 328 csBundle(2 * i).lsrc(0) := src1 + i.U 329 csBundle(2 * i).lsrc(1) := src2 + i.U 330 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 331 csBundle(2 * i).ldest := dest + (2 * i).U 332 csBundle(2 * i).uopIdx := (2 * i).U 333 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 334 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 335 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 336 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 337 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 338 } 339 } 340 is(UopSplitType.VEC_WVW) { 341 for (i <- 0 until MAX_VLMUL / 2) { 342 csBundle(2 * i).lsrc(0) := src1 + i.U 343 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 344 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 345 csBundle(2 * i).ldest := dest + (2 * i).U 346 csBundle(2 * i).uopIdx := (2 * i).U 347 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 348 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 349 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 350 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 351 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 352 } 353 } 354 is(UopSplitType.VEC_VXW) { 355 /* 356 FMV.D.X 357 */ 358 csBundle(0).srcType(0) := SrcType.reg 359 csBundle(0).srcType(1) := SrcType.imm 360 csBundle(0).lsrc(1) := 0.U 361 csBundle(0).ldest := FP_TMP_REG_MV.U 362 csBundle(0).fuType := FuType.i2f.U 363 csBundle(0).rfWen := false.B 364 csBundle(0).fpWen := true.B 365 csBundle(0).vecWen := false.B 366 csBundle(0).fpu.isAddSub := false.B 367 csBundle(0).fpu.typeTagIn := FPU.D 368 csBundle(0).fpu.typeTagOut := FPU.D 369 csBundle(0).fpu.fromInt := true.B 370 csBundle(0).fpu.wflags := false.B 371 csBundle(0).fpu.fpWen := true.B 372 csBundle(0).fpu.div := false.B 373 csBundle(0).fpu.sqrt := false.B 374 csBundle(0).fpu.fcvt := false.B 375 376 for (i <- 0 until MAX_VLMUL / 2) { 377 csBundle(2 * i + 1).srcType(0) := SrcType.fp 378 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 379 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 380 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 381 csBundle(2 * i + 1).ldest := dest + (2 * i).U 382 csBundle(2 * i + 1).uopIdx := (2 * i).U 383 csBundle(2 * i + 2).srcType(0) := SrcType.fp 384 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 385 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 386 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 387 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 388 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 389 } 390 } 391 is(UopSplitType.VEC_WXW) { 392 /* 393 FMV.D.X 394 */ 395 csBundle(0).srcType(0) := SrcType.reg 396 csBundle(0).srcType(1) := SrcType.imm 397 csBundle(0).lsrc(1) := 0.U 398 csBundle(0).ldest := FP_TMP_REG_MV.U 399 csBundle(0).fuType := FuType.i2f.U 400 csBundle(0).rfWen := false.B 401 csBundle(0).fpWen := true.B 402 csBundle(0).vecWen := false.B 403 csBundle(0).fpu.isAddSub := false.B 404 csBundle(0).fpu.typeTagIn := FPU.D 405 csBundle(0).fpu.typeTagOut := FPU.D 406 csBundle(0).fpu.fromInt := true.B 407 csBundle(0).fpu.wflags := false.B 408 csBundle(0).fpu.fpWen := true.B 409 csBundle(0).fpu.div := false.B 410 csBundle(0).fpu.sqrt := false.B 411 csBundle(0).fpu.fcvt := false.B 412 413 for (i <- 0 until MAX_VLMUL / 2) { 414 csBundle(2 * i + 1).srcType(0) := SrcType.fp 415 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 417 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 418 csBundle(2 * i + 1).ldest := dest + (2 * i).U 419 csBundle(2 * i + 1).uopIdx := (2 * i).U 420 csBundle(2 * i + 2).srcType(0) := SrcType.fp 421 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 422 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 423 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 424 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 425 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 426 } 427 } 428 is(UopSplitType.VEC_WVV) { 429 for (i <- 0 until MAX_VLMUL / 2) { 430 431 csBundle(2 * i).lsrc(0) := src1 + i.U 432 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 433 csBundle(2 * i).lsrc(2) := dest + i.U 434 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 435 csBundle(2 * i).uopIdx := (2 * i).U 436 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 437 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 438 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 439 csBundle(2 * i + 1).ldest := dest + i.U 440 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 441 } 442 } 443 is(UopSplitType.VEC_WXV) { 444 /* 445 FMV.D.X 446 */ 447 csBundle(0).srcType(0) := SrcType.reg 448 csBundle(0).srcType(1) := SrcType.imm 449 csBundle(0).lsrc(1) := 0.U 450 csBundle(0).ldest := FP_TMP_REG_MV.U 451 csBundle(0).fuType := FuType.i2f.U 452 csBundle(0).rfWen := false.B 453 csBundle(0).fpWen := true.B 454 csBundle(0).vecWen := false.B 455 csBundle(0).fpu.isAddSub := false.B 456 csBundle(0).fpu.typeTagIn := FPU.D 457 csBundle(0).fpu.typeTagOut := FPU.D 458 csBundle(0).fpu.fromInt := true.B 459 csBundle(0).fpu.wflags := false.B 460 csBundle(0).fpu.fpWen := true.B 461 csBundle(0).fpu.div := false.B 462 csBundle(0).fpu.sqrt := false.B 463 csBundle(0).fpu.fcvt := false.B 464 465 for (i <- 0 until MAX_VLMUL / 2) { 466 csBundle(2 * i + 1).srcType(0) := SrcType.fp 467 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 468 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 469 csBundle(2 * i + 1).lsrc(2) := dest + i.U 470 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 471 csBundle(2 * i + 1).uopIdx := (2 * i).U 472 csBundle(2 * i + 2).srcType(0) := SrcType.fp 473 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 474 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 475 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 476 csBundle(2 * i + 2).ldest := dest + i.U 477 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 478 } 479 } 480 is(UopSplitType.VEC_VVM) { 481 csBundle(0).lsrc(2) := dest 482 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 483 csBundle(0).uopIdx := 0.U 484 for(i <- 1 until MAX_VLMUL) { 485 csBundle(i).lsrc(0) := src1 + i.U 486 csBundle(i).lsrc(1) := src2 + i.U 487 csBundle(i).lsrc(2) := VECTOR_TMP_REG_LMUL.U 488 csBundle(i).ldest := VECTOR_TMP_REG_LMUL.U 489 csBundle(i).uopIdx := i.U 490 } 491 csBundle(numOfUop - 1.U).ldest := dest 492 } 493 is(UopSplitType.VEC_VXM) { 494 /* 495 FMV.D.X 496 */ 497 csBundle(0).srcType(0) := SrcType.reg 498 csBundle(0).srcType(1) := SrcType.imm 499 csBundle(0).lsrc(1) := 0.U 500 csBundle(0).ldest := FP_TMP_REG_MV.U 501 csBundle(0).fuType := FuType.i2f.U 502 csBundle(0).rfWen := false.B 503 csBundle(0).fpWen := true.B 504 csBundle(0).vecWen := false.B 505 csBundle(0).fpu.isAddSub := false.B 506 csBundle(0).fpu.typeTagIn := FPU.D 507 csBundle(0).fpu.typeTagOut := FPU.D 508 csBundle(0).fpu.fromInt := true.B 509 csBundle(0).fpu.wflags := false.B 510 csBundle(0).fpu.fpWen := true.B 511 csBundle(0).fpu.div := false.B 512 csBundle(0).fpu.sqrt := false.B 513 csBundle(0).fpu.fcvt := false.B 514 //LMUL 515 csBundle(1).srcType(0) := SrcType.fp 516 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 517 csBundle(1).lsrc(2) := dest 518 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 519 csBundle(1).uopIdx := 0.U 520 for (i <- 1 until MAX_VLMUL) { 521 csBundle(i + 1).srcType(0) := SrcType.fp 522 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 523 csBundle(i + 1).lsrc(1) := src2 + i.U 524 csBundle(i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 525 csBundle(i + 1).ldest := VECTOR_TMP_REG_LMUL.U 526 csBundle(i + 1).uopIdx := i.U 527 } 528 csBundle(numOfUop - 1.U).ldest := dest 529 } 530 is(UopSplitType.VEC_SLIDE1UP) { 531 /* 532 FMV.D.X 533 */ 534 csBundle(0).srcType(0) := SrcType.reg 535 csBundle(0).srcType(1) := SrcType.imm 536 csBundle(0).lsrc(1) := 0.U 537 csBundle(0).ldest := FP_TMP_REG_MV.U 538 csBundle(0).fuType := FuType.i2f.U 539 csBundle(0).rfWen := false.B 540 csBundle(0).fpWen := true.B 541 csBundle(0).vecWen := false.B 542 csBundle(0).fpu.isAddSub := false.B 543 csBundle(0).fpu.typeTagIn := FPU.D 544 csBundle(0).fpu.typeTagOut := FPU.D 545 csBundle(0).fpu.fromInt := true.B 546 csBundle(0).fpu.wflags := false.B 547 csBundle(0).fpu.fpWen := true.B 548 csBundle(0).fpu.div := false.B 549 csBundle(0).fpu.sqrt := false.B 550 csBundle(0).fpu.fcvt := false.B 551 //LMUL 552 csBundle(1).srcType(0) := SrcType.fp 553 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 554 csBundle(1).lsrc(2) := dest 555 csBundle(1).ldest := dest 556 csBundle(1).uopIdx := 0.U 557 for (i <- 1 until MAX_VLMUL) { 558 csBundle(i + 1).srcType(0) := SrcType.vp 559 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 560 csBundle(i + 1).lsrc(1) := src2 + i.U 561 csBundle(i + 1).lsrc(2) := dest + i.U 562 csBundle(i + 1).ldest := dest + i.U 563 csBundle(i + 1).uopIdx := i.U 564 } 565 } 566 is(UopSplitType.VEC_FSLIDE1UP) { 567 //LMUL 568 csBundle(0).srcType(0) := SrcType.fp 569 csBundle(0).lsrc(0) := src1 570 csBundle(0).lsrc(1) := src2 571 csBundle(0).lsrc(2) := dest 572 csBundle(0).ldest := dest 573 csBundle(0).uopIdx := 0.U 574 for (i <- 1 until MAX_VLMUL) { 575 csBundle(i).srcType(0) := SrcType.vp 576 csBundle(i).lsrc(0) := src2 + (i - 1).U 577 csBundle(i).lsrc(1) := src2 + i.U 578 csBundle(i).lsrc(2) := dest + i.U 579 csBundle(i).ldest := dest + i.U 580 csBundle(i).uopIdx := i.U 581 } 582 } 583 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 584 /* 585 FMV.D.X 586 */ 587 csBundle(0).srcType(0) := SrcType.reg 588 csBundle(0).srcType(1) := SrcType.imm 589 csBundle(0).lsrc(1) := 0.U 590 csBundle(0).ldest := FP_TMP_REG_MV.U 591 csBundle(0).fuType := FuType.i2f.U 592 csBundle(0).rfWen := false.B 593 csBundle(0).fpWen := true.B 594 csBundle(0).vecWen := false.B 595 csBundle(0).fpu.isAddSub := false.B 596 csBundle(0).fpu.typeTagIn := FPU.D 597 csBundle(0).fpu.typeTagOut := FPU.D 598 csBundle(0).fpu.fromInt := true.B 599 csBundle(0).fpu.wflags := false.B 600 csBundle(0).fpu.fpWen := true.B 601 csBundle(0).fpu.div := false.B 602 csBundle(0).fpu.sqrt := false.B 603 csBundle(0).fpu.fcvt := false.B 604 //LMUL 605 for (i <- 0 until MAX_VLMUL) { 606 csBundle(2 * i + 1).srcType(0) := SrcType.vp 607 csBundle(2 * i + 1).srcType(1) := SrcType.vp 608 csBundle(2 * i + 1).lsrc(0) := src2 + (i+1).U 609 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 610 csBundle(2 * i + 1).lsrc(2) := dest + i.U 611 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 612 csBundle(2 * i + 1).uopIdx := (2 * i).U 613 if (2 * i + 2 < MAX_VLMUL * 2 ){ 614 csBundle(2 * i + 2).srcType(0) := SrcType.fp 615 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 616 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 617 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 618 csBundle(2 * i + 2).ldest := dest + i.U 619 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 620 } 621 } 622 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 623 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 624 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 625 } 626 is(UopSplitType.VEC_FSLIDE1DOWN) { 627 //LMUL 628 for (i <- 0 until MAX_VLMUL) { 629 csBundle(2 * i).srcType(0) := SrcType.vp 630 csBundle(2 * i).srcType(1) := SrcType.vp 631 csBundle(2 * i).lsrc(0) := src2 + (i+1).U 632 csBundle(2 * i).lsrc(1) := src2 + i.U 633 csBundle(2 * i).lsrc(2) := dest + i.U 634 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 635 csBundle(2 * i).uopIdx := (2 * i).U 636 csBundle(2 * i + 1).srcType(0) := SrcType.fp 637 csBundle(2 * i + 1).lsrc(0) := src1 638 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 639 csBundle(2 * i + 1).ldest := dest + i.U 640 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 641 } 642 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 643 csBundle(numOfUop - 1.U).lsrc(0) := src1 644 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 645 } 646 is(UopSplitType.VEC_VRED) { 647 when(simple.io.enq.vtype.vlmul === "b001".U){ 648 csBundle(0).srcType(2) := SrcType.DC 649 csBundle(0).lsrc(0) := src2 + 1.U 650 csBundle(0).lsrc(1) := src2 651 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 652 csBundle(0).uopIdx := 0.U 653 } 654 when(simple.io.enq.vtype.vlmul === "b010".U) { 655 csBundle(0).srcType(2) := SrcType.DC 656 csBundle(0).lsrc(0) := src2 + 1.U 657 csBundle(0).lsrc(1) := src2 658 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 659 csBundle(0).uopIdx := 0.U 660 661 csBundle(1).srcType(2) := SrcType.DC 662 csBundle(1).lsrc(0) := src2 + 3.U 663 csBundle(1).lsrc(1) := src2 + 2.U 664 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL+1).U 665 csBundle(1).uopIdx := 1.U 666 667 csBundle(2).srcType(2) := SrcType.DC 668 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL+1).U 669 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 670 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL+2).U 671 csBundle(2).uopIdx := 2.U 672 } 673 when(simple.io.enq.vtype.vlmul === "b011".U) { 674 for(i <- 0 until MAX_VLMUL){ 675 if(i < MAX_VLMUL - MAX_VLMUL/2){ 676 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 677 csBundle(i).lsrc(1) := src2 + (i * 2).U 678 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 679 } else if (i < MAX_VLMUL - MAX_VLMUL/4) { 680 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2 + 1).U 681 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL/2)*2).U 682 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 683 }else if (i < MAX_VLMUL - MAX_VLMUL/8) { 684 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 685 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 686 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 687 } 688 csBundle(i).srcType(2) := SrcType.DC 689 csBundle(i).uopIdx := i.U 690 } 691 } 692 when (simple.io.enq.vtype.vlmul.orR()){ 693 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 694 csBundle(numOfUop - 1.U).lsrc(0) := src1 695 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 696 csBundle(numOfUop - 1.U).lsrc(2) := dest 697 csBundle(numOfUop - 1.U).ldest := dest 698 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 699 } 700 } 701 702 is(UopSplitType.VEC_SLIDEUP) { 703 // FMV.D.X 704 csBundle(0).srcType(0) := SrcType.reg 705 csBundle(0).srcType(1) := SrcType.imm 706 csBundle(0).lsrc(1) := 0.U 707 csBundle(0).ldest := FP_TMP_REG_MV.U 708 csBundle(0).fuType := FuType.i2f.U 709 csBundle(0).rfWen := false.B 710 csBundle(0).fpWen := true.B 711 csBundle(0).vecWen := false.B 712 csBundle(0).fpu.isAddSub := false.B 713 csBundle(0).fpu.typeTagIn := FPU.D 714 csBundle(0).fpu.typeTagOut := FPU.D 715 csBundle(0).fpu.fromInt := true.B 716 csBundle(0).fpu.wflags := false.B 717 csBundle(0).fpu.fpWen := true.B 718 csBundle(0).fpu.div := false.B 719 csBundle(0).fpu.sqrt := false.B 720 csBundle(0).fpu.fcvt := false.B 721 // LMUL 722 for(i <- 0 until MAX_VLMUL) 723 for(j <- 0 to i){ 724 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 725 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 726 csBundle(i*(i+1)/2+j+1).srcType(0) := SrcType.fp 727 csBundle(i*(i+1)/2+j+1).lsrc(0) := FP_TMP_REG_MV.U 728 csBundle(i*(i+1)/2+j+1).lsrc(1) := src2 + j.U 729 csBundle(i*(i+1)/2+j+1).lsrc(2) := old_vd 730 csBundle(i*(i+1)/2+j+1).ldest := vd 731 csBundle(i*(i+1)/2+j+1).uopIdx := (i*(i+1)/2+j).U 732 } 733 } 734 735 is(UopSplitType.VEC_ISLIDEUP) { 736 // LMUL 737 for(i <- 0 until MAX_VLMUL) 738 for(j <- 0 to i){ 739 val old_vd = if (j==0) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 740 val vd = if (j==i) {dest + i.U} else (VECTOR_TMP_REG_LMUL+j).U 741 csBundle(i*(i+1)/2+j).lsrc(1) := src2 + j.U 742 csBundle(i*(i+1)/2+j).lsrc(2) := old_vd 743 csBundle(i*(i+1)/2+j).ldest := vd 744 csBundle(i*(i+1)/2+j).uopIdx := (i*(i+1)/2+j).U 745 } 746 } 747 748 is(UopSplitType.VEC_SLIDEDOWN) { 749 // FMV.D.X 750 csBundle(0).srcType(0) := SrcType.reg 751 csBundle(0).srcType(1) := SrcType.imm 752 csBundle(0).lsrc(1) := 0.U 753 csBundle(0).ldest := FP_TMP_REG_MV.U 754 csBundle(0).fuType := FuType.i2f.U 755 csBundle(0).rfWen := false.B 756 csBundle(0).fpWen := true.B 757 csBundle(0).vecWen := false.B 758 csBundle(0).fpu.isAddSub := false.B 759 csBundle(0).fpu.typeTagIn := FPU.D 760 csBundle(0).fpu.typeTagOut := FPU.D 761 csBundle(0).fpu.fromInt := true.B 762 csBundle(0).fpu.wflags := false.B 763 csBundle(0).fpu.fpWen := true.B 764 csBundle(0).fpu.div := false.B 765 csBundle(0).fpu.sqrt := false.B 766 csBundle(0).fpu.fcvt := false.B 767 // LMUL 768 for(i <- 0 until MAX_VLMUL) 769 for(j <- (0 to i).reverse){ 770 when(i.U < lmul){ 771 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 772 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 773 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).srcType(0) := SrcType.fp 774 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(0) := FP_TMP_REG_MV.U 775 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 776 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 777 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 778 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+2).U 779 } 780 } 781 } 782 783 is(UopSplitType.VEC_ISLIDEDOWN) { 784 // LMUL 785 for(i <- 0 until MAX_VLMUL) 786 for(j <- (0 to i).reverse){ 787 when(i.U < lmul){ 788 val old_vd = if (j==0) {dest + lmul -1.U - i.U} else (VECTOR_TMP_REG_LMUL+j-1).U 789 val vd = if (j==i) {dest + lmul - 1.U - i.U} else (VECTOR_TMP_REG_LMUL+j).U 790 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(1) := src2 + lmul - 1.U - j.U 791 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).lsrc(2) := old_vd 792 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).ldest := vd 793 csBundle(numOfUop-(i*(i+1)/2+i-j+1).U).uopIdx := numOfUop-(i*(i+1)/2+i-j+1).U 794 } 795 } 796 } 797 798 is(UopSplitType.VEC_M0X) { 799 // LMUL 800 for (i <- 0 until MAX_VLMUL) { 801 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 802 val ldest = (VECTOR_TMP_REG_LMUL + i).U 803 csBundle(i).srcType(0) := srcType0 804 csBundle(i).srcType(1) := SrcType.vp 805 csBundle(i).rfWen := false.B 806 csBundle(i).vecWen := true.B 807 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 808 csBundle(i).lsrc(1) := src2 809 // csBundle(i).lsrc(2) := dest + i.U DontCare 810 csBundle(i).ldest := ldest 811 csBundle(i).uopIdx := i.U 812 } 813 csBundle(lmul-1.U).vecWen := false.B 814 csBundle(lmul-1.U).fpWen := true.B 815 csBundle(lmul-1.U).ldest := FP_TMP_REG_MV.U 816 // FMV_X_D 817 csBundle(lmul).srcType(0) := SrcType.fp 818 csBundle(lmul).srcType(1) := SrcType.imm 819 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 820 csBundle(lmul).lsrc(1) := 0.U 821 csBundle(lmul).ldest := dest 822 csBundle(lmul).fuType := FuType.fmisc.U 823 csBundle(lmul).rfWen := true.B 824 csBundle(lmul).fpWen := false.B 825 csBundle(lmul).vecWen := false.B 826 csBundle(lmul).fpu.isAddSub := false.B 827 csBundle(lmul).fpu.typeTagIn := FPU.D 828 csBundle(lmul).fpu.typeTagOut := FPU.D 829 csBundle(lmul).fpu.fromInt := false.B 830 csBundle(lmul).fpu.wflags := false.B 831 csBundle(lmul).fpu.fpWen := false.B 832 csBundle(lmul).fpu.div := false.B 833 csBundle(lmul).fpu.sqrt := false.B 834 csBundle(lmul).fpu.fcvt := false.B 835 } 836 837 is(UopSplitType.VEC_MVV) { 838 // LMUL 839 for (i <- 0 until MAX_VLMUL) { 840 val srcType0 = if (i==0) SrcType.DC else SrcType.vp 841 csBundle(i*2+0).srcType(0) := srcType0 842 csBundle(i*2+0).srcType(1) := SrcType.vp 843 csBundle(i*2+0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 844 csBundle(i*2+0).lsrc(1) := src2 845 csBundle(i*2+0).lsrc(2) := dest + i.U 846 csBundle(i*2+0).ldest := dest + i.U 847 csBundle(i*2+0).uopIdx := (i*2+0).U 848 849 csBundle(i*2+1).srcType(0) := srcType0 850 csBundle(i*2+1).srcType(1) := SrcType.vp 851 csBundle(i*2+1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 852 csBundle(i*2+1).lsrc(1) := src2 853 // csBundle(i).lsrc(2) := dest + i.U DontCare 854 csBundle(i*2+1).ldest := (VECTOR_TMP_REG_LMUL + i).U 855 csBundle(i*2+1).uopIdx := (i*2+1).U 856 } 857 } 858 859 is(UopSplitType.VEC_M0X_VFIRST) { 860 // LMUL 861 csBundle(0).rfWen := false.B 862 csBundle(0).fpWen := true.B 863 csBundle(0).ldest := FP_TMP_REG_MV.U 864 // FMV_X_D 865 csBundle(1).srcType(0) := SrcType.fp 866 csBundle(1).srcType(1) := SrcType.imm 867 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 868 csBundle(1).lsrc(1) := 0.U 869 csBundle(1).ldest := dest 870 csBundle(1).fuType := FuType.fmisc.U 871 csBundle(1).rfWen := true.B 872 csBundle(1).fpWen := false.B 873 csBundle(1).vecWen := false.B 874 csBundle(1).fpu.isAddSub := false.B 875 csBundle(1).fpu.typeTagIn := FPU.D 876 csBundle(1).fpu.typeTagOut := FPU.D 877 csBundle(1).fpu.fromInt := false.B 878 csBundle(1).fpu.wflags := false.B 879 csBundle(1).fpu.fpWen := false.B 880 csBundle(1).fpu.div := false.B 881 csBundle(1).fpu.sqrt := false.B 882 csBundle(1).fpu.fcvt := false.B 883 } 884 } 885 886 //uops dispatch 887 val normal :: ext :: Nil = Enum(2) 888 val stateReg = RegInit(normal) 889 val uopRes = RegInit(0.U) 890 891 //readyFromRename Counter 892 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 893 894 switch(stateReg) { 895 is(normal) { 896 stateReg := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), ext, normal) 897 } 898 is(ext) { 899 stateReg := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), ext, normal) 900 } 901 } 902 903 val uopRes0 = Mux(stateReg === normal, numOfUop, uopRes) 904 val uopResJudge = Mux(stateReg === normal, 905 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 906 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 907 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 908 909 for(i <- 0 until RenameWidth) { 910 decodedInsts(i) := MuxCase(csBundle(i), Seq( 911 (stateReg === normal) -> csBundle(i), 912 (stateReg === ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 913 )) 914 } 915 916 917 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 918 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 919 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 920 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 921 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 922 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 923 notInfVec(0) := true.B 924 925 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 926 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 927 1.U) 928 validToRename.zipWithIndex.foreach{ 929 case(dst, i) => 930 dst := MuxCase(false.B, Seq( 931 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 932 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 933 )) 934 } 935 936 readyToIBuf.zipWithIndex.foreach { 937 case (dst, i) => 938 dst := MuxCase(true.B, Seq( 939 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 940 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 941 )) 942 } 943 944 io.deq.decodedInsts := decodedInsts 945 io.deq.isVset := isVset_u 946 io.deq.complexNum := complexNum 947 io.deq.validToRename := validToRename 948 io.deq.readyToIBuf := readyToIBuf 949 950} 951