1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 71 staticInst := io.enq.staticInst 72 private val inst: XSInstBitFields = staticInst.instr.asTypeOf(new XSInstBitFields) 73 74 val src1 = Cat(0.U(1.W), inst.RS1) 75 val src2 = Cat(0.U(1.W), inst.RS2) 76 val dest = Cat(0.U(1.W), inst.RD) 77 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 88 val lmul = Wire(UInt(4.W)) 89 val isVsetSimple = Wire(Bool()) 90 91 //pre decode 92 val simple = Module(new DecodeUnit) 93 simple.io.enq.ctrlFlow := staticInst 94 simple.io.enq.vtype := io.vtype 95 simple.io.csrCtrl := io.csrCtrl 96 decodedInstsSimple := simple.io.deq.decodedInst 97 lmul := simple.io.deq.uopInfo.lmul 98 isVsetSimple := simple.io.deq.decodedInst.isVset 99 when(isVsetSimple) { 100 when(dest === 0.U && src1 === 0.U) { 101 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 102 }.elsewhen(src1 === 0.U) { 103 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 104 } 105 when(io.vtype.illegal){ 106 decodedInstsSimple.flushPipe := true.B 107 } 108 } 109 //Type of uop Div 110 val typeOfSplit = decodedInstsSimple.uopSplitType 111 112 when(typeOfSplit === UopSplitType.DIR) { 113 numOfUop := Mux(dest =/= 0.U, 2.U, 114 Mux(src1 =/= 0.U, 1.U, 115 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 116 } .otherwise { 117 numOfUop := simple.io.deq.uopInfo.numOfUop 118 } 119 120 121 //uop div up to maxUopSize 122 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 123 csBundle.map { case dst => 124 dst := decodedInstsSimple 125 dst.firstUop := false.B 126 dst.lastUop := false.B 127 } 128 129 csBundle(0).numUops := numOfUop 130 csBundle(0).firstUop := true.B 131 csBundle(numOfUop - 1.U).lastUop := true.B 132 133 switch(typeOfSplit) { 134 is(UopSplitType.DIR) { 135 when(isVsetSimple) { 136 when(dest =/= 0.U) { 137 csBundle(0).fuType := FuType.vsetiwi.U 138 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 139 csBundle(0).flushPipe := false.B 140 csBundle(0).rfWen := true.B 141 csBundle(0).vecWen := false.B 142 csBundle(1).ldest := VCONFIG_IDX.U 143 csBundle(1).rfWen := false.B 144 csBundle(1).vecWen := true.B 145 }.elsewhen(src1 =/= 0.U) { 146 csBundle(0).ldest := VCONFIG_IDX.U 147 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 148 csBundle(0).fuType := FuType.vsetfwf.U 149 csBundle(0).srcType(0) := SrcType.vp 150 csBundle(0).lsrc(0) := VCONFIG_IDX.U 151 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 152 csBundle(0).srcType(0) := SrcType.reg 153 csBundle(0).srcType(1) := SrcType.imm 154 csBundle(0).lsrc(1) := 0.U 155 csBundle(0).ldest := FP_TMP_REG_MV.U 156 csBundle(0).fuType := FuType.i2f.U 157 csBundle(0).rfWen := false.B 158 csBundle(0).fpWen := true.B 159 csBundle(0).vecWen := false.B 160 csBundle(0).fpu.isAddSub := false.B 161 csBundle(0).fpu.typeTagIn := FPU.D 162 csBundle(0).fpu.typeTagOut := FPU.D 163 csBundle(0).fpu.fromInt := true.B 164 csBundle(0).fpu.wflags := false.B 165 csBundle(0).fpu.fpWen := true.B 166 csBundle(0).fpu.div := false.B 167 csBundle(0).fpu.sqrt := false.B 168 csBundle(0).fpu.fcvt := false.B 169 csBundle(0).flushPipe := false.B 170 csBundle(1).fuType := FuType.vsetfwf.U 171 csBundle(1).srcType(0) := SrcType.vp 172 csBundle(1).lsrc(0) := VCONFIG_IDX.U 173 csBundle(1).srcType(1) := SrcType.fp 174 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 175 csBundle(1).ldest := VCONFIG_IDX.U 176 } 177 } 178 } 179 is(UopSplitType.VEC_VVV) { 180 for (i <- 0 until MAX_VLMUL) { 181 csBundle(i).lsrc(0) := src1 + i.U 182 csBundle(i).lsrc(1) := src2 + i.U 183 csBundle(i).lsrc(2) := dest + i.U 184 csBundle(i).ldest := dest + i.U 185 csBundle(i).uopIdx := i.U 186 } 187 } 188 is(UopSplitType.VEC_EXT2) { 189 for (i <- 0 until MAX_VLMUL / 2) { 190 csBundle(2 * i).lsrc(1) := src2 + i.U 191 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 192 csBundle(2 * i).ldest := dest + (2 * i).U 193 csBundle(2 * i).uopIdx := (2 * i).U 194 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 195 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 196 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 197 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 198 } 199 } 200 is(UopSplitType.VEC_EXT4) { 201 for (i <- 0 until MAX_VLMUL / 4) { 202 csBundle(4 * i).lsrc(1) := src2 + i.U 203 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 204 csBundle(4 * i).ldest := dest + (4 * i).U 205 csBundle(4 * i).uopIdx := (4 * i).U 206 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 207 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 208 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 209 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 210 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 211 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 212 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 213 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 214 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 215 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 216 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 217 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 218 } 219 } 220 is(UopSplitType.VEC_EXT8) { 221 for (i <- 0 until MAX_VLMUL) { 222 csBundle(i).lsrc(1) := src2 223 csBundle(i).lsrc(2) := dest + i.U 224 csBundle(i).ldest := dest + i.U 225 csBundle(i).uopIdx := i.U 226 } 227 } 228 is(UopSplitType.VEC_0XV) { 229 /* 230 FMV.D.X 231 */ 232 csBundle(0).srcType(0) := SrcType.reg 233 csBundle(0).srcType(1) := SrcType.imm 234 csBundle(0).lsrc(1) := 0.U 235 csBundle(0).ldest := FP_TMP_REG_MV.U 236 csBundle(0).fuType := FuType.i2f.U 237 csBundle(0).rfWen := false.B 238 csBundle(0).fpWen := true.B 239 csBundle(0).vecWen := false.B 240 csBundle(0).fpu.isAddSub := false.B 241 csBundle(0).fpu.typeTagIn := FPU.D 242 csBundle(0).fpu.typeTagOut := FPU.D 243 csBundle(0).fpu.fromInt := true.B 244 csBundle(0).fpu.wflags := false.B 245 csBundle(0).fpu.fpWen := true.B 246 csBundle(0).fpu.div := false.B 247 csBundle(0).fpu.sqrt := false.B 248 csBundle(0).fpu.fcvt := false.B 249 /* 250 vfmv.s.f 251 */ 252 csBundle(1).srcType(0) := SrcType.fp 253 csBundle(1).srcType(1) := SrcType.vp 254 csBundle(1).srcType(2) := SrcType.vp 255 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 256 csBundle(1).lsrc(1) := 0.U 257 csBundle(1).lsrc(2) := dest 258 csBundle(1).ldest := dest 259 csBundle(1).fuType := FuType.vppu.U 260 csBundle(1).fuOpType := VpermType.dummy 261 csBundle(1).rfWen := false.B 262 csBundle(1).fpWen := false.B 263 csBundle(1).vecWen := true.B 264 } 265 is(UopSplitType.VEC_VXV) { 266 /* 267 FMV.D.X 268 */ 269 csBundle(0).srcType(0) := SrcType.reg 270 csBundle(0).srcType(1) := SrcType.imm 271 csBundle(0).lsrc(1) := 0.U 272 csBundle(0).ldest := FP_TMP_REG_MV.U 273 csBundle(0).fuType := FuType.i2f.U 274 csBundle(0).rfWen := false.B 275 csBundle(0).fpWen := true.B 276 csBundle(0).vecWen := false.B 277 csBundle(0).fpu.isAddSub := false.B 278 csBundle(0).fpu.typeTagIn := FPU.D 279 csBundle(0).fpu.typeTagOut := FPU.D 280 csBundle(0).fpu.fromInt := true.B 281 csBundle(0).fpu.wflags := false.B 282 csBundle(0).fpu.fpWen := true.B 283 csBundle(0).fpu.div := false.B 284 csBundle(0).fpu.sqrt := false.B 285 csBundle(0).fpu.fcvt := false.B 286 /* 287 LMUL 288 */ 289 for (i <- 0 until MAX_VLMUL) { 290 csBundle(i + 1).srcType(0) := SrcType.fp 291 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 292 csBundle(i + 1).lsrc(1) := src2 + i.U 293 csBundle(i + 1).lsrc(2) := dest + i.U 294 csBundle(i + 1).ldest := dest + i.U 295 csBundle(i + 1).uopIdx := i.U 296 } 297 } 298 is(UopSplitType.VEC_VVW) { 299 for (i <- 0 until MAX_VLMUL / 2) { 300 csBundle(2 * i).lsrc(0) := src1 + i.U 301 csBundle(2 * i).lsrc(1) := src2 + i.U 302 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 303 csBundle(2 * i).ldest := dest + (2 * i).U 304 csBundle(2 * i).uopIdx := (2 * i).U 305 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 306 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 307 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 308 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 309 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 310 } 311 } 312 is(UopSplitType.VEC_WVW) { 313 for (i <- 0 until MAX_VLMUL / 2) { 314 csBundle(2 * i).lsrc(0) := src1 + i.U 315 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 316 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 317 csBundle(2 * i).ldest := dest + (2 * i).U 318 csBundle(2 * i).uopIdx := (2 * i).U 319 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 320 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 321 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 322 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 323 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 324 } 325 } 326 is(UopSplitType.VEC_VXW) { 327 /* 328 FMV.D.X 329 */ 330 csBundle(0).srcType(0) := SrcType.reg 331 csBundle(0).srcType(1) := SrcType.imm 332 csBundle(0).lsrc(1) := 0.U 333 csBundle(0).ldest := FP_TMP_REG_MV.U 334 csBundle(0).fuType := FuType.i2f.U 335 csBundle(0).rfWen := false.B 336 csBundle(0).fpWen := true.B 337 csBundle(0).vecWen := false.B 338 csBundle(0).fpu.isAddSub := false.B 339 csBundle(0).fpu.typeTagIn := FPU.D 340 csBundle(0).fpu.typeTagOut := FPU.D 341 csBundle(0).fpu.fromInt := true.B 342 csBundle(0).fpu.wflags := false.B 343 csBundle(0).fpu.fpWen := true.B 344 csBundle(0).fpu.div := false.B 345 csBundle(0).fpu.sqrt := false.B 346 csBundle(0).fpu.fcvt := false.B 347 348 for (i <- 0 until MAX_VLMUL / 2) { 349 csBundle(2 * i + 1).srcType(0) := SrcType.fp 350 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 351 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 352 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 353 csBundle(2 * i + 1).ldest := dest + (2 * i).U 354 csBundle(2 * i + 1).uopIdx := (2 * i).U 355 csBundle(2 * i + 2).srcType(0) := SrcType.fp 356 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 357 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 358 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 359 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 360 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 361 } 362 } 363 is(UopSplitType.VEC_WXW) { 364 /* 365 FMV.D.X 366 */ 367 csBundle(0).srcType(0) := SrcType.reg 368 csBundle(0).srcType(1) := SrcType.imm 369 csBundle(0).lsrc(1) := 0.U 370 csBundle(0).ldest := FP_TMP_REG_MV.U 371 csBundle(0).fuType := FuType.i2f.U 372 csBundle(0).rfWen := false.B 373 csBundle(0).fpWen := true.B 374 csBundle(0).vecWen := false.B 375 csBundle(0).fpu.isAddSub := false.B 376 csBundle(0).fpu.typeTagIn := FPU.D 377 csBundle(0).fpu.typeTagOut := FPU.D 378 csBundle(0).fpu.fromInt := true.B 379 csBundle(0).fpu.wflags := false.B 380 csBundle(0).fpu.fpWen := true.B 381 csBundle(0).fpu.div := false.B 382 csBundle(0).fpu.sqrt := false.B 383 csBundle(0).fpu.fcvt := false.B 384 385 for (i <- 0 until MAX_VLMUL / 2) { 386 csBundle(2 * i + 1).srcType(0) := SrcType.fp 387 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 388 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 389 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 390 csBundle(2 * i + 1).ldest := dest + (2 * i).U 391 csBundle(2 * i + 1).uopIdx := (2 * i).U 392 csBundle(2 * i + 2).srcType(0) := SrcType.fp 393 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 394 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 395 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 396 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 397 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 398 } 399 } 400 is(UopSplitType.VEC_WVV) { 401 for (i <- 0 until MAX_VLMUL / 2) { 402 403 csBundle(2 * i).lsrc(0) := src1 + i.U 404 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 405 csBundle(2 * i).lsrc(2) := dest + i.U 406 csBundle(2 * i).ldest := dest + i.U 407 csBundle(2 * i).uopIdx := (2 * i).U 408 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 409 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 410 csBundle(2 * i + 1).lsrc(2) := dest + i.U 411 csBundle(2 * i + 1).ldest := dest + i.U 412 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 413 } 414 } 415 is(UopSplitType.VEC_WXV) { 416 /* 417 FMV.D.X 418 */ 419 csBundle(0).srcType(0) := SrcType.reg 420 csBundle(0).srcType(1) := SrcType.imm 421 csBundle(0).lsrc(1) := 0.U 422 csBundle(0).ldest := FP_TMP_REG_MV.U 423 csBundle(0).fuType := FuType.i2f.U 424 csBundle(0).rfWen := false.B 425 csBundle(0).fpWen := true.B 426 csBundle(0).vecWen := false.B 427 csBundle(0).fpu.isAddSub := false.B 428 csBundle(0).fpu.typeTagIn := FPU.D 429 csBundle(0).fpu.typeTagOut := FPU.D 430 csBundle(0).fpu.fromInt := true.B 431 csBundle(0).fpu.wflags := false.B 432 csBundle(0).fpu.fpWen := true.B 433 csBundle(0).fpu.div := false.B 434 csBundle(0).fpu.sqrt := false.B 435 csBundle(0).fpu.fcvt := false.B 436 437 for (i <- 0 until MAX_VLMUL / 2) { 438 csBundle(2 * i + 1).srcType(0) := SrcType.fp 439 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 440 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 441 csBundle(2 * i + 1).lsrc(2) := dest + i.U 442 csBundle(2 * i + 1).ldest := dest + i.U 443 csBundle(2 * i + 1).uopIdx := (2 * i).U 444 csBundle(2 * i + 2).srcType(0) := SrcType.fp 445 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 446 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 447 csBundle(2 * i + 2).lsrc(2) := dest + i.U 448 csBundle(2 * i + 2).ldest := dest + i.U 449 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 450 } 451 } 452 is(UopSplitType.VEC_VVM) { 453 csBundle(0).lsrc(2) := dest 454 csBundle(0).ldest := dest 455 csBundle(0).uopIdx := 0.U 456 for (i <- 1 until MAX_VLMUL) { 457 csBundle(i).lsrc(0) := src1 + i.U 458 csBundle(i).lsrc(1) := src2 + i.U 459 csBundle(i).lsrc(2) := dest 460 csBundle(i).ldest := dest 461 csBundle(i).uopIdx := i.U 462 } 463 csBundle(numOfUop - 1.U).ldest := dest 464 } 465 is(UopSplitType.VEC_VXM) { 466 /* 467 FMV.D.X 468 */ 469 csBundle(0).srcType(0) := SrcType.reg 470 csBundle(0).srcType(1) := SrcType.imm 471 csBundle(0).lsrc(1) := 0.U 472 csBundle(0).ldest := FP_TMP_REG_MV.U 473 csBundle(0).fuType := FuType.i2f.U 474 csBundle(0).rfWen := false.B 475 csBundle(0).fpWen := true.B 476 csBundle(0).vecWen := false.B 477 csBundle(0).fpu.isAddSub := false.B 478 csBundle(0).fpu.typeTagIn := FPU.D 479 csBundle(0).fpu.typeTagOut := FPU.D 480 csBundle(0).fpu.fromInt := true.B 481 csBundle(0).fpu.wflags := false.B 482 csBundle(0).fpu.fpWen := true.B 483 csBundle(0).fpu.div := false.B 484 csBundle(0).fpu.sqrt := false.B 485 csBundle(0).fpu.fcvt := false.B 486 //LMUL 487 csBundle(1).srcType(0) := SrcType.fp 488 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 489 csBundle(1).lsrc(2) := dest 490 csBundle(1).ldest := dest 491 csBundle(1).uopIdx := 0.U 492 for (i <- 1 until MAX_VLMUL) { 493 csBundle(i + 1).srcType(0) := SrcType.fp 494 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 495 csBundle(i + 1).lsrc(1) := src2 + i.U 496 csBundle(i + 1).lsrc(2) := dest 497 csBundle(i + 1).ldest := dest 498 csBundle(i + 1).uopIdx := i.U 499 } 500 csBundle(numOfUop - 1.U).ldest := dest 501 } 502 is(UopSplitType.VEC_SLIDE1UP) { 503 /* 504 FMV.D.X 505 */ 506 csBundle(0).srcType(0) := SrcType.reg 507 csBundle(0).srcType(1) := SrcType.imm 508 csBundle(0).lsrc(1) := 0.U 509 csBundle(0).ldest := FP_TMP_REG_MV.U 510 csBundle(0).fuType := FuType.i2f.U 511 csBundle(0).rfWen := false.B 512 csBundle(0).fpWen := true.B 513 csBundle(0).vecWen := false.B 514 csBundle(0).fpu.isAddSub := false.B 515 csBundle(0).fpu.typeTagIn := FPU.D 516 csBundle(0).fpu.typeTagOut := FPU.D 517 csBundle(0).fpu.fromInt := true.B 518 csBundle(0).fpu.wflags := false.B 519 csBundle(0).fpu.fpWen := true.B 520 csBundle(0).fpu.div := false.B 521 csBundle(0).fpu.sqrt := false.B 522 csBundle(0).fpu.fcvt := false.B 523 //LMUL 524 csBundle(1).srcType(0) := SrcType.fp 525 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 526 csBundle(1).lsrc(2) := dest 527 csBundle(1).ldest := dest 528 csBundle(1).uopIdx := 0.U 529 for (i <- 1 until MAX_VLMUL) { 530 csBundle(i + 1).srcType(0) := SrcType.vp 531 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 532 csBundle(i + 1).lsrc(1) := src2 + i.U 533 csBundle(i + 1).lsrc(2) := dest + i.U 534 csBundle(i + 1).ldest := dest + i.U 535 csBundle(i + 1).uopIdx := i.U 536 } 537 } 538 is(UopSplitType.VEC_FSLIDE1UP) { 539 //LMUL 540 csBundle(0).srcType(0) := SrcType.fp 541 csBundle(0).lsrc(0) := src1 542 csBundle(0).lsrc(1) := src2 543 csBundle(0).lsrc(2) := dest 544 csBundle(0).ldest := dest 545 csBundle(0).uopIdx := 0.U 546 for (i <- 1 until MAX_VLMUL) { 547 csBundle(i).srcType(0) := SrcType.vp 548 csBundle(i).lsrc(0) := src2 + (i - 1).U 549 csBundle(i).lsrc(1) := src2 + i.U 550 csBundle(i).lsrc(2) := dest + i.U 551 csBundle(i).ldest := dest + i.U 552 csBundle(i).uopIdx := i.U 553 } 554 } 555 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 556 /* 557 FMV.D.X 558 */ 559 csBundle(0).srcType(0) := SrcType.reg 560 csBundle(0).srcType(1) := SrcType.imm 561 csBundle(0).lsrc(1) := 0.U 562 csBundle(0).ldest := FP_TMP_REG_MV.U 563 csBundle(0).fuType := FuType.i2f.U 564 csBundle(0).rfWen := false.B 565 csBundle(0).fpWen := true.B 566 csBundle(0).vecWen := false.B 567 csBundle(0).fpu.isAddSub := false.B 568 csBundle(0).fpu.typeTagIn := FPU.D 569 csBundle(0).fpu.typeTagOut := FPU.D 570 csBundle(0).fpu.fromInt := true.B 571 csBundle(0).fpu.wflags := false.B 572 csBundle(0).fpu.fpWen := true.B 573 csBundle(0).fpu.div := false.B 574 csBundle(0).fpu.sqrt := false.B 575 csBundle(0).fpu.fcvt := false.B 576 //LMUL 577 for (i <- 0 until MAX_VLMUL) { 578 csBundle(2 * i + 1).srcType(0) := SrcType.vp 579 csBundle(2 * i + 1).srcType(1) := SrcType.vp 580 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 581 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 582 csBundle(2 * i + 1).lsrc(2) := dest + i.U 583 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 584 csBundle(2 * i + 1).uopIdx := (2 * i).U 585 if (2 * i + 2 < MAX_VLMUL * 2) { 586 csBundle(2 * i + 2).srcType(0) := SrcType.fp 587 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 588 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 589 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 590 csBundle(2 * i + 2).ldest := dest + i.U 591 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 592 } 593 } 594 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 595 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 596 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 597 } 598 is(UopSplitType.VEC_FSLIDE1DOWN) { 599 //LMUL 600 for (i <- 0 until MAX_VLMUL) { 601 csBundle(2 * i).srcType(0) := SrcType.vp 602 csBundle(2 * i).srcType(1) := SrcType.vp 603 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 604 csBundle(2 * i).lsrc(1) := src2 + i.U 605 csBundle(2 * i).lsrc(2) := dest + i.U 606 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 607 csBundle(2 * i).uopIdx := (2 * i).U 608 csBundle(2 * i + 1).srcType(0) := SrcType.fp 609 csBundle(2 * i + 1).lsrc(0) := src1 610 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 611 csBundle(2 * i + 1).ldest := dest + i.U 612 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 613 } 614 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 615 csBundle(numOfUop - 1.U).lsrc(0) := src1 616 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 617 } 618 is(UopSplitType.VEC_VRED) { 619 when(simple.io.enq.vtype.vlmul === "b001".U) { 620 csBundle(0).srcType(2) := SrcType.DC 621 csBundle(0).lsrc(0) := src2 + 1.U 622 csBundle(0).lsrc(1) := src2 623 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 624 csBundle(0).uopIdx := 0.U 625 } 626 when(simple.io.enq.vtype.vlmul === "b010".U) { 627 csBundle(0).srcType(2) := SrcType.DC 628 csBundle(0).lsrc(0) := src2 + 1.U 629 csBundle(0).lsrc(1) := src2 630 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 631 csBundle(0).uopIdx := 0.U 632 633 csBundle(1).srcType(2) := SrcType.DC 634 csBundle(1).lsrc(0) := src2 + 3.U 635 csBundle(1).lsrc(1) := src2 + 2.U 636 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 637 csBundle(1).uopIdx := 1.U 638 639 csBundle(2).srcType(2) := SrcType.DC 640 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 641 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 642 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 643 csBundle(2).uopIdx := 2.U 644 } 645 when(simple.io.enq.vtype.vlmul === "b011".U) { 646 for (i <- 0 until MAX_VLMUL) { 647 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 648 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 649 csBundle(i).lsrc(1) := src2 + (i * 2).U 650 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 651 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 652 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 653 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 654 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 655 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 656 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 657 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 658 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 659 } 660 csBundle(i).srcType(2) := SrcType.DC 661 csBundle(i).uopIdx := i.U 662 } 663 } 664 when(simple.io.enq.vtype.vlmul.orR()) { 665 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 666 csBundle(numOfUop - 1.U).lsrc(0) := src1 667 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 668 csBundle(numOfUop - 1.U).lsrc(2) := dest 669 csBundle(numOfUop - 1.U).ldest := dest 670 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 671 } 672 } 673 674 is(UopSplitType.VEC_SLIDEUP) { 675 // FMV.D.X 676 csBundle(0).srcType(0) := SrcType.reg 677 csBundle(0).srcType(1) := SrcType.imm 678 csBundle(0).lsrc(1) := 0.U 679 csBundle(0).ldest := FP_TMP_REG_MV.U 680 csBundle(0).fuType := FuType.i2f.U 681 csBundle(0).rfWen := false.B 682 csBundle(0).fpWen := true.B 683 csBundle(0).vecWen := false.B 684 csBundle(0).fpu.isAddSub := false.B 685 csBundle(0).fpu.typeTagIn := FPU.D 686 csBundle(0).fpu.typeTagOut := FPU.D 687 csBundle(0).fpu.fromInt := true.B 688 csBundle(0).fpu.wflags := false.B 689 csBundle(0).fpu.fpWen := true.B 690 csBundle(0).fpu.div := false.B 691 csBundle(0).fpu.sqrt := false.B 692 csBundle(0).fpu.fcvt := false.B 693 // LMUL 694 for (i <- 0 until MAX_VLMUL) 695 for (j <- 0 to i) { 696 val old_vd = if (j == 0) { 697 dest + i.U 698 } else (VECTOR_TMP_REG_LMUL + j - 1).U 699 val vd = if (j == i) { 700 dest + i.U 701 } else (VECTOR_TMP_REG_LMUL + j).U 702 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 703 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 704 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 705 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 706 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 707 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 708 } 709 } 710 711 is(UopSplitType.VEC_ISLIDEUP) { 712 // LMUL 713 for (i <- 0 until MAX_VLMUL) 714 for (j <- 0 to i) { 715 val old_vd = if (j == 0) { 716 dest + i.U 717 } else (VECTOR_TMP_REG_LMUL + j - 1).U 718 val vd = if (j == i) { 719 dest + i.U 720 } else (VECTOR_TMP_REG_LMUL + j).U 721 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 722 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 723 csBundle(i * (i + 1) / 2 + j).ldest := vd 724 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 725 } 726 } 727 728 is(UopSplitType.VEC_SLIDEDOWN) { 729 // FMV.D.X 730 csBundle(0).srcType(0) := SrcType.reg 731 csBundle(0).srcType(1) := SrcType.imm 732 csBundle(0).lsrc(1) := 0.U 733 csBundle(0).ldest := FP_TMP_REG_MV.U 734 csBundle(0).fuType := FuType.i2f.U 735 csBundle(0).rfWen := false.B 736 csBundle(0).fpWen := true.B 737 csBundle(0).vecWen := false.B 738 csBundle(0).fpu.isAddSub := false.B 739 csBundle(0).fpu.typeTagIn := FPU.D 740 csBundle(0).fpu.typeTagOut := FPU.D 741 csBundle(0).fpu.fromInt := true.B 742 csBundle(0).fpu.wflags := false.B 743 csBundle(0).fpu.fpWen := true.B 744 csBundle(0).fpu.div := false.B 745 csBundle(0).fpu.sqrt := false.B 746 csBundle(0).fpu.fcvt := false.B 747 // LMUL 748 for (i <- 0 until MAX_VLMUL) 749 for (j <- (0 to i).reverse) { 750 when(i.U < lmul) { 751 val old_vd = if (j == 0) { 752 dest + lmul - 1.U - i.U 753 } else (VECTOR_TMP_REG_LMUL + j - 1).U 754 val vd = if (j == i) { 755 dest + lmul - 1.U - i.U 756 } else (VECTOR_TMP_REG_LMUL + j).U 757 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 758 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 759 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 760 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 761 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 762 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 763 } 764 } 765 } 766 767 is(UopSplitType.VEC_ISLIDEDOWN) { 768 // LMUL 769 for (i <- 0 until MAX_VLMUL) 770 for (j <- (0 to i).reverse) { 771 when(i.U < lmul) { 772 val old_vd = if (j == 0) { 773 dest + lmul - 1.U - i.U 774 } else (VECTOR_TMP_REG_LMUL + j - 1).U 775 val vd = if (j == i) { 776 dest + lmul - 1.U - i.U 777 } else (VECTOR_TMP_REG_LMUL + j).U 778 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 779 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 780 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 781 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 782 } 783 } 784 } 785 786 is(UopSplitType.VEC_M0X) { 787 // LMUL 788 for (i <- 0 until MAX_VLMUL) { 789 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 790 val ldest = (VECTOR_TMP_REG_LMUL + i).U 791 csBundle(i).srcType(0) := srcType0 792 csBundle(i).srcType(1) := SrcType.vp 793 csBundle(i).rfWen := false.B 794 csBundle(i).vecWen := true.B 795 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 796 csBundle(i).lsrc(1) := src2 797 // csBundle(i).lsrc(2) := dest + i.U DontCare 798 csBundle(i).ldest := ldest 799 csBundle(i).uopIdx := i.U 800 } 801 csBundle(lmul - 1.U).vecWen := false.B 802 csBundle(lmul - 1.U).fpWen := true.B 803 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 804 // FMV_X_D 805 csBundle(lmul).srcType(0) := SrcType.fp 806 csBundle(lmul).srcType(1) := SrcType.imm 807 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 808 csBundle(lmul).lsrc(1) := 0.U 809 csBundle(lmul).ldest := dest 810 csBundle(lmul).fuType := FuType.fmisc.U 811 csBundle(lmul).rfWen := true.B 812 csBundle(lmul).fpWen := false.B 813 csBundle(lmul).vecWen := false.B 814 csBundle(lmul).fpu.isAddSub := false.B 815 csBundle(lmul).fpu.typeTagIn := FPU.D 816 csBundle(lmul).fpu.typeTagOut := FPU.D 817 csBundle(lmul).fpu.fromInt := false.B 818 csBundle(lmul).fpu.wflags := false.B 819 csBundle(lmul).fpu.fpWen := false.B 820 csBundle(lmul).fpu.div := false.B 821 csBundle(lmul).fpu.sqrt := false.B 822 csBundle(lmul).fpu.fcvt := false.B 823 } 824 825 is(UopSplitType.VEC_MVV) { 826 // LMUL 827 for (i <- 0 until MAX_VLMUL) { 828 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 829 csBundle(i * 2 + 0).srcType(0) := srcType0 830 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 831 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 832 csBundle(i * 2 + 0).lsrc(1) := src2 833 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 834 csBundle(i * 2 + 0).ldest := dest + i.U 835 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 836 837 csBundle(i * 2 + 1).srcType(0) := srcType0 838 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 839 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 840 csBundle(i * 2 + 1).lsrc(1) := src2 841 // csBundle(i).lsrc(2) := dest + i.U DontCare 842 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 843 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 844 } 845 } 846 847 is(UopSplitType.VEC_M0X_VFIRST) { 848 // LMUL 849 csBundle(0).rfWen := false.B 850 csBundle(0).fpWen := true.B 851 csBundle(0).ldest := FP_TMP_REG_MV.U 852 // FMV_X_D 853 csBundle(1).srcType(0) := SrcType.fp 854 csBundle(1).srcType(1) := SrcType.imm 855 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 856 csBundle(1).lsrc(1) := 0.U 857 csBundle(1).ldest := dest 858 csBundle(1).fuType := FuType.fmisc.U 859 csBundle(1).rfWen := true.B 860 csBundle(1).fpWen := false.B 861 csBundle(1).vecWen := false.B 862 csBundle(1).fpu.isAddSub := false.B 863 csBundle(1).fpu.typeTagIn := FPU.D 864 csBundle(1).fpu.typeTagOut := FPU.D 865 csBundle(1).fpu.fromInt := false.B 866 csBundle(1).fpu.wflags := false.B 867 csBundle(1).fpu.fpWen := false.B 868 csBundle(1).fpu.div := false.B 869 csBundle(1).fpu.sqrt := false.B 870 csBundle(1).fpu.fcvt := false.B 871 } 872 is(UopSplitType.VEC_VWW) { 873 for (i <- 0 until MAX_VLMUL*2) { 874 when(i.U < lmul){ 875 csBundle(i).srcType(2) := SrcType.DC 876 csBundle(i).lsrc(0) := src2 + i.U 877 csBundle(i).lsrc(1) := src2 + i.U 878 // csBundle(i).lsrc(2) := dest + (2 * i).U 879 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 880 csBundle(i).uopIdx := i.U 881 } otherwise { 882 csBundle(i).srcType(2) := SrcType.DC 883 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 884 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 885 // csBundle(i).lsrc(2) := dest + (2 * i).U 886 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 887 csBundle(i).uopIdx := i.U 888 } 889 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 890 csBundle(numOfUop-1.U).lsrc(0) := src1 891 csBundle(numOfUop-1.U).lsrc(2) := dest 892 csBundle(numOfUop-1.U).ldest := dest 893 } 894 } 895 is(UopSplitType.VEC_RGATHER) { 896 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 897 for (i <- 0 until len) 898 for (j <- 0 until len) { 899 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 900 // csBundle(i * len + j).srcType(1) := SrcType.vp 901 // csBundle(i * len + j).srcType(2) := SrcType.vp 902 csBundle(i * len + j).lsrc(0) := src1 + i.U 903 csBundle(i * len + j).lsrc(1) := src2 + j.U 904 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 905 csBundle(i * len + j).lsrc(2) := vd_old 906 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 907 csBundle(i * len + j).ldest := vd 908 csBundle(i * len + j).uopIdx := (i * len + j).U 909 } 910 } 911 switch(simple.io.enq.vtype.vlmul) { 912 is("b001".U ){ 913 genCsBundle_VEC_RGATHER(2) 914 } 915 is("b010".U ){ 916 genCsBundle_VEC_RGATHER(4) 917 } 918 is("b011".U ){ 919 genCsBundle_VEC_RGATHER(8) 920 } 921 } 922 } 923 is(UopSplitType.VEC_RGATHER_VX) { 924 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 925 for (i <- 0 until len) 926 for (j <- 0 until len) { 927 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 928 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 929 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 930 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 931 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 932 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 933 csBundle(i * len + j + 1).lsrc(2) := vd_old 934 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 935 csBundle(i * len + j + 1).ldest := vd 936 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 937 } 938 } 939 // FMV.D.X 940 csBundle(0).srcType(0) := SrcType.reg 941 csBundle(0).srcType(1) := SrcType.imm 942 csBundle(0).lsrc(1) := 0.U 943 csBundle(0).ldest := FP_TMP_REG_MV.U 944 csBundle(0).fuType := FuType.i2f.U 945 csBundle(0).rfWen := false.B 946 csBundle(0).fpWen := true.B 947 csBundle(0).vecWen := false.B 948 csBundle(0).fpu.isAddSub := false.B 949 csBundle(0).fpu.typeTagIn := FPU.D 950 csBundle(0).fpu.typeTagOut := FPU.D 951 csBundle(0).fpu.fromInt := true.B 952 csBundle(0).fpu.wflags := false.B 953 csBundle(0).fpu.fpWen := true.B 954 csBundle(0).fpu.div := false.B 955 csBundle(0).fpu.sqrt := false.B 956 csBundle(0).fpu.fcvt := false.B 957 switch(simple.io.enq.vtype.vlmul) { 958 is("b000".U ){ 959 genCsBundle_RGATHER_VX(1) 960 } 961 is("b001".U ){ 962 genCsBundle_RGATHER_VX(2) 963 } 964 is("b010".U ){ 965 genCsBundle_RGATHER_VX(4) 966 } 967 is("b011".U ){ 968 genCsBundle_RGATHER_VX(8) 969 } 970 } 971 } 972 is(UopSplitType.VEC_RGATHEREI16) { 973 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 974 for (i <- 0 until len) 975 for (j <- 0 until len) { 976 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 977 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 978 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 979 // csBundle(i * len + j).srcType(1) := SrcType.vp 980 // csBundle(i * len + j).srcType(2) := SrcType.vp 981 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 982 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 983 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 984 csBundle((i * len + j)*2+0).ldest := vd0 985 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 986 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 987 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 988 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 989 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 990 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 991 csBundle((i * len + j)*2+1).ldest := vd1 992 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 993 } 994 } 995 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 996 for (i <- 0 until len) 997 for (j <- 0 until len) { 998 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 999 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1000 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1001 // csBundle(i * len + j).srcType(1) := SrcType.vp 1002 // csBundle(i * len + j).srcType(2) := SrcType.vp 1003 csBundle(i * len + j).lsrc(0) := src1 + i.U 1004 csBundle(i * len + j).lsrc(1) := src2 + j.U 1005 csBundle(i * len + j).lsrc(2) := vd_old 1006 csBundle(i * len + j).ldest := vd 1007 csBundle(i * len + j).uopIdx := (i * len + j).U 1008 } 1009 } 1010 switch(simple.io.enq.vtype.vlmul) { 1011 is("b000".U ){ 1012 when(!simple.io.enq.vtype.vsew.orR){ 1013 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1014 } .otherwise{ 1015 genCsBundle_VEC_RGATHEREI16(1) 1016 } 1017 } 1018 is("b001".U) { 1019 when(!simple.io.enq.vtype.vsew.orR) { 1020 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1021 }.otherwise { 1022 genCsBundle_VEC_RGATHEREI16(2) 1023 } 1024 } 1025 is("b010".U) { 1026 when(!simple.io.enq.vtype.vsew.orR) { 1027 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1028 }.otherwise { 1029 genCsBundle_VEC_RGATHEREI16(4) 1030 } 1031 } 1032 is("b011".U) { 1033 genCsBundle_VEC_RGATHEREI16(8) 1034 } 1035 } 1036 } 1037 is(UopSplitType.VEC_COMPRESS) { 1038 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1039 for (i <- 0 until len){ 1040 val jlen = if (i == len-1) i+1 else i+2 1041 for (j <- 0 until jlen) { 1042 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1043 val vd = if(i==len-1) (dest + j.U) else{ 1044 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1045 } 1046 val src23Type = if (j == i+1) DontCare else SrcType.vp 1047 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1048 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1049 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1050 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1051 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1052 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1053 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1054 csBundle(i*(i+3)/2 + j).ldest := vd 1055 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1056 } 1057 } 1058 } 1059 switch(simple.io.enq.vtype.vlmul) { 1060 is("b001".U ){ 1061 genCsBundle_VEC_COMPRESS(2) 1062 } 1063 is("b010".U ){ 1064 genCsBundle_VEC_COMPRESS(4) 1065 } 1066 is("b011".U ){ 1067 genCsBundle_VEC_COMPRESS(8) 1068 } 1069 } 1070 } 1071 is(UopSplitType.VEC_US_LD) { 1072 /* 1073 FMV.D.X 1074 */ 1075 csBundle(0).srcType(0) := SrcType.reg 1076 csBundle(0).srcType(1) := SrcType.imm 1077 csBundle(0).lsrc(1) := 0.U 1078 csBundle(0).ldest := FP_TMP_REG_MV.U 1079 csBundle(0).fuType := FuType.i2f.U 1080 csBundle(0).rfWen := false.B 1081 csBundle(0).fpWen := true.B 1082 csBundle(0).vecWen := false.B 1083 csBundle(0).fpu.isAddSub := false.B 1084 csBundle(0).fpu.typeTagIn := FPU.D 1085 csBundle(0).fpu.typeTagOut := FPU.D 1086 csBundle(0).fpu.fromInt := true.B 1087 csBundle(0).fpu.wflags := false.B 1088 csBundle(0).fpu.fpWen := true.B 1089 csBundle(0).fpu.div := false.B 1090 csBundle(0).fpu.sqrt := false.B 1091 csBundle(0).fpu.fcvt := false.B 1092 //LMUL 1093 for (i <- 0 until MAX_VLMUL) { 1094 csBundle(i + 1).srcType(0) := SrcType.fp 1095 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1096 csBundle(i + 1).ldest := dest + i.U 1097 csBundle(i + 1).uopIdx := i.U 1098 } 1099 } 1100 } 1101 1102 //uops dispatch 1103 val s_normal :: s_ext :: Nil = Enum(2) 1104 val state = RegInit(s_normal) 1105 val state_next = WireDefault(state) 1106 val uopRes = RegInit(0.U) 1107 1108 //readyFromRename Counter 1109 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1110 1111 switch(state) { 1112 is(s_normal) { 1113 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1114 } 1115 is(s_ext) { 1116 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1117 } 1118 } 1119 1120 state := state_next 1121 1122 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1123 val uopResJudge = Mux(state === s_normal, 1124 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1125 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1126 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1127 1128 for(i <- 0 until RenameWidth) { 1129 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1130 (state === s_normal) -> csBundle(i), 1131 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1132 )) 1133 } 1134 1135 1136 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1137 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1138 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1139 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1140 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1141 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1142 notInfVec(0) := true.B 1143 1144 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1145 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1146 1.U) 1147 validToRename.zipWithIndex.foreach{ 1148 case(dst, i) => 1149 dst := MuxCase(false.B, Seq( 1150 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1151 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1152 )) 1153 } 1154 1155 readyToIBuf.zipWithIndex.foreach { 1156 case (dst, i) => 1157 dst := MuxCase(true.B, Seq( 1158 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1159 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1160 )) 1161 } 1162 1163 io.deq.decodedInsts := decodedInsts 1164 io.deq.isVset := isVsetSimple 1165 io.deq.complexNum := complexNum 1166 io.deq.validToRename := validToRename 1167 io.deq.readyToIBuf := readyToIBuf 1168 1169} 1170