1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val simple = new Bundle { 46 val decodedInst = Input(new DecodedInst) 47 val isComplex = Input(Bool()) 48 val uopInfo = Input(new UopInfo) 49 } 50 val vtype = Input(new VType) 51 val in0pc = Input(UInt(VAddrBits.W)) 52 val isComplex = Input(Vec(DecodeWidth, Bool())) 53 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 54 val readyFromRename = Input(Vec(RenameWidth, Bool())) 55 val deq = new Bundle { 56 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 57 val isVset = Output(Bool()) 58 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 59 val validToRename = Output(Vec(RenameWidth, Bool())) 60 val complexNum = Output(UInt(3.W)) 61 } 62 val csrCtrl = Input(new CustomCSRCtrlIO) 63} 64 65/** 66 * @author zly 67 */ 68class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 69 val io = IO(new DecodeUnitCompIO) 70 71 val maxUopSize = MaxUopSize 72 //input bits 73 private val inst: XSInstBitFields = io.simple.decodedInst.instr.asTypeOf(new XSInstBitFields) 74 75 val src1 = Cat(0.U(1.W), inst.RS1) 76 val src2 = Cat(0.U(1.W), inst.RS2) 77 val dest = Cat(0.U(1.W), inst.RD) 78 79 80 //output bits 81 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 82 val validToRename = Wire(Vec(RenameWidth, Bool())) 83 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 84 val complexNum = Wire(UInt(3.W)) 85 86 //output of DecodeUnit 87 val decodedInstsSimple = Wire(new DecodedInst) 88 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 89 val lmul = Wire(UInt(4.W)) 90 val isVsetSimple = Wire(Bool()) 91 92 //pre decode 93 decodedInstsSimple := io.simple.decodedInst 94 lmul := io.simple.uopInfo.lmul 95 isVsetSimple := io.simple.decodedInst.isVset 96 val vlmulReg = io.simple.decodedInst.vpu.vlmul 97 val vsewReg = io.simple.decodedInst.vpu.vsew 98 when(isVsetSimple) { 99 when(dest === 0.U && src1 === 0.U) { 100 decodedInstsSimple.fuOpType := VSETOpType.keepVl(io.simple.decodedInst.fuOpType) 101 }.elsewhen(src1 === 0.U) { 102 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(io.simple.decodedInst.fuOpType) 103 } 104 when(io.vtype.illegal){ 105 decodedInstsSimple.flushPipe := true.B 106 } 107 } 108 //Type of uop Div 109 val typeOfSplit = decodedInstsSimple.uopSplitType 110 val src1Type = decodedInstsSimple.srcType(0) 111 val src1IsImm = src1Type === SrcType.imm 112 113 when(typeOfSplit === UopSplitType.DIR) { 114 numOfUop := Mux(dest =/= 0.U, 2.U, 115 Mux(src1 =/= 0.U, 1.U, 116 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 117 } .otherwise { 118 numOfUop := io.simple.uopInfo.numOfUop 119 } 120 121 122 //uop div up to maxUopSize 123 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 124 csBundle.map { case dst => 125 dst := decodedInstsSimple 126 dst.firstUop := false.B 127 dst.lastUop := false.B 128 } 129 130 csBundle(0).numUops := numOfUop 131 csBundle(0).firstUop := true.B 132 csBundle(numOfUop - 1.U).lastUop := true.B 133 134 switch(typeOfSplit) { 135 is(UopSplitType.DIR) { 136 when(isVsetSimple) { 137 when(dest =/= 0.U) { 138 csBundle(0).fuType := FuType.vsetiwi.U 139 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 140 csBundle(0).flushPipe := false.B 141 csBundle(0).rfWen := true.B 142 csBundle(0).vecWen := false.B 143 csBundle(1).ldest := VCONFIG_IDX.U 144 csBundle(1).rfWen := false.B 145 csBundle(1).vecWen := true.B 146 }.elsewhen(src1 =/= 0.U) { 147 csBundle(0).ldest := VCONFIG_IDX.U 148 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 149 csBundle(0).fuType := FuType.vsetfwf.U 150 csBundle(0).srcType(0) := SrcType.vp 151 csBundle(0).lsrc(0) := VCONFIG_IDX.U 152 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 153 csBundle(0).srcType(0) := SrcType.reg 154 csBundle(0).srcType(1) := SrcType.imm 155 csBundle(0).lsrc(1) := 0.U 156 csBundle(0).ldest := FP_TMP_REG_MV.U 157 csBundle(0).fuType := FuType.i2f.U 158 csBundle(0).rfWen := false.B 159 csBundle(0).fpWen := true.B 160 csBundle(0).vecWen := false.B 161 csBundle(0).fpu.isAddSub := false.B 162 csBundle(0).fpu.typeTagIn := FPU.D 163 csBundle(0).fpu.typeTagOut := FPU.D 164 csBundle(0).fpu.fromInt := true.B 165 csBundle(0).fpu.wflags := false.B 166 csBundle(0).fpu.fpWen := true.B 167 csBundle(0).fpu.div := false.B 168 csBundle(0).fpu.sqrt := false.B 169 csBundle(0).fpu.fcvt := false.B 170 csBundle(0).flushPipe := false.B 171 csBundle(1).fuType := FuType.vsetfwf.U 172 csBundle(1).srcType(0) := SrcType.vp 173 csBundle(1).lsrc(0) := VCONFIG_IDX.U 174 csBundle(1).srcType(1) := SrcType.fp 175 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 176 csBundle(1).ldest := VCONFIG_IDX.U 177 } 178 } 179 } 180 is(UopSplitType.VEC_VVV) { 181 for (i <- 0 until MAX_VLMUL) { 182 csBundle(i).lsrc(0) := src1 + i.U 183 csBundle(i).lsrc(1) := src2 + i.U 184 csBundle(i).lsrc(2) := dest + i.U 185 csBundle(i).ldest := dest + i.U 186 csBundle(i).uopIdx := i.U 187 } 188 } 189 is(UopSplitType.VEC_VFV) { 190 for (i <- 0 until MAX_VLMUL) { 191 csBundle(i).lsrc(1) := src2 + i.U 192 csBundle(i).lsrc(2) := dest + i.U 193 csBundle(i).ldest := dest + i.U 194 csBundle(i).uopIdx := i.U 195 } 196 } 197 is(UopSplitType.VEC_EXT2) { 198 for (i <- 0 until MAX_VLMUL / 2) { 199 csBundle(2 * i).lsrc(1) := src2 + i.U 200 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 201 csBundle(2 * i).ldest := dest + (2 * i).U 202 csBundle(2 * i).uopIdx := (2 * i).U 203 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 204 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 205 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 206 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 207 } 208 } 209 is(UopSplitType.VEC_EXT4) { 210 for (i <- 0 until MAX_VLMUL / 4) { 211 csBundle(4 * i).lsrc(1) := src2 + i.U 212 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 213 csBundle(4 * i).ldest := dest + (4 * i).U 214 csBundle(4 * i).uopIdx := (4 * i).U 215 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 216 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 217 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 218 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 219 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 220 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 221 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 222 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 223 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 224 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 225 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 226 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 227 } 228 } 229 is(UopSplitType.VEC_EXT8) { 230 for (i <- 0 until MAX_VLMUL) { 231 csBundle(i).lsrc(1) := src2 232 csBundle(i).lsrc(2) := dest + i.U 233 csBundle(i).ldest := dest + i.U 234 csBundle(i).uopIdx := i.U 235 } 236 } 237 is(UopSplitType.VEC_0XV) { 238 /* 239 FMV.D.X 240 */ 241 csBundle(0).srcType(0) := SrcType.reg 242 csBundle(0).srcType(1) := SrcType.imm 243 csBundle(0).lsrc(1) := 0.U 244 csBundle(0).ldest := FP_TMP_REG_MV.U 245 csBundle(0).fuType := FuType.i2f.U 246 csBundle(0).rfWen := false.B 247 csBundle(0).fpWen := true.B 248 csBundle(0).vecWen := false.B 249 csBundle(0).fpu.isAddSub := false.B 250 csBundle(0).fpu.typeTagIn := FPU.D 251 csBundle(0).fpu.typeTagOut := FPU.D 252 csBundle(0).fpu.fromInt := true.B 253 csBundle(0).fpu.wflags := false.B 254 csBundle(0).fpu.fpWen := true.B 255 csBundle(0).fpu.div := false.B 256 csBundle(0).fpu.sqrt := false.B 257 csBundle(0).fpu.fcvt := false.B 258 /* 259 vfmv.s.f 260 */ 261 csBundle(1).srcType(0) := SrcType.fp 262 csBundle(1).srcType(1) := SrcType.vp 263 csBundle(1).srcType(2) := SrcType.vp 264 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 265 csBundle(1).lsrc(1) := 0.U 266 csBundle(1).lsrc(2) := dest 267 csBundle(1).ldest := dest 268 csBundle(1).fuType := FuType.vppu.U 269 csBundle(1).fuOpType := VpermType.dummy 270 csBundle(1).rfWen := false.B 271 csBundle(1).fpWen := false.B 272 csBundle(1).vecWen := true.B 273 } 274 is(UopSplitType.VEC_VXV) { 275 /* 276 i to vector move 277 */ 278 csBundle(0).srcType(0) := SrcType.reg 279 csBundle(0).srcType(1) := SrcType.imm 280 csBundle(0).lsrc(1) := 0.U 281 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 282 csBundle(0).fuType := FuType.i2v.U 283 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 284 csBundle(0).vecWen := true.B 285 /* 286 LMUL 287 */ 288 for (i <- 0 until MAX_VLMUL) { 289 csBundle(i + 1).srcType(0) := SrcType.vp 290 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 291 csBundle(i + 1).lsrc(1) := src2 + i.U 292 csBundle(i + 1).lsrc(2) := dest + i.U 293 csBundle(i + 1).ldest := dest + i.U 294 csBundle(i + 1).uopIdx := i.U 295 } 296 } 297 is(UopSplitType.VEC_VVW) { 298 for (i <- 0 until MAX_VLMUL / 2) { 299 csBundle(2 * i).lsrc(0) := src1 + i.U 300 csBundle(2 * i).lsrc(1) := src2 + i.U 301 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 302 csBundle(2 * i).ldest := dest + (2 * i).U 303 csBundle(2 * i).uopIdx := (2 * i).U 304 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 305 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 306 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 307 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 308 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 309 } 310 } 311 is(UopSplitType.VEC_VFW) { 312 for (i <- 0 until MAX_VLMUL / 2) { 313 csBundle(2 * i).lsrc(0) := src1 314 csBundle(2 * i).lsrc(1) := src2 + i.U 315 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 316 csBundle(2 * i).ldest := dest + (2 * i).U 317 csBundle(2 * i).uopIdx := (2 * i).U 318 csBundle(2 * i + 1).lsrc(0) := src1 319 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 320 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 321 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 322 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 323 } 324 } 325 is(UopSplitType.VEC_WVW) { 326 for (i <- 0 until MAX_VLMUL / 2) { 327 csBundle(2 * i).lsrc(0) := src1 + i.U 328 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 329 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 330 csBundle(2 * i).ldest := dest + (2 * i).U 331 csBundle(2 * i).uopIdx := (2 * i).U 332 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 333 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 334 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 335 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 336 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 337 } 338 } 339 is(UopSplitType.VEC_VXW) { 340 /* 341 i to vector move 342 */ 343 csBundle(0).srcType(0) := SrcType.reg 344 csBundle(0).srcType(1) := SrcType.imm 345 csBundle(0).lsrc(1) := 0.U 346 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 347 csBundle(0).fuType := FuType.i2v.U 348 csBundle(0).fuOpType := vsewReg 349 csBundle(0).vecWen := true.B 350 351 for (i <- 0 until MAX_VLMUL / 2) { 352 csBundle(2 * i + 1).srcType(0) := SrcType.vp 353 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 354 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 355 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 356 csBundle(2 * i + 1).ldest := dest + (2 * i).U 357 csBundle(2 * i + 1).uopIdx := (2 * i).U 358 csBundle(2 * i + 2).srcType(0) := SrcType.vp 359 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 360 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 361 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 362 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 363 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 364 } 365 } 366 is(UopSplitType.VEC_WXW) { 367 /* 368 i to vector move 369 */ 370 csBundle(0).srcType(0) := SrcType.reg 371 csBundle(0).srcType(1) := SrcType.imm 372 csBundle(0).lsrc(1) := 0.U 373 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 374 csBundle(0).fuType := FuType.i2v.U 375 csBundle(0).fuOpType := vsewReg 376 csBundle(0).vecWen := true.B 377 378 for (i <- 0 until MAX_VLMUL / 2) { 379 csBundle(2 * i + 1).srcType(0) := SrcType.vp 380 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 381 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 382 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 383 csBundle(2 * i + 1).ldest := dest + (2 * i).U 384 csBundle(2 * i + 1).uopIdx := (2 * i).U 385 csBundle(2 * i + 2).srcType(0) := SrcType.vp 386 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 387 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 388 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 389 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 390 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 391 } 392 } 393 is(UopSplitType.VEC_WVV) { 394 for (i <- 0 until MAX_VLMUL / 2) { 395 396 csBundle(2 * i).lsrc(0) := src1 + i.U 397 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 398 csBundle(2 * i).lsrc(2) := dest + i.U 399 csBundle(2 * i).ldest := dest + i.U 400 csBundle(2 * i).uopIdx := (2 * i).U 401 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 402 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 403 csBundle(2 * i + 1).lsrc(2) := dest + i.U 404 csBundle(2 * i + 1).ldest := dest + i.U 405 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 406 } 407 } 408 is(UopSplitType.VEC_WFW) { 409 for (i <- 0 until MAX_VLMUL / 2) { 410 csBundle(2 * i).lsrc(0) := src1 411 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 412 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 413 csBundle(2 * i).ldest := dest + (2 * i).U 414 csBundle(2 * i).uopIdx := (2 * i).U 415 csBundle(2 * i + 1).lsrc(0) := src1 416 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 418 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 419 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopSplitType.VEC_WXV) { 423 /* 424 i to vector move 425 */ 426 csBundle(0).srcType(0) := SrcType.reg 427 csBundle(0).srcType(1) := SrcType.imm 428 csBundle(0).lsrc(1) := 0.U 429 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 430 csBundle(0).fuType := FuType.i2v.U 431 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 432 csBundle(0).vecWen := true.B 433 434 for (i <- 0 until MAX_VLMUL / 2) { 435 csBundle(2 * i + 1).srcType(0) := SrcType.vp 436 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 437 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 438 csBundle(2 * i + 1).lsrc(2) := dest + i.U 439 csBundle(2 * i + 1).ldest := dest + i.U 440 csBundle(2 * i + 1).uopIdx := (2 * i).U 441 csBundle(2 * i + 2).srcType(0) := SrcType.vp 442 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 443 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 444 csBundle(2 * i + 2).lsrc(2) := dest + i.U 445 csBundle(2 * i + 2).ldest := dest + i.U 446 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 447 } 448 } 449 is(UopSplitType.VEC_VVM) { 450 csBundle(0).lsrc(2) := dest 451 csBundle(0).ldest := dest 452 csBundle(0).uopIdx := 0.U 453 for (i <- 1 until MAX_VLMUL) { 454 csBundle(i).lsrc(0) := src1 + i.U 455 csBundle(i).lsrc(1) := src2 + i.U 456 csBundle(i).lsrc(2) := dest 457 csBundle(i).ldest := dest 458 csBundle(i).uopIdx := i.U 459 } 460 } 461 is(UopSplitType.VEC_VFM) { 462 csBundle(0).lsrc(2) := dest 463 csBundle(0).ldest := dest 464 csBundle(0).uopIdx := 0.U 465 for (i <- 1 until MAX_VLMUL) { 466 csBundle(i).lsrc(0) := src1 467 csBundle(i).lsrc(1) := src2 + i.U 468 csBundle(i).lsrc(2) := dest 469 csBundle(i).ldest := dest 470 csBundle(i).uopIdx := i.U 471 } 472 csBundle(numOfUop - 1.U).ldest := dest 473 } 474 is(UopSplitType.VEC_VXM) { 475 /* 476 i to vector move 477 */ 478 csBundle(0).srcType(0) := SrcType.reg 479 csBundle(0).srcType(1) := SrcType.imm 480 csBundle(0).lsrc(1) := 0.U 481 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 482 csBundle(0).fuType := FuType.i2v.U 483 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 484 csBundle(0).vecWen := true.B 485 //LMUL 486 csBundle(1).srcType(0) := SrcType.vp 487 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 488 csBundle(1).lsrc(2) := dest 489 csBundle(1).ldest := dest 490 csBundle(1).uopIdx := 0.U 491 for (i <- 1 until MAX_VLMUL) { 492 csBundle(i + 1).srcType(0) := SrcType.vp 493 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 494 csBundle(i + 1).lsrc(1) := src2 + i.U 495 csBundle(i + 1).lsrc(2) := dest 496 csBundle(i + 1).ldest := dest 497 csBundle(i + 1).uopIdx := i.U 498 } 499 csBundle(numOfUop - 1.U).ldest := dest 500 } 501 is(UopSplitType.VEC_SLIDE1UP) { 502 /* 503 i to vector move 504 */ 505 csBundle(0).srcType(0) := SrcType.reg 506 csBundle(0).srcType(1) := SrcType.imm 507 csBundle(0).lsrc(1) := 0.U 508 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 509 csBundle(0).fuType := FuType.i2v.U 510 csBundle(0).fuOpType := vsewReg 511 csBundle(0).vecWen := true.B 512 //LMUL 513 csBundle(1).srcType(0) := SrcType.vp 514 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 515 csBundle(1).lsrc(2) := dest 516 csBundle(1).ldest := dest 517 csBundle(1).uopIdx := 0.U 518 for (i <- 1 until MAX_VLMUL) { 519 csBundle(i + 1).srcType(0) := SrcType.vp 520 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 521 csBundle(i + 1).lsrc(1) := src2 + i.U 522 csBundle(i + 1).lsrc(2) := dest + i.U 523 csBundle(i + 1).ldest := dest + i.U 524 csBundle(i + 1).uopIdx := i.U 525 } 526 } 527 is(UopSplitType.VEC_FSLIDE1UP) { 528 //LMUL 529 csBundle(0).srcType(0) := SrcType.fp 530 csBundle(0).lsrc(0) := src1 531 csBundle(0).lsrc(1) := src2 532 csBundle(0).lsrc(2) := dest 533 csBundle(0).ldest := dest 534 csBundle(0).uopIdx := 0.U 535 for (i <- 1 until MAX_VLMUL) { 536 csBundle(i).srcType(0) := SrcType.vp 537 csBundle(i).lsrc(0) := src2 + (i - 1).U 538 csBundle(i).lsrc(1) := src2 + i.U 539 csBundle(i).lsrc(2) := dest + i.U 540 csBundle(i).ldest := dest + i.U 541 csBundle(i).uopIdx := i.U 542 } 543 } 544 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 545 /* 546 i to vector move 547 */ 548 csBundle(0).srcType(0) := SrcType.reg 549 csBundle(0).srcType(1) := SrcType.imm 550 csBundle(0).lsrc(1) := 0.U 551 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 552 csBundle(0).fuType := FuType.i2v.U 553 csBundle(0).fuOpType := vsewReg 554 csBundle(0).vecWen := true.B 555 //LMUL 556 for (i <- 0 until MAX_VLMUL) { 557 csBundle(2 * i + 1).srcType(0) := SrcType.vp 558 csBundle(2 * i + 1).srcType(1) := SrcType.vp 559 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 560 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 561 csBundle(2 * i + 1).lsrc(2) := dest + i.U 562 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 563 csBundle(2 * i + 1).uopIdx := (2 * i).U 564 if (2 * i + 2 < MAX_VLMUL * 2) { 565 csBundle(2 * i + 2).srcType(0) := SrcType.vp 566 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 567 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 568 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 569 csBundle(2 * i + 2).ldest := dest + i.U 570 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 571 } 572 } 573 csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 574 csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 575 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 576 } 577 is(UopSplitType.VEC_FSLIDE1DOWN) { 578 //LMUL 579 for (i <- 0 until MAX_VLMUL) { 580 csBundle(2 * i).srcType(0) := SrcType.vp 581 csBundle(2 * i).srcType(1) := SrcType.vp 582 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 583 csBundle(2 * i).lsrc(1) := src2 + i.U 584 csBundle(2 * i).lsrc(2) := dest + i.U 585 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 586 csBundle(2 * i).uopIdx := (2 * i).U 587 csBundle(2 * i + 1).srcType(0) := SrcType.fp 588 csBundle(2 * i + 1).lsrc(0) := src1 589 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 590 csBundle(2 * i + 1).ldest := dest + i.U 591 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 592 } 593 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 594 csBundle(numOfUop - 1.U).lsrc(0) := src1 595 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 596 } 597 is(UopSplitType.VEC_VRED) { 598 when(vlmulReg === "b001".U) { 599 csBundle(0).srcType(2) := SrcType.DC 600 csBundle(0).lsrc(0) := src2 + 1.U 601 csBundle(0).lsrc(1) := src2 602 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 603 csBundle(0).uopIdx := 0.U 604 } 605 when(vlmulReg === "b010".U) { 606 csBundle(0).srcType(2) := SrcType.DC 607 csBundle(0).lsrc(0) := src2 + 1.U 608 csBundle(0).lsrc(1) := src2 609 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 610 csBundle(0).uopIdx := 0.U 611 612 csBundle(1).srcType(2) := SrcType.DC 613 csBundle(1).lsrc(0) := src2 + 3.U 614 csBundle(1).lsrc(1) := src2 + 2.U 615 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 616 csBundle(1).uopIdx := 1.U 617 618 csBundle(2).srcType(2) := SrcType.DC 619 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 620 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 621 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 622 csBundle(2).uopIdx := 2.U 623 } 624 when(vlmulReg === "b011".U) { 625 for (i <- 0 until MAX_VLMUL) { 626 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 627 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 628 csBundle(i).lsrc(1) := src2 + (i * 2).U 629 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 630 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 631 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 632 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 633 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 634 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 635 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 636 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 637 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 638 } 639 csBundle(i).srcType(2) := SrcType.DC 640 csBundle(i).uopIdx := i.U 641 } 642 } 643 when(vlmulReg.orR) { 644 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 645 csBundle(numOfUop - 1.U).lsrc(0) := src1 646 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 647 csBundle(numOfUop - 1.U).lsrc(2) := dest 648 csBundle(numOfUop - 1.U).ldest := dest 649 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 650 } 651 } 652 is(UopSplitType.VEC_VFRED) { 653 val vlmul = vlmulReg 654 val vsew = vsewReg 655 when(vlmul === VLmul.m8){ 656 for (i <- 0 until 4) { 657 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 658 csBundle(i).lsrc(1) := src2 + (i * 2).U 659 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 660 csBundle(i).uopIdx := i.U 661 } 662 for (i <- 4 until 6) { 663 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 664 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 665 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 666 csBundle(i).uopIdx := i.U 667 } 668 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 669 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 670 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 671 csBundle(6).uopIdx := 6.U 672 when(vsew === VSew.e64) { 673 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 674 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 675 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 676 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 677 csBundle(7).uopIdx := 7.U 678 csBundle(8).lsrc(0) := src1 679 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 680 csBundle(8).ldest := dest 681 csBundle(8).uopIdx := 8.U 682 } 683 when(vsew === VSew.e32) { 684 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 685 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 686 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 687 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 688 csBundle(7).uopIdx := 7.U 689 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 690 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 691 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 692 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 693 csBundle(8).uopIdx := 8.U 694 csBundle(9).lsrc(0) := src1 695 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 696 csBundle(9).ldest := dest 697 csBundle(9).uopIdx := 9.U 698 } 699 when(vsew === VSew.e16) { 700 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 701 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 702 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 703 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 704 csBundle(7).uopIdx := 7.U 705 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 706 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 707 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 708 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 709 csBundle(8).uopIdx := 8.U 710 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 711 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 712 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 713 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 714 csBundle(9).uopIdx := 9.U 715 csBundle(10).lsrc(0) := src1 716 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 717 csBundle(10).ldest := dest 718 csBundle(10).uopIdx := 10.U 719 } 720 } 721 when(vlmul === VLmul.m4) { 722 for (i <- 0 until 2) { 723 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 724 csBundle(i).lsrc(1) := src2 + (i * 2).U 725 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 726 csBundle(i).uopIdx := i.U 727 } 728 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 729 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 730 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 731 csBundle(2).uopIdx := 2.U 732 when(vsew === VSew.e64) { 733 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 734 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 735 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 736 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 737 csBundle(3).uopIdx := 3.U 738 csBundle(4).lsrc(0) := src1 739 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 740 csBundle(4).ldest := dest 741 csBundle(4).uopIdx := 4.U 742 } 743 when(vsew === VSew.e32) { 744 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 745 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 746 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 747 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 748 csBundle(3).uopIdx := 3.U 749 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 750 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 751 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 752 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 753 csBundle(4).uopIdx := 4.U 754 csBundle(5).lsrc(0) := src1 755 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 756 csBundle(5).ldest := dest 757 csBundle(5).uopIdx := 5.U 758 } 759 when(vsew === VSew.e16) { 760 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 761 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 762 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 763 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 764 csBundle(3).uopIdx := 3.U 765 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 766 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 767 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 768 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 769 csBundle(4).uopIdx := 4.U 770 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 771 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 772 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 773 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 774 csBundle(5).uopIdx := 5.U 775 csBundle(6).lsrc(0) := src1 776 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 777 csBundle(6).ldest := dest 778 csBundle(6).uopIdx := 6.U 779 } 780 } 781 when(vlmul === VLmul.m2) { 782 csBundle(0).lsrc(0) := src2 + 1.U 783 csBundle(0).lsrc(1) := src2 + 0.U 784 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 785 csBundle(0).uopIdx := 0.U 786 when(vsew === VSew.e64) { 787 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 788 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 789 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 790 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 791 csBundle(1).uopIdx := 1.U 792 csBundle(2).lsrc(0) := src1 793 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 794 csBundle(2).ldest := dest 795 csBundle(2).uopIdx := 2.U 796 } 797 when(vsew === VSew.e32) { 798 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 799 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 800 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 801 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 802 csBundle(1).uopIdx := 1.U 803 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 804 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 805 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 806 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 807 csBundle(2).uopIdx := 2.U 808 csBundle(3).lsrc(0) := src1 809 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 810 csBundle(3).ldest := dest 811 csBundle(3).uopIdx := 3.U 812 } 813 when(vsew === VSew.e16) { 814 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 815 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 816 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 817 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 818 csBundle(1).uopIdx := 1.U 819 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 820 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 821 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 822 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 823 csBundle(2).uopIdx := 2.U 824 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 825 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 826 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 827 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 828 csBundle(3).uopIdx := 3.U 829 csBundle(4).lsrc(0) := src1 830 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 831 csBundle(4).ldest := dest 832 csBundle(4).uopIdx := 4.U 833 } 834 } 835 when(vlmul === VLmul.m1) { 836 when(vsew === VSew.e64) { 837 csBundle(0).lsrc(0) := src2 838 csBundle(0).lsrc(1) := src2 839 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 840 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 841 csBundle(0).uopIdx := 0.U 842 csBundle(1).lsrc(0) := src1 843 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 844 csBundle(1).ldest := dest 845 csBundle(1).uopIdx := 1.U 846 } 847 when(vsew === VSew.e32) { 848 csBundle(0).lsrc(0) := src2 849 csBundle(0).lsrc(1) := src2 850 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 851 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 852 csBundle(0).uopIdx := 0.U 853 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 854 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 855 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 856 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 857 csBundle(1).uopIdx := 1.U 858 csBundle(2).lsrc(0) := src1 859 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 860 csBundle(2).ldest := dest 861 csBundle(2).uopIdx := 2.U 862 } 863 when(vsew === VSew.e16) { 864 csBundle(0).lsrc(0) := src2 865 csBundle(0).lsrc(1) := src2 866 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 867 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 868 csBundle(0).uopIdx := 0.U 869 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 870 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 871 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 872 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 873 csBundle(1).uopIdx := 1.U 874 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 875 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 876 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 877 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 878 csBundle(2).uopIdx := 2.U 879 csBundle(3).lsrc(0) := src1 880 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 881 csBundle(3).ldest := dest 882 csBundle(3).uopIdx := 3.U 883 } 884 } 885 when(vlmul === VLmul.mf2) { 886 when(vsew === VSew.e32) { 887 csBundle(0).lsrc(0) := src2 888 csBundle(0).lsrc(1) := src2 889 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 890 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 891 csBundle(0).uopIdx := 0.U 892 csBundle(1).lsrc(0) := src1 893 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 894 csBundle(1).ldest := dest 895 csBundle(1).uopIdx := 1.U 896 } 897 when(vsew === VSew.e16) { 898 csBundle(0).lsrc(0) := src2 899 csBundle(0).lsrc(1) := src2 900 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 901 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 902 csBundle(0).uopIdx := 0.U 903 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 904 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 905 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 906 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 907 csBundle(1).uopIdx := 1.U 908 csBundle(2).lsrc(0) := src1 909 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 910 csBundle(2).ldest := dest 911 csBundle(2).uopIdx := 2.U 912 } 913 } 914 when(vlmul === VLmul.mf4) { 915 when(vsew === VSew.e16) { 916 csBundle(0).lsrc(0) := src2 917 csBundle(0).lsrc(1) := src2 918 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 919 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 920 csBundle(0).uopIdx := 0.U 921 csBundle(1).lsrc(0) := src1 922 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 923 csBundle(1).ldest := dest 924 csBundle(1).uopIdx := 1.U 925 } 926 } 927 } 928 929 is(UopSplitType.VEC_VFREDOSUM) { 930 import yunsuan.VfaluType 931 val vlmul = vlmulReg 932 val vsew = vsewReg 933 val isWiden = decodedInstsSimple.fuOpType === VfaluType.vfwredosum 934 when(vlmul === VLmul.m8) { 935 when(vsew === VSew.e64) { 936 val vlmax = 16 937 for (i <- 0 until vlmax) { 938 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 939 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 940 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 941 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 942 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 943 csBundle(i).uopIdx := i.U 944 } 945 } 946 when(vsew === VSew.e32) { 947 val vlmax = 32 948 for (i <- 0 until vlmax) { 949 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 950 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 951 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 952 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 953 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 954 csBundle(i).uopIdx := i.U 955 } 956 } 957 when(vsew === VSew.e16) { 958 val vlmax = 64 959 for (i <- 0 until vlmax) { 960 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 961 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 962 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 963 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 964 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 965 csBundle(i).uopIdx := i.U 966 } 967 } 968 } 969 when(vlmul === VLmul.m4) { 970 when(vsew === VSew.e64) { 971 val vlmax = 8 972 for (i <- 0 until vlmax) { 973 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 974 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 975 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 976 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 977 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 978 csBundle(i).uopIdx := i.U 979 } 980 } 981 when(vsew === VSew.e32) { 982 val vlmax = 16 983 for (i <- 0 until vlmax) { 984 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 985 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 986 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 987 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 988 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 989 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 990 csBundle(i).uopIdx := i.U 991 } 992 } 993 when(vsew === VSew.e16) { 994 val vlmax = 32 995 for (i <- 0 until vlmax) { 996 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 997 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 998 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 999 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1000 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1001 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1002 csBundle(i).uopIdx := i.U 1003 } 1004 } 1005 } 1006 when(vlmul === VLmul.m2) { 1007 when(vsew === VSew.e64) { 1008 val vlmax = 4 1009 for (i <- 0 until vlmax) { 1010 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1011 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1012 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1013 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1014 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1015 csBundle(i).uopIdx := i.U 1016 } 1017 } 1018 when(vsew === VSew.e32) { 1019 val vlmax = 8 1020 for (i <- 0 until vlmax) { 1021 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1022 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1023 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1024 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1025 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1026 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1027 csBundle(i).uopIdx := i.U 1028 } 1029 } 1030 when(vsew === VSew.e16) { 1031 val vlmax = 16 1032 for (i <- 0 until vlmax) { 1033 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1034 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1035 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1036 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1037 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1038 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1039 csBundle(i).uopIdx := i.U 1040 } 1041 } 1042 } 1043 when(vlmul === VLmul.m1) { 1044 when(vsew === VSew.e64) { 1045 val vlmax = 2 1046 for (i <- 0 until vlmax) { 1047 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1048 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1049 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1050 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1051 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1052 csBundle(i).uopIdx := i.U 1053 } 1054 } 1055 when(vsew === VSew.e32) { 1056 val vlmax = 4 1057 for (i <- 0 until vlmax) { 1058 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1059 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1060 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1061 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1062 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1063 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1064 csBundle(i).uopIdx := i.U 1065 } 1066 } 1067 when(vsew === VSew.e16) { 1068 val vlmax = 8 1069 for (i <- 0 until vlmax) { 1070 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1071 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1072 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1073 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1074 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1075 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1076 csBundle(i).uopIdx := i.U 1077 } 1078 } 1079 } 1080 when(vlmul === VLmul.mf2) { 1081 when(vsew === VSew.e32) { 1082 val vlmax = 2 1083 for (i <- 0 until vlmax) { 1084 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1085 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1086 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1087 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1088 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1089 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1090 csBundle(i).uopIdx := i.U 1091 } 1092 } 1093 when(vsew === VSew.e16) { 1094 val vlmax = 4 1095 for (i <- 0 until vlmax) { 1096 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1097 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1098 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1099 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1100 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1101 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1102 csBundle(i).uopIdx := i.U 1103 } 1104 } 1105 } 1106 when(vlmul === VLmul.mf4) { 1107 when(vsew === VSew.e16) { 1108 val vlmax = 2 1109 for (i <- 0 until vlmax) { 1110 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1111 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1112 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1113 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1114 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1115 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1116 csBundle(i).uopIdx := i.U 1117 } 1118 } 1119 } 1120 } 1121 1122 is(UopSplitType.VEC_SLIDEUP) { 1123 // i to vector move 1124 csBundle(0).srcType(0) := SrcType.reg 1125 csBundle(0).srcType(1) := SrcType.imm 1126 csBundle(0).lsrc(1) := 0.U 1127 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1128 csBundle(0).fuType := FuType.i2v.U 1129 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1130 csBundle(0).vecWen := true.B 1131 // LMUL 1132 for (i <- 0 until MAX_VLMUL) 1133 for (j <- 0 to i) { 1134 val old_vd = if (j == 0) { 1135 dest + i.U 1136 } else (VECTOR_TMP_REG_LMUL + j).U 1137 val vd = if (j == i) { 1138 dest + i.U 1139 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1140 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1141 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1142 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1143 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1144 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1145 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1146 } 1147 } 1148 1149 is(UopSplitType.VEC_SLIDEDOWN) { 1150 // i to vector move 1151 csBundle(0).srcType(0) := SrcType.reg 1152 csBundle(0).srcType(1) := SrcType.imm 1153 csBundle(0).lsrc(1) := 0.U 1154 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1155 csBundle(0).fuType := FuType.i2v.U 1156 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1157 csBundle(0).vecWen := true.B 1158 // LMUL 1159 for (i <- 0 until MAX_VLMUL) 1160 for (j <- (0 to i).reverse) { 1161 when(i.U < lmul) { 1162 val old_vd = if (j == 0) { 1163 dest + lmul - 1.U - i.U 1164 } else (VECTOR_TMP_REG_LMUL + j).U 1165 val vd = if (j == i) { 1166 dest + lmul - 1.U - i.U 1167 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1168 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1169 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1170 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1171 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1172 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1173 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1174 } 1175 } 1176 } 1177 1178 is(UopSplitType.VEC_M0X) { 1179 // LMUL 1180 for (i <- 0 until MAX_VLMUL) { 1181 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1182 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1183 csBundle(i).srcType(0) := srcType0 1184 csBundle(i).srcType(1) := SrcType.vp 1185 csBundle(i).rfWen := false.B 1186 csBundle(i).vecWen := true.B 1187 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1188 csBundle(i).lsrc(1) := src2 1189 // csBundle(i).lsrc(2) := dest + i.U DontCare 1190 csBundle(i).ldest := ldest 1191 csBundle(i).uopIdx := i.U 1192 } 1193 csBundle(lmul - 1.U).vecWen := false.B 1194 csBundle(lmul - 1.U).fpWen := true.B 1195 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 1196 // FMV_X_D 1197 csBundle(lmul).srcType(0) := SrcType.fp 1198 csBundle(lmul).srcType(1) := SrcType.imm 1199 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 1200 csBundle(lmul).lsrc(1) := 0.U 1201 csBundle(lmul).ldest := dest 1202 csBundle(lmul).fuType := FuType.fmisc.U 1203 csBundle(lmul).rfWen := true.B 1204 csBundle(lmul).fpWen := false.B 1205 csBundle(lmul).vecWen := false.B 1206 csBundle(lmul).fpu.isAddSub := false.B 1207 csBundle(lmul).fpu.typeTagIn := FPU.D 1208 csBundle(lmul).fpu.typeTagOut := FPU.D 1209 csBundle(lmul).fpu.fromInt := false.B 1210 csBundle(lmul).fpu.wflags := false.B 1211 csBundle(lmul).fpu.fpWen := false.B 1212 csBundle(lmul).fpu.div := false.B 1213 csBundle(lmul).fpu.sqrt := false.B 1214 csBundle(lmul).fpu.fcvt := false.B 1215 } 1216 1217 is(UopSplitType.VEC_MVV) { 1218 // LMUL 1219 for (i <- 0 until MAX_VLMUL) { 1220 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1221 csBundle(i * 2 + 0).srcType(0) := srcType0 1222 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1223 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1224 csBundle(i * 2 + 0).lsrc(1) := src2 1225 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1226 csBundle(i * 2 + 0).ldest := dest + i.U 1227 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1228 1229 csBundle(i * 2 + 1).srcType(0) := srcType0 1230 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1231 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1232 csBundle(i * 2 + 1).lsrc(1) := src2 1233 // csBundle(i).lsrc(2) := dest + i.U DontCare 1234 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1235 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1236 } 1237 } 1238 1239 is(UopSplitType.VEC_M0X_VFIRST) { 1240 // LMUL 1241 csBundle(0).rfWen := false.B 1242 csBundle(0).fpWen := true.B 1243 csBundle(0).ldest := FP_TMP_REG_MV.U 1244 // FMV_X_D 1245 csBundle(1).srcType(0) := SrcType.fp 1246 csBundle(1).srcType(1) := SrcType.imm 1247 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 1248 csBundle(1).lsrc(1) := 0.U 1249 csBundle(1).ldest := dest 1250 csBundle(1).fuType := FuType.fmisc.U 1251 csBundle(1).rfWen := true.B 1252 csBundle(1).fpWen := false.B 1253 csBundle(1).vecWen := false.B 1254 csBundle(1).fpu.isAddSub := false.B 1255 csBundle(1).fpu.typeTagIn := FPU.D 1256 csBundle(1).fpu.typeTagOut := FPU.D 1257 csBundle(1).fpu.fromInt := false.B 1258 csBundle(1).fpu.wflags := false.B 1259 csBundle(1).fpu.fpWen := false.B 1260 csBundle(1).fpu.div := false.B 1261 csBundle(1).fpu.sqrt := false.B 1262 csBundle(1).fpu.fcvt := false.B 1263 } 1264 is(UopSplitType.VEC_VWW) { 1265 for (i <- 0 until MAX_VLMUL*2) { 1266 when(i.U < lmul){ 1267 csBundle(i).srcType(2) := SrcType.DC 1268 csBundle(i).lsrc(0) := src2 + i.U 1269 csBundle(i).lsrc(1) := src2 + i.U 1270 // csBundle(i).lsrc(2) := dest + (2 * i).U 1271 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1272 csBundle(i).uopIdx := i.U 1273 } otherwise { 1274 csBundle(i).srcType(2) := SrcType.DC 1275 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1276 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1277 // csBundle(i).lsrc(2) := dest + (2 * i).U 1278 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1279 csBundle(i).uopIdx := i.U 1280 } 1281 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1282 csBundle(numOfUop-1.U).lsrc(0) := src1 1283 csBundle(numOfUop-1.U).lsrc(2) := dest 1284 csBundle(numOfUop-1.U).ldest := dest 1285 } 1286 } 1287 is(UopSplitType.VEC_RGATHER) { 1288 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1289 for (i <- 0 until len) 1290 for (j <- 0 until len) { 1291 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1292 // csBundle(i * len + j).srcType(1) := SrcType.vp 1293 // csBundle(i * len + j).srcType(2) := SrcType.vp 1294 csBundle(i * len + j).lsrc(0) := src1 + i.U 1295 csBundle(i * len + j).lsrc(1) := src2 + j.U 1296 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1297 csBundle(i * len + j).lsrc(2) := vd_old 1298 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1299 csBundle(i * len + j).ldest := vd 1300 csBundle(i * len + j).uopIdx := (i * len + j).U 1301 } 1302 } 1303 switch(vlmulReg) { 1304 is("b001".U ){ 1305 genCsBundle_VEC_RGATHER(2) 1306 } 1307 is("b010".U ){ 1308 genCsBundle_VEC_RGATHER(4) 1309 } 1310 is("b011".U ){ 1311 genCsBundle_VEC_RGATHER(8) 1312 } 1313 } 1314 } 1315 is(UopSplitType.VEC_RGATHER_VX) { 1316 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1317 for (i <- 0 until len) 1318 for (j <- 0 until len) { 1319 csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1320 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1321 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1322 csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1323 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1324 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1325 csBundle(i * len + j + 1).lsrc(2) := vd_old 1326 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1327 csBundle(i * len + j + 1).ldest := vd 1328 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1329 } 1330 } 1331 // i to vector move 1332 csBundle(0).srcType(0) := SrcType.reg 1333 csBundle(0).srcType(1) := SrcType.imm 1334 csBundle(0).lsrc(1) := 0.U 1335 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1336 csBundle(0).fuType := FuType.i2v.U 1337 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.permImm2vector(2, 0), IF2VectorType.i2vector(2, 0)), vsewReg) 1338 csBundle(0).vecWen := true.B 1339 switch(vlmulReg) { 1340 is("b000".U ){ 1341 genCsBundle_RGATHER_VX(1) 1342 } 1343 is("b001".U ){ 1344 genCsBundle_RGATHER_VX(2) 1345 } 1346 is("b010".U ){ 1347 genCsBundle_RGATHER_VX(4) 1348 } 1349 is("b011".U ){ 1350 genCsBundle_RGATHER_VX(8) 1351 } 1352 } 1353 } 1354 is(UopSplitType.VEC_RGATHEREI16) { 1355 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1356 for (i <- 0 until len) 1357 for (j <- 0 until len) { 1358 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1359 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1360 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1361 // csBundle(i * len + j).srcType(1) := SrcType.vp 1362 // csBundle(i * len + j).srcType(2) := SrcType.vp 1363 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1364 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1365 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1366 csBundle((i * len + j)*2+0).ldest := vd0 1367 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1368 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1369 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1370 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1371 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1372 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1373 csBundle((i * len + j)*2+1).ldest := vd1 1374 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1375 } 1376 } 1377 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1378 for (i <- 0 until len) 1379 for (j <- 0 until len) { 1380 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1381 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1382 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1383 // csBundle(i * len + j).srcType(1) := SrcType.vp 1384 // csBundle(i * len + j).srcType(2) := SrcType.vp 1385 csBundle(i * len + j).lsrc(0) := src1 + i.U 1386 csBundle(i * len + j).lsrc(1) := src2 + j.U 1387 csBundle(i * len + j).lsrc(2) := vd_old 1388 csBundle(i * len + j).ldest := vd 1389 csBundle(i * len + j).uopIdx := (i * len + j).U 1390 } 1391 } 1392 switch(vlmulReg) { 1393 is("b000".U ){ 1394 when(!vsewReg.orR){ 1395 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1396 } .otherwise{ 1397 genCsBundle_VEC_RGATHEREI16(1) 1398 } 1399 } 1400 is("b001".U) { 1401 when(!vsewReg.orR) { 1402 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1403 }.otherwise { 1404 genCsBundle_VEC_RGATHEREI16(2) 1405 } 1406 } 1407 is("b010".U) { 1408 when(!vsewReg.orR) { 1409 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1410 }.otherwise { 1411 genCsBundle_VEC_RGATHEREI16(4) 1412 } 1413 } 1414 is("b011".U) { 1415 genCsBundle_VEC_RGATHEREI16(8) 1416 } 1417 } 1418 } 1419 is(UopSplitType.VEC_COMPRESS) { 1420 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1421 for (i <- 0 until len){ 1422 val jlen = if (i == len-1) i+1 else i+2 1423 for (j <- 0 until jlen) { 1424 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1425 val vd = if(i==len-1) (dest + j.U) else{ 1426 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1427 } 1428 val src23Type = if (j == i+1) DontCare else SrcType.vp 1429 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1430 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1431 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1432 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1433 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1434 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1435 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1436 csBundle(i*(i+3)/2 + j).ldest := vd 1437 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1438 } 1439 } 1440 } 1441 switch(vlmulReg) { 1442 is("b001".U ){ 1443 genCsBundle_VEC_COMPRESS(2) 1444 } 1445 is("b010".U ){ 1446 genCsBundle_VEC_COMPRESS(4) 1447 } 1448 is("b011".U ){ 1449 genCsBundle_VEC_COMPRESS(8) 1450 } 1451 } 1452 } 1453 is(UopSplitType.VEC_MVNR) { 1454 for (i <- 0 until MAX_VLMUL) { 1455 csBundle(i).lsrc(0) := src1 + i.U 1456 csBundle(i).lsrc(1) := src2 + i.U 1457 csBundle(i).lsrc(2) := dest + i.U 1458 csBundle(i).ldest := dest + i.U 1459 csBundle(i).uopIdx := i.U 1460 } 1461 } 1462 is(UopSplitType.VEC_US_LD) { 1463 /* 1464 FMV.D.X 1465 */ 1466 csBundle(0).srcType(0) := SrcType.reg 1467 csBundle(0).srcType(1) := SrcType.imm 1468 csBundle(0).lsrc(1) := 0.U 1469 csBundle(0).ldest := FP_TMP_REG_MV.U 1470 csBundle(0).fuType := FuType.i2f.U 1471 csBundle(0).rfWen := false.B 1472 csBundle(0).fpWen := true.B 1473 csBundle(0).vecWen := false.B 1474 csBundle(0).fpu.isAddSub := false.B 1475 csBundle(0).fpu.typeTagIn := FPU.D 1476 csBundle(0).fpu.typeTagOut := FPU.D 1477 csBundle(0).fpu.fromInt := true.B 1478 csBundle(0).fpu.wflags := false.B 1479 csBundle(0).fpu.fpWen := true.B 1480 csBundle(0).fpu.div := false.B 1481 csBundle(0).fpu.sqrt := false.B 1482 csBundle(0).fpu.fcvt := false.B 1483 //LMUL 1484 for (i <- 0 until MAX_VLMUL) { 1485 csBundle(i + 1).srcType(0) := SrcType.fp 1486 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1487 csBundle(i + 1).ldest := dest + i.U 1488 csBundle(i + 1).uopIdx := i.U 1489 } 1490 } 1491 } 1492 1493 //uops dispatch 1494 val s_normal :: s_ext :: Nil = Enum(2) 1495 val state = RegInit(s_normal) 1496 val state_next = WireDefault(state) 1497 val uopRes = RegInit(0.U) 1498 1499 //readyFromRename Counter 1500 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1501 1502 switch(state) { 1503 is(s_normal) { 1504 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1505 } 1506 is(s_ext) { 1507 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1508 } 1509 } 1510 1511 state := state_next 1512 1513 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1514 val uopResJudge = Mux(state === s_normal, 1515 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1516 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1517 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1518 1519 for(i <- 0 until RenameWidth) { 1520 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1521 (state === s_normal) -> csBundle(i), 1522 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1523 ).toSeq) 1524 } 1525 1526 val validSimple = Wire(Vec(DecodeWidth, Bool())) 1527 validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1528 val notInf = Wire(Vec(DecodeWidth, Bool())) 1529 notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1530 notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1531 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1532 notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1533 1534 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1535 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1536 0.U) 1537 validToRename.zipWithIndex.foreach{ 1538 case(dst, i) => 1539 val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1540 dst := MuxCase(false.B, Seq( 1541 (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1542 (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1543 ).toSeq) 1544 } 1545 1546 readyToIBuf.zipWithIndex.foreach { 1547 case (dst, i) => 1548 val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1549 dst := MuxCase(true.B, Seq( 1550 (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1551 (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1552 ).toSeq) 1553 } 1554 1555 io.deq.decodedInsts := decodedInsts 1556 io.deq.isVset := isVsetSimple 1557 io.deq.complexNum := complexNum 1558 io.deq.validToRename := validToRename 1559 io.deq.readyToIBuf := readyToIBuf 1560 1561} 1562