1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import org.chipsalliance.cde.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul} 34import yunsuan.VpermType 35import scala.collection.Seq 36import chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 37 38class indexedLSUopTable(uopIdx:Int) extends Module { 39 val src = IO(Input(UInt(7.W))) 40 val outOffsetVs2 = IO(Output(UInt(3.W))) 41 val outOffsetVd = IO(Output(UInt(3.W))) 42 val outIsFirstUopInVd = IO(Output(Bool())) 43 def genCsBundle_VEC_INDEXED_LDST(lmul:Int, emul:Int, nfields:Int, uopIdx:Int): (Int, Int, Int) ={ 44 if (lmul * nfields <= 8) { 45 for (k <-0 until nfields) { 46 if (lmul < emul) { // lmul < emul, uop num is depend on emul * nf 47 var offset = 1 << (emul - lmul) 48 for (i <- 0 until (1 << emul)) { 49 if (uopIdx == k * (1 << emul) + i) { 50 return (i, i / offset + k * (1 << lmul), if (i % offset == 0) 1 else 0) 51 } 52 } 53 } else { // lmul > emul, uop num is depend on lmul * nf 54 var offset = 1 << (lmul - emul) 55 for (i <- 0 until (1 << lmul)) { 56 if (uopIdx == k * (1 << lmul) + i) { 57 return (i / offset, i + k * (1 << lmul), 1) 58 } 59 } 60 } 61 } 62 } 63 return (0, 0, 1) 64 } 65 // strided load/store 66 var combVemulNf : Seq[(Int, Int, Int, Int, Int, Int)] = Seq() 67 for (emul <- 0 until 4) { 68 for (lmul <- 0 until 4) { 69 for (nf <- 0 until 8) { 70 var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, nf+1, uopIdx) 71 var offsetVs2 = offset._1 72 var offsetVd = offset._2 73 var isFirstUopInVd = offset._3 74 combVemulNf :+= (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) 75 } 76 } 77 } 78 val out = decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 79 case (emul, lmul, nf, isFirstUopInVd, offsetVs2, offsetVd) => 80 (BitPat((emul << 5 | lmul << 3 | nf).U(7.W)), BitPat((isFirstUopInVd << 6 | offsetVs2 << 3 | offsetVd).U(7.W))) 81 }, BitPat.N(7))) 82 outOffsetVs2 := out(5, 3) 83 outOffsetVd := out(2, 0) 84 outIsFirstUopInVd := out(6).asBool 85} 86 87trait VectorConstants { 88 val MAX_VLMUL = 8 89 val FP_TMP_REG_MV = 32 90 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 91 val MAX_INDEXED_LS_UOPNUM = 64 92} 93 94class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 95 val redirect = Input(Bool()) 96 val csrCtrl = Input(new CustomCSRCtrlIO) 97 // When the first inst in decode vector is complex inst, pass it in 98 val in = Flipped(DecoupledIO(new Bundle { 99 val simpleDecodedInst = new DecodedInst 100 val uopInfo = new UopInfo 101 })) 102 val out = new Bundle { 103 val complexDecodedInsts = Vec(RenameWidth, DecoupledIO(new DecodedInst)) 104 } 105 val complexNum = Output(UInt(3.W)) 106} 107 108/** 109 * @author zly 110 */ 111class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 112 val io = IO(new DecodeUnitCompIO) 113 114 // alias 115 private val inReady = io.in.ready 116 private val inValid = io.in.valid 117 private val inDecodedInst = WireInit(io.in.bits.simpleDecodedInst) 118 private val inInstFields = io.in.bits.simpleDecodedInst.instr.asTypeOf(new XSInstBitFields) 119 private val inUopInfo = io.in.bits.uopInfo 120 private val outValids = io.out.complexDecodedInsts.map(_.valid) 121 private val outReadys = io.out.complexDecodedInsts.map(_.ready) 122 private val outDecodedInsts = io.out.complexDecodedInsts.map(_.bits) 123 private val outComplexNum = io.complexNum 124 125 val maxUopSize = MaxUopSize 126 when (io.in.fire && io.in.bits.simpleDecodedInst.isVset) { 127 when(inInstFields.RD === 0.U && inInstFields.RS1 === 0.U) { 128 inDecodedInst.fuOpType := VSETOpType.keepVl(io.in.bits.simpleDecodedInst.fuOpType) 129 }.elsewhen(inInstFields.RS1 === 0.U) { 130 inDecodedInst.fuOpType := VSETOpType.setVlmax(io.in.bits.simpleDecodedInst.fuOpType) 131 } 132 } 133 134 val latchedInst = RegEnable(inDecodedInst, inValid && inReady) 135 val latchedUopInfo = RegEnable(inUopInfo, inValid && inReady) 136 //input bits 137 private val instFields: XSInstBitFields = latchedInst.instr.asTypeOf(new XSInstBitFields) 138 139 val src1 = Cat(0.U(1.W), instFields.RS1) 140 val src2 = Cat(0.U(1.W), instFields.RS2) 141 val dest = Cat(0.U(1.W), instFields.RD) 142 143 val nf = instFields.NF 144 val width = instFields.WIDTH(1, 0) 145 146 //output of DecodeUnit 147 val numOfUop = Wire(UInt(log2Up(maxUopSize).W)) 148 val numOfWB = Wire(UInt(log2Up(maxUopSize).W)) 149 val lmul = Wire(UInt(4.W)) 150 val isVsetSimple = Wire(Bool()) 151 152 val indexedLSRegOffset = Seq.tabulate(MAX_INDEXED_LS_UOPNUM)(i => Module(new indexedLSUopTable(i))) 153 indexedLSRegOffset.map(_.src := 0.U) 154 155 //pre decode 156 lmul := latchedUopInfo.lmul 157 isVsetSimple := latchedInst.isVset 158 val vlmulReg = latchedInst.vpu.vlmul 159 val vsewReg = latchedInst.vpu.vsew 160 161 //Type of uop Div 162 val typeOfSplit = latchedInst.uopSplitType 163 val src1Type = latchedInst.srcType(0) 164 val src1IsImm = src1Type === SrcType.imm 165 166 numOfUop := latchedUopInfo.numOfUop 167 numOfWB := latchedUopInfo.numOfWB 168 169 //uops dispatch 170 val s_idle :: s_active :: Nil = Enum(2) 171 val state = RegInit(s_idle) 172 val stateNext = WireDefault(state) 173 val numDecodedUop = RegInit(0.U(log2Up(maxUopSize).W)) 174 val uopRes = RegInit(0.U(log2Up(maxUopSize).W)) 175 val uopResNext = WireInit(uopRes) 176 177 //uop div up to maxUopSize 178 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 179 csBundle.foreach { case dst => 180 dst := latchedInst 181 dst.numUops := latchedUopInfo.numOfUop 182 dst.numWB := latchedUopInfo.numOfWB 183 dst.firstUop := false.B 184 dst.lastUop := false.B 185 dst.vlsInstr := false.B 186 } 187 188 csBundle(0).firstUop := true.B 189 csBundle(numOfUop - 1.U).lastUop := true.B 190 191 switch(typeOfSplit) { 192 is(UopSplitType.VSET) { 193 // In simple decoder, rfWen and vecWen are not set 194 when(isVsetSimple) { 195 // Default 196 // uop0 set rd, never flushPipe 197 csBundle(0).fuType := FuType.vsetiwi.U 198 csBundle(0).flushPipe := false.B 199 csBundle(0).rfWen := true.B 200 // uop1 set vl, vsetvl will flushPipe 201 csBundle(1).ldest := VCONFIG_IDX.U 202 csBundle(1).vecWen := true.B 203 when(VSETOpType.isVsetvli(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 204 csBundle(1).fuType := FuType.vsetfwf.U 205 csBundle(1).srcType(0) := SrcType.vp 206 csBundle(1).lsrc(0) := VCONFIG_IDX.U 207 }.elsewhen(VSETOpType.isVsetvl(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 208 // uop0: mv vtype gpr to vector region 209 csBundle(0).srcType(0) := SrcType.xp 210 csBundle(0).srcType(1) := SrcType.no 211 csBundle(0).lsrc(1) := 0.U 212 csBundle(0).ldest := FP_TMP_REG_MV.U 213 csBundle(0).fuType := FuType.i2f.U 214 csBundle(0).fpWen := true.B 215 csBundle(0).fpu.isAddSub := false.B 216 csBundle(0).fpu.typeTagIn := FPU.D 217 csBundle(0).fpu.typeTagOut := FPU.D 218 csBundle(0).fpu.fromInt := true.B 219 csBundle(0).fpu.wflags := false.B 220 csBundle(0).fpu.fpWen := true.B 221 csBundle(0).fpu.div := false.B 222 csBundle(0).fpu.sqrt := false.B 223 csBundle(0).fpu.fcvt := false.B 224 csBundle(0).flushPipe := false.B 225 // uop1: uvsetvcfg_vv 226 csBundle(1).fuType := FuType.vsetfwf.U 227 // vl 228 csBundle(1).srcType(0) := SrcType.vp 229 csBundle(1).lsrc(0) := VCONFIG_IDX.U 230 // vtype 231 csBundle(1).srcType(1) := SrcType.fp 232 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 233 csBundle(1).vecWen := true.B 234 csBundle(1).ldest := VCONFIG_IDX.U 235 } 236 } 237 } 238 is(UopSplitType.VEC_VVV) { 239 for (i <- 0 until MAX_VLMUL) { 240 csBundle(i).lsrc(0) := src1 + i.U 241 csBundle(i).lsrc(1) := src2 + i.U 242 csBundle(i).lsrc(2) := dest + i.U 243 csBundle(i).ldest := dest + i.U 244 csBundle(i).uopIdx := i.U 245 } 246 } 247 is(UopSplitType.VEC_VFV) { 248 for (i <- 0 until MAX_VLMUL) { 249 csBundle(i).lsrc(1) := src2 + i.U 250 csBundle(i).lsrc(2) := dest + i.U 251 csBundle(i).ldest := dest + i.U 252 csBundle(i).uopIdx := i.U 253 } 254 } 255 is(UopSplitType.VEC_EXT2) { 256 for (i <- 0 until MAX_VLMUL / 2) { 257 csBundle(2 * i).lsrc(1) := src2 + i.U 258 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 259 csBundle(2 * i).ldest := dest + (2 * i).U 260 csBundle(2 * i).uopIdx := (2 * i).U 261 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 262 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 263 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 264 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 265 } 266 } 267 is(UopSplitType.VEC_EXT4) { 268 for (i <- 0 until MAX_VLMUL / 4) { 269 csBundle(4 * i).lsrc(1) := src2 + i.U 270 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 271 csBundle(4 * i).ldest := dest + (4 * i).U 272 csBundle(4 * i).uopIdx := (4 * i).U 273 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 274 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 275 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 276 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 277 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 278 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 279 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 280 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 281 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 282 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 283 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 284 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 285 } 286 } 287 is(UopSplitType.VEC_EXT8) { 288 for (i <- 0 until MAX_VLMUL) { 289 csBundle(i).lsrc(1) := src2 290 csBundle(i).lsrc(2) := dest + i.U 291 csBundle(i).ldest := dest + i.U 292 csBundle(i).uopIdx := i.U 293 } 294 } 295 is(UopSplitType.VEC_0XV) { 296 /* 297 FMV.D.X 298 */ 299 csBundle(0).srcType(0) := SrcType.reg 300 csBundle(0).srcType(1) := SrcType.imm 301 csBundle(0).lsrc(1) := 0.U 302 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 303 csBundle(0).fuType := FuType.i2v.U 304 csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), vsewReg) 305 csBundle(0).rfWen := false.B 306 csBundle(0).fpWen := false.B 307 csBundle(0).vecWen := true.B 308 /* 309 vmv.s.x 310 */ 311 csBundle(1).srcType(0) := SrcType.vp 312 csBundle(1).srcType(1) := SrcType.imm 313 csBundle(1).srcType(2) := SrcType.vp 314 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 315 csBundle(1).lsrc(1) := 0.U 316 csBundle(1).lsrc(2) := dest 317 csBundle(1).ldest := dest 318 csBundle(1).rfWen := false.B 319 csBundle(1).fpWen := false.B 320 csBundle(1).vecWen := true.B 321 csBundle(1).uopIdx := 0.U 322 } 323 is(UopSplitType.VEC_VXV) { 324 /* 325 i to vector move 326 */ 327 csBundle(0).srcType(0) := SrcType.reg 328 csBundle(0).srcType(1) := SrcType.imm 329 csBundle(0).lsrc(1) := 0.U 330 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 331 csBundle(0).fuType := FuType.i2v.U 332 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 333 csBundle(0).vecWen := true.B 334 /* 335 LMUL 336 */ 337 for (i <- 0 until MAX_VLMUL) { 338 csBundle(i + 1).srcType(0) := SrcType.vp 339 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 340 csBundle(i + 1).lsrc(1) := src2 + i.U 341 csBundle(i + 1).lsrc(2) := dest + i.U 342 csBundle(i + 1).ldest := dest + i.U 343 csBundle(i + 1).uopIdx := i.U 344 } 345 } 346 is(UopSplitType.VEC_VVW) { 347 for (i <- 0 until MAX_VLMUL / 2) { 348 csBundle(2 * i).lsrc(0) := src1 + i.U 349 csBundle(2 * i).lsrc(1) := src2 + i.U 350 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 351 csBundle(2 * i).ldest := dest + (2 * i).U 352 csBundle(2 * i).uopIdx := (2 * i).U 353 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 354 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 355 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 356 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 357 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 358 } 359 } 360 is(UopSplitType.VEC_VFW) { 361 for (i <- 0 until MAX_VLMUL / 2) { 362 csBundle(2 * i).lsrc(0) := src1 363 csBundle(2 * i).lsrc(1) := src2 + i.U 364 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 365 csBundle(2 * i).ldest := dest + (2 * i).U 366 csBundle(2 * i).uopIdx := (2 * i).U 367 csBundle(2 * i + 1).lsrc(0) := src1 368 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 369 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 370 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 371 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 372 } 373 } 374 is(UopSplitType.VEC_WVW) { 375 for (i <- 0 until MAX_VLMUL / 2) { 376 csBundle(2 * i).lsrc(0) := src1 + i.U 377 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 378 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 379 csBundle(2 * i).ldest := dest + (2 * i).U 380 csBundle(2 * i).uopIdx := (2 * i).U 381 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 382 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 383 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 384 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 385 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 386 } 387 } 388 is(UopSplitType.VEC_VXW) { 389 /* 390 i to vector move 391 */ 392 csBundle(0).srcType(0) := SrcType.reg 393 csBundle(0).srcType(1) := SrcType.imm 394 csBundle(0).lsrc(1) := 0.U 395 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 396 csBundle(0).fuType := FuType.i2v.U 397 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 398 csBundle(0).vecWen := true.B 399 400 for (i <- 0 until MAX_VLMUL / 2) { 401 csBundle(2 * i + 1).srcType(0) := SrcType.vp 402 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 403 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 404 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 405 csBundle(2 * i + 1).ldest := dest + (2 * i).U 406 csBundle(2 * i + 1).uopIdx := (2 * i).U 407 csBundle(2 * i + 2).srcType(0) := SrcType.vp 408 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 409 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 410 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 411 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 412 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 413 } 414 } 415 is(UopSplitType.VEC_WXW) { 416 /* 417 i to vector move 418 */ 419 csBundle(0).srcType(0) := SrcType.reg 420 csBundle(0).srcType(1) := SrcType.imm 421 csBundle(0).lsrc(1) := 0.U 422 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 423 csBundle(0).fuType := FuType.i2v.U 424 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 425 csBundle(0).vecWen := true.B 426 427 for (i <- 0 until MAX_VLMUL / 2) { 428 csBundle(2 * i + 1).srcType(0) := SrcType.vp 429 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 430 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 431 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 432 csBundle(2 * i + 1).ldest := dest + (2 * i).U 433 csBundle(2 * i + 1).uopIdx := (2 * i).U 434 csBundle(2 * i + 2).srcType(0) := SrcType.vp 435 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 436 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 437 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 438 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 439 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 440 } 441 } 442 is(UopSplitType.VEC_WVV) { 443 for (i <- 0 until MAX_VLMUL / 2) { 444 445 csBundle(2 * i).lsrc(0) := src1 + i.U 446 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 447 csBundle(2 * i).lsrc(2) := dest + i.U 448 csBundle(2 * i).ldest := dest + i.U 449 csBundle(2 * i).uopIdx := (2 * i).U 450 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 451 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 452 csBundle(2 * i + 1).lsrc(2) := dest + i.U 453 csBundle(2 * i + 1).ldest := dest + i.U 454 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 455 } 456 } 457 is(UopSplitType.VEC_WFW) { 458 for (i <- 0 until MAX_VLMUL / 2) { 459 csBundle(2 * i).lsrc(0) := src1 460 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 461 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 462 csBundle(2 * i).ldest := dest + (2 * i).U 463 csBundle(2 * i).uopIdx := (2 * i).U 464 csBundle(2 * i + 1).lsrc(0) := src1 465 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 466 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 467 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 468 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 469 } 470 } 471 is(UopSplitType.VEC_WXV) { 472 /* 473 i to vector move 474 */ 475 csBundle(0).srcType(0) := SrcType.reg 476 csBundle(0).srcType(1) := SrcType.imm 477 csBundle(0).lsrc(1) := 0.U 478 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 479 csBundle(0).fuType := FuType.i2v.U 480 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 481 csBundle(0).vecWen := true.B 482 483 for (i <- 0 until MAX_VLMUL / 2) { 484 csBundle(2 * i + 1).srcType(0) := SrcType.vp 485 csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 486 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 487 csBundle(2 * i + 1).lsrc(2) := dest + i.U 488 csBundle(2 * i + 1).ldest := dest + i.U 489 csBundle(2 * i + 1).uopIdx := (2 * i).U 490 csBundle(2 * i + 2).srcType(0) := SrcType.vp 491 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 492 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 493 csBundle(2 * i + 2).lsrc(2) := dest + i.U 494 csBundle(2 * i + 2).ldest := dest + i.U 495 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 496 } 497 } 498 is(UopSplitType.VEC_VVM) { 499 csBundle(0).lsrc(2) := dest 500 csBundle(0).ldest := dest 501 csBundle(0).uopIdx := 0.U 502 for (i <- 1 until MAX_VLMUL) { 503 csBundle(i).lsrc(0) := src1 + i.U 504 csBundle(i).lsrc(1) := src2 + i.U 505 csBundle(i).lsrc(2) := dest 506 csBundle(i).ldest := dest 507 csBundle(i).uopIdx := i.U 508 } 509 } 510 is(UopSplitType.VEC_VFM) { 511 csBundle(0).lsrc(2) := dest 512 csBundle(0).ldest := dest 513 csBundle(0).uopIdx := 0.U 514 for (i <- 1 until MAX_VLMUL) { 515 csBundle(i).lsrc(0) := src1 516 csBundle(i).lsrc(1) := src2 + i.U 517 csBundle(i).lsrc(2) := dest 518 csBundle(i).ldest := dest 519 csBundle(i).uopIdx := i.U 520 } 521 csBundle(numOfUop - 1.U).ldest := dest 522 } 523 is(UopSplitType.VEC_VXM) { 524 /* 525 i to vector move 526 */ 527 csBundle(0).srcType(0) := SrcType.reg 528 csBundle(0).srcType(1) := SrcType.imm 529 csBundle(0).lsrc(1) := 0.U 530 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 531 csBundle(0).fuType := FuType.i2v.U 532 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 533 csBundle(0).vecWen := true.B 534 //LMUL 535 csBundle(1).srcType(0) := SrcType.vp 536 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 537 csBundle(1).lsrc(2) := dest 538 csBundle(1).ldest := dest 539 csBundle(1).uopIdx := 0.U 540 for (i <- 1 until MAX_VLMUL) { 541 csBundle(i + 1).srcType(0) := SrcType.vp 542 csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 543 csBundle(i + 1).lsrc(1) := src2 + i.U 544 csBundle(i + 1).lsrc(2) := dest 545 csBundle(i + 1).ldest := dest 546 csBundle(i + 1).uopIdx := i.U 547 } 548 csBundle(numOfUop - 1.U).ldest := dest 549 } 550 is(UopSplitType.VEC_SLIDE1UP) { 551 /* 552 i to vector move 553 */ 554 csBundle(0).srcType(0) := SrcType.reg 555 csBundle(0).srcType(1) := SrcType.imm 556 csBundle(0).lsrc(1) := 0.U 557 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 558 csBundle(0).fuType := FuType.i2v.U 559 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 560 csBundle(0).vecWen := true.B 561 //LMUL 562 csBundle(1).srcType(0) := SrcType.vp 563 csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 564 csBundle(1).lsrc(2) := dest 565 csBundle(1).ldest := dest 566 csBundle(1).uopIdx := 0.U 567 for (i <- 1 until MAX_VLMUL) { 568 csBundle(i + 1).srcType(0) := SrcType.vp 569 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 570 csBundle(i + 1).lsrc(1) := src2 + i.U 571 csBundle(i + 1).lsrc(2) := dest + i.U 572 csBundle(i + 1).ldest := dest + i.U 573 csBundle(i + 1).uopIdx := i.U 574 } 575 } 576 is(UopSplitType.VEC_FSLIDE1UP) { 577 //LMUL 578 csBundle(0).srcType(0) := SrcType.fp 579 csBundle(0).lsrc(0) := src1 580 csBundle(0).lsrc(1) := src2 581 csBundle(0).lsrc(2) := dest 582 csBundle(0).ldest := dest 583 csBundle(0).uopIdx := 0.U 584 for (i <- 1 until MAX_VLMUL) { 585 csBundle(i).srcType(0) := SrcType.vp 586 csBundle(i).lsrc(0) := src2 + (i - 1).U 587 csBundle(i).lsrc(1) := src2 + i.U 588 csBundle(i).lsrc(2) := dest + i.U 589 csBundle(i).ldest := dest + i.U 590 csBundle(i).uopIdx := i.U 591 } 592 } 593 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 594 /* 595 i to vector move 596 */ 597 csBundle(0).srcType(0) := SrcType.reg 598 csBundle(0).srcType(1) := SrcType.imm 599 csBundle(0).lsrc(1) := 0.U 600 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 601 csBundle(0).fuType := FuType.i2v.U 602 csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 603 csBundle(0).vecWen := true.B 604 //LMUL 605 for (i <- 0 until MAX_VLMUL) { 606 csBundle(2 * i + 1).srcType(0) := SrcType.vp 607 csBundle(2 * i + 1).srcType(1) := SrcType.vp 608 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 609 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 610 csBundle(2 * i + 1).lsrc(2) := dest + i.U 611 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 612 csBundle(2 * i + 1).uopIdx := (2 * i).U 613 if (2 * i + 2 < MAX_VLMUL * 2) { 614 csBundle(2 * i + 2).srcType(0) := SrcType.vp 615 csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 616 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 617 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 618 csBundle(2 * i + 2).ldest := dest + i.U 619 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 620 } 621 } 622 csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 623 csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 624 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 625 } 626 is(UopSplitType.VEC_FSLIDE1DOWN) { 627 //LMUL 628 for (i <- 0 until MAX_VLMUL) { 629 csBundle(2 * i).srcType(0) := SrcType.vp 630 csBundle(2 * i).srcType(1) := SrcType.vp 631 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 632 csBundle(2 * i).lsrc(1) := src2 + i.U 633 csBundle(2 * i).lsrc(2) := dest + i.U 634 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 635 csBundle(2 * i).uopIdx := (2 * i).U 636 csBundle(2 * i + 1).srcType(0) := SrcType.fp 637 csBundle(2 * i + 1).lsrc(0) := src1 638 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 639 csBundle(2 * i + 1).ldest := dest + i.U 640 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 641 } 642 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 643 csBundle(numOfUop - 1.U).lsrc(0) := src1 644 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 645 } 646 is(UopSplitType.VEC_VRED) { 647 when(vlmulReg === "b001".U) { 648 csBundle(0).srcType(2) := SrcType.DC 649 csBundle(0).lsrc(0) := src2 + 1.U 650 csBundle(0).lsrc(1) := src2 651 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 652 csBundle(0).uopIdx := 0.U 653 } 654 when(vlmulReg === "b010".U) { 655 csBundle(0).srcType(2) := SrcType.DC 656 csBundle(0).lsrc(0) := src2 + 1.U 657 csBundle(0).lsrc(1) := src2 658 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 659 csBundle(0).uopIdx := 0.U 660 661 csBundle(1).srcType(2) := SrcType.DC 662 csBundle(1).lsrc(0) := src2 + 3.U 663 csBundle(1).lsrc(1) := src2 + 2.U 664 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 665 csBundle(1).uopIdx := 1.U 666 667 csBundle(2).srcType(2) := SrcType.DC 668 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 669 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 670 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 671 csBundle(2).uopIdx := 2.U 672 } 673 when(vlmulReg === "b011".U) { 674 for (i <- 0 until MAX_VLMUL) { 675 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 676 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 677 csBundle(i).lsrc(1) := src2 + (i * 2).U 678 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 679 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 680 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 681 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 682 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 683 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 684 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 685 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 686 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 687 } 688 csBundle(i).srcType(2) := SrcType.DC 689 csBundle(i).uopIdx := i.U 690 } 691 } 692 when(vlmulReg(2) === 0.U && vlmulReg(1, 0).orR) { 693 /* 694 * 2 <= vlmul <= 8 695 */ 696 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 697 csBundle(numOfUop - 1.U).lsrc(0) := src1 698 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 699 csBundle(numOfUop - 1.U).lsrc(2) := dest 700 csBundle(numOfUop - 1.U).ldest := dest 701 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 702 } 703 } 704 is(UopSplitType.VEC_VFRED) { 705 val vlmul = vlmulReg 706 val vsew = vsewReg 707 when(vlmul === VLmul.m8){ 708 for (i <- 0 until 4) { 709 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 710 csBundle(i).lsrc(1) := src2 + (i * 2).U 711 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 712 csBundle(i).uopIdx := i.U 713 } 714 for (i <- 4 until 6) { 715 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 716 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 717 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 718 csBundle(i).uopIdx := i.U 719 } 720 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 721 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 722 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 723 csBundle(6).uopIdx := 6.U 724 when(vsew === VSew.e64) { 725 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 726 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 727 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 728 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 729 csBundle(7).uopIdx := 7.U 730 csBundle(8).lsrc(0) := src1 731 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 732 csBundle(8).ldest := dest 733 csBundle(8).uopIdx := 8.U 734 } 735 when(vsew === VSew.e32) { 736 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 737 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 738 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 739 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 740 csBundle(7).uopIdx := 7.U 741 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 742 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 743 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 744 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 745 csBundle(8).uopIdx := 8.U 746 csBundle(9).lsrc(0) := src1 747 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 748 csBundle(9).ldest := dest 749 csBundle(9).uopIdx := 9.U 750 } 751 when(vsew === VSew.e16) { 752 csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 753 csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 754 csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 755 csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 756 csBundle(7).uopIdx := 7.U 757 csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 758 csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 759 csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 760 csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 761 csBundle(8).uopIdx := 8.U 762 csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 763 csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 764 csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 765 csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 766 csBundle(9).uopIdx := 9.U 767 csBundle(10).lsrc(0) := src1 768 csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 769 csBundle(10).ldest := dest 770 csBundle(10).uopIdx := 10.U 771 } 772 } 773 when(vlmul === VLmul.m4) { 774 for (i <- 0 until 2) { 775 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 776 csBundle(i).lsrc(1) := src2 + (i * 2).U 777 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 778 csBundle(i).uopIdx := i.U 779 } 780 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 781 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 782 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 783 csBundle(2).uopIdx := 2.U 784 when(vsew === VSew.e64) { 785 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 786 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 787 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 788 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 789 csBundle(3).uopIdx := 3.U 790 csBundle(4).lsrc(0) := src1 791 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 792 csBundle(4).ldest := dest 793 csBundle(4).uopIdx := 4.U 794 } 795 when(vsew === VSew.e32) { 796 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 797 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 798 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 799 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 800 csBundle(3).uopIdx := 3.U 801 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 802 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 803 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 804 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 805 csBundle(4).uopIdx := 4.U 806 csBundle(5).lsrc(0) := src1 807 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 808 csBundle(5).ldest := dest 809 csBundle(5).uopIdx := 5.U 810 } 811 when(vsew === VSew.e16) { 812 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 813 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 814 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 815 csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 816 csBundle(3).uopIdx := 3.U 817 csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 818 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 819 csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 820 csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 821 csBundle(4).uopIdx := 4.U 822 csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 823 csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 824 csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 825 csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 826 csBundle(5).uopIdx := 5.U 827 csBundle(6).lsrc(0) := src1 828 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 829 csBundle(6).ldest := dest 830 csBundle(6).uopIdx := 6.U 831 } 832 } 833 when(vlmul === VLmul.m2) { 834 csBundle(0).lsrc(0) := src2 + 1.U 835 csBundle(0).lsrc(1) := src2 + 0.U 836 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 837 csBundle(0).uopIdx := 0.U 838 when(vsew === VSew.e64) { 839 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 840 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 841 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 842 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 843 csBundle(1).uopIdx := 1.U 844 csBundle(2).lsrc(0) := src1 845 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 846 csBundle(2).ldest := dest 847 csBundle(2).uopIdx := 2.U 848 } 849 when(vsew === VSew.e32) { 850 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 851 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 852 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 853 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 854 csBundle(1).uopIdx := 1.U 855 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 856 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 857 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 858 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 859 csBundle(2).uopIdx := 2.U 860 csBundle(3).lsrc(0) := src1 861 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 862 csBundle(3).ldest := dest 863 csBundle(3).uopIdx := 3.U 864 } 865 when(vsew === VSew.e16) { 866 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 867 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 868 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 869 csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 870 csBundle(1).uopIdx := 1.U 871 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 872 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 873 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 874 csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 875 csBundle(2).uopIdx := 2.U 876 csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 877 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 878 csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 879 csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 880 csBundle(3).uopIdx := 3.U 881 csBundle(4).lsrc(0) := src1 882 csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 883 csBundle(4).ldest := dest 884 csBundle(4).uopIdx := 4.U 885 } 886 } 887 when(vlmul === VLmul.m1) { 888 when(vsew === VSew.e64) { 889 csBundle(0).lsrc(0) := src2 890 csBundle(0).lsrc(1) := src2 891 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 892 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 893 csBundle(0).uopIdx := 0.U 894 csBundle(1).lsrc(0) := src1 895 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 896 csBundle(1).ldest := dest 897 csBundle(1).uopIdx := 1.U 898 } 899 when(vsew === VSew.e32) { 900 csBundle(0).lsrc(0) := src2 901 csBundle(0).lsrc(1) := src2 902 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 903 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 904 csBundle(0).uopIdx := 0.U 905 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 906 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 907 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 908 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 909 csBundle(1).uopIdx := 1.U 910 csBundle(2).lsrc(0) := src1 911 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 912 csBundle(2).ldest := dest 913 csBundle(2).uopIdx := 2.U 914 } 915 when(vsew === VSew.e16) { 916 csBundle(0).lsrc(0) := src2 917 csBundle(0).lsrc(1) := src2 918 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 919 csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 920 csBundle(0).uopIdx := 0.U 921 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 922 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 923 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 924 csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 925 csBundle(1).uopIdx := 1.U 926 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 927 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 928 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 929 csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 930 csBundle(2).uopIdx := 2.U 931 csBundle(3).lsrc(0) := src1 932 csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 933 csBundle(3).ldest := dest 934 csBundle(3).uopIdx := 3.U 935 } 936 } 937 when(vlmul === VLmul.mf2) { 938 when(vsew === VSew.e32) { 939 csBundle(0).lsrc(0) := src2 940 csBundle(0).lsrc(1) := src2 941 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 942 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 943 csBundle(0).uopIdx := 0.U 944 csBundle(1).lsrc(0) := src1 945 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 946 csBundle(1).ldest := dest 947 csBundle(1).uopIdx := 1.U 948 } 949 when(vsew === VSew.e16) { 950 csBundle(0).lsrc(0) := src2 951 csBundle(0).lsrc(1) := src2 952 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 953 csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 954 csBundle(0).uopIdx := 0.U 955 csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 956 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 957 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 958 csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 959 csBundle(1).uopIdx := 1.U 960 csBundle(2).lsrc(0) := src1 961 csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 962 csBundle(2).ldest := dest 963 csBundle(2).uopIdx := 2.U 964 } 965 } 966 when(vlmul === VLmul.mf4) { 967 when(vsew === VSew.e16) { 968 csBundle(0).lsrc(0) := src2 969 csBundle(0).lsrc(1) := src2 970 csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 971 csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 972 csBundle(0).uopIdx := 0.U 973 csBundle(1).lsrc(0) := src1 974 csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 975 csBundle(1).ldest := dest 976 csBundle(1).uopIdx := 1.U 977 } 978 } 979 } 980 981 is(UopSplitType.VEC_VFREDOSUM) { 982 import yunsuan.VfaluType 983 val vlmul = vlmulReg 984 val vsew = vsewReg 985 val isWiden = latchedInst.fuOpType === VfaluType.vfwredosum 986 when(vlmul === VLmul.m8) { 987 when(vsew === VSew.e64) { 988 val vlmax = 16 989 for (i <- 0 until vlmax) { 990 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 991 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 992 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 993 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 994 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 995 csBundle(i).uopIdx := i.U 996 } 997 } 998 when(vsew === VSew.e32) { 999 val vlmax = 32 1000 for (i <- 0 until vlmax) { 1001 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1002 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1003 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1004 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1005 csBundle(i).vpu.fpu.isFoldTo1_4 := (if (i % 4 == 0) false.B else true.B) 1006 csBundle(i).uopIdx := i.U 1007 } 1008 } 1009 when(vsew === VSew.e16) { 1010 val vlmax = 64 1011 for (i <- 0 until vlmax) { 1012 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1013 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1014 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1015 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1016 csBundle(i).vpu.fpu.isFoldTo1_8 := (if (i % 8 == 0) false.B else true.B) 1017 csBundle(i).uopIdx := i.U 1018 } 1019 } 1020 } 1021 when(vlmul === VLmul.m4) { 1022 when(vsew === VSew.e64) { 1023 val vlmax = 8 1024 for (i <- 0 until vlmax) { 1025 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1026 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1027 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1028 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1029 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1030 csBundle(i).uopIdx := i.U 1031 } 1032 } 1033 when(vsew === VSew.e32) { 1034 val vlmax = 16 1035 for (i <- 0 until vlmax) { 1036 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1037 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1038 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1039 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1040 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1041 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1042 csBundle(i).uopIdx := i.U 1043 } 1044 } 1045 when(vsew === VSew.e16) { 1046 val vlmax = 32 1047 for (i <- 0 until vlmax) { 1048 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1049 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1050 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1051 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1052 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1053 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1054 csBundle(i).uopIdx := i.U 1055 } 1056 } 1057 } 1058 when(vlmul === VLmul.m2) { 1059 when(vsew === VSew.e64) { 1060 val vlmax = 4 1061 for (i <- 0 until vlmax) { 1062 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1063 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1064 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1065 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1066 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1067 csBundle(i).uopIdx := i.U 1068 } 1069 } 1070 when(vsew === VSew.e32) { 1071 val vlmax = 8 1072 for (i <- 0 until vlmax) { 1073 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1074 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1075 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1076 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1077 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1078 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1079 csBundle(i).uopIdx := i.U 1080 } 1081 } 1082 when(vsew === VSew.e16) { 1083 val vlmax = 16 1084 for (i <- 0 until vlmax) { 1085 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1086 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1087 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1088 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1089 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1090 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1091 csBundle(i).uopIdx := i.U 1092 } 1093 } 1094 } 1095 when(vlmul === VLmul.m1) { 1096 when(vsew === VSew.e64) { 1097 val vlmax = 2 1098 for (i <- 0 until vlmax) { 1099 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1100 csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1101 csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1102 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1103 csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1104 csBundle(i).uopIdx := i.U 1105 } 1106 } 1107 when(vsew === VSew.e32) { 1108 val vlmax = 4 1109 for (i <- 0 until vlmax) { 1110 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1111 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1112 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1113 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1114 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1115 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1116 csBundle(i).uopIdx := i.U 1117 } 1118 } 1119 when(vsew === VSew.e16) { 1120 val vlmax = 8 1121 for (i <- 0 until vlmax) { 1122 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1123 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1124 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1125 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1126 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1127 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1128 csBundle(i).uopIdx := i.U 1129 } 1130 } 1131 } 1132 when(vlmul === VLmul.mf2) { 1133 when(vsew === VSew.e32) { 1134 val vlmax = 2 1135 for (i <- 0 until vlmax) { 1136 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1137 csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1138 csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1139 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1140 csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1141 csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1142 csBundle(i).uopIdx := i.U 1143 } 1144 } 1145 when(vsew === VSew.e16) { 1146 val vlmax = 4 1147 for (i <- 0 until vlmax) { 1148 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1149 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1150 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1151 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1152 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1153 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1154 csBundle(i).uopIdx := i.U 1155 } 1156 } 1157 } 1158 when(vlmul === VLmul.mf4) { 1159 when(vsew === VSew.e16) { 1160 val vlmax = 2 1161 for (i <- 0 until vlmax) { 1162 csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1163 csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1164 csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1165 csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1166 csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1167 csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1168 csBundle(i).uopIdx := i.U 1169 } 1170 } 1171 } 1172 } 1173 1174 is(UopSplitType.VEC_SLIDEUP) { 1175 // i to vector move 1176 csBundle(0).srcType(0) := SrcType.reg 1177 csBundle(0).srcType(1) := SrcType.imm 1178 csBundle(0).lsrc(1) := 0.U 1179 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1180 csBundle(0).fuType := FuType.i2v.U 1181 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1182 csBundle(0).vecWen := true.B 1183 // LMUL 1184 for (i <- 0 until MAX_VLMUL) 1185 for (j <- 0 to i) { 1186 val old_vd = if (j == 0) { 1187 dest + i.U 1188 } else (VECTOR_TMP_REG_LMUL + j).U 1189 val vd = if (j == i) { 1190 dest + i.U 1191 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1192 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1193 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1194 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1195 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1196 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1197 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1198 } 1199 } 1200 1201 is(UopSplitType.VEC_SLIDEDOWN) { 1202 // i to vector move 1203 csBundle(0).srcType(0) := SrcType.reg 1204 csBundle(0).srcType(1) := SrcType.imm 1205 csBundle(0).lsrc(1) := 0.U 1206 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1207 csBundle(0).fuType := FuType.i2v.U 1208 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1209 csBundle(0).vecWen := true.B 1210 // LMUL 1211 for (i <- 0 until MAX_VLMUL) 1212 for (j <- (0 to i).reverse) { 1213 when(i.U < lmul) { 1214 val old_vd = if (j == 0) { 1215 dest + lmul - 1.U - i.U 1216 } else (VECTOR_TMP_REG_LMUL + j).U 1217 val vd = if (j == i) { 1218 dest + lmul - 1.U - i.U 1219 } else (VECTOR_TMP_REG_LMUL + j + 1).U 1220 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1221 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1222 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1223 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1224 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1225 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1226 } 1227 } 1228 } 1229 1230 is(UopSplitType.VEC_M0X) { 1231 // LMUL 1232 for (i <- 0 until MAX_VLMUL) { 1233 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1234 val ldest = (VECTOR_TMP_REG_LMUL + i).U 1235 csBundle(i).srcType(0) := srcType0 1236 csBundle(i).srcType(1) := SrcType.vp 1237 csBundle(i).rfWen := false.B 1238 csBundle(i).fpWen := false.B 1239 csBundle(i).vecWen := true.B 1240 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1241 csBundle(i).lsrc(1) := src2 1242 // csBundle(i).lsrc(2) := dest + i.U DontCare 1243 csBundle(i).ldest := ldest 1244 csBundle(i).uopIdx := i.U 1245 } 1246 csBundle(lmul - 1.U).rfWen := true.B 1247 csBundle(lmul - 1.U).fpWen := false.B 1248 csBundle(lmul - 1.U).vecWen := false.B 1249 csBundle(lmul - 1.U).ldest := dest 1250 } 1251 1252 is(UopSplitType.VEC_MVV) { 1253 // LMUL 1254 for (i <- 0 until MAX_VLMUL) { 1255 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1256 csBundle(i * 2 + 0).srcType(0) := srcType0 1257 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1258 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1259 csBundle(i * 2 + 0).lsrc(1) := src2 1260 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1261 csBundle(i * 2 + 0).ldest := dest + i.U 1262 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1263 1264 csBundle(i * 2 + 1).srcType(0) := srcType0 1265 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1266 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1267 csBundle(i * 2 + 1).lsrc(1) := src2 1268 // csBundle(i).lsrc(2) := dest + i.U DontCare 1269 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1270 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1271 } 1272 } 1273 1274 is(UopSplitType.VEC_M0X_VFIRST) { 1275 // LMUL 1276 csBundle(0).rfWen := true.B 1277 csBundle(0).fpWen := false.B 1278 csBundle(0).vecWen := false.B 1279 csBundle(0).ldest := dest 1280 } 1281 is(UopSplitType.VEC_VWW) { 1282 for (i <- 0 until MAX_VLMUL*2) { 1283 when(i.U < lmul){ 1284 csBundle(i).srcType(2) := SrcType.DC 1285 csBundle(i).lsrc(0) := src2 + i.U 1286 csBundle(i).lsrc(1) := src2 + i.U 1287 // csBundle(i).lsrc(2) := dest + (2 * i).U 1288 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1289 csBundle(i).uopIdx := i.U 1290 } otherwise { 1291 csBundle(i).srcType(2) := SrcType.DC 1292 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1293 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1294 // csBundle(i).lsrc(2) := dest + (2 * i).U 1295 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1296 csBundle(i).uopIdx := i.U 1297 } 1298 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1299 csBundle(numOfUop-1.U).lsrc(0) := src1 1300 csBundle(numOfUop-1.U).lsrc(2) := dest 1301 csBundle(numOfUop-1.U).ldest := dest 1302 } 1303 } 1304 is(UopSplitType.VEC_RGATHER) { 1305 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1306 for (i <- 0 until len) 1307 for (j <- 0 until len) { 1308 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1309 // csBundle(i * len + j).srcType(1) := SrcType.vp 1310 // csBundle(i * len + j).srcType(2) := SrcType.vp 1311 csBundle(i * len + j).lsrc(0) := src1 + i.U 1312 csBundle(i * len + j).lsrc(1) := src2 + j.U 1313 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1314 csBundle(i * len + j).lsrc(2) := vd_old 1315 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1316 csBundle(i * len + j).ldest := vd 1317 csBundle(i * len + j).uopIdx := (i * len + j).U 1318 } 1319 } 1320 switch(vlmulReg) { 1321 is("b001".U ){ 1322 genCsBundle_VEC_RGATHER(2) 1323 } 1324 is("b010".U ){ 1325 genCsBundle_VEC_RGATHER(4) 1326 } 1327 is("b011".U ){ 1328 genCsBundle_VEC_RGATHER(8) 1329 } 1330 } 1331 } 1332 is(UopSplitType.VEC_RGATHER_VX) { 1333 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1334 for (i <- 0 until len) 1335 for (j <- 0 until len) { 1336 csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1337 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1338 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1339 csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1340 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1341 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1342 csBundle(i * len + j + 1).lsrc(2) := vd_old 1343 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1344 csBundle(i * len + j + 1).ldest := vd 1345 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1346 } 1347 } 1348 // i to vector move 1349 csBundle(0).srcType(0) := SrcType.reg 1350 csBundle(0).srcType(1) := SrcType.imm 1351 csBundle(0).lsrc(1) := 0.U 1352 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1353 csBundle(0).fuType := FuType.i2v.U 1354 csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1355 csBundle(0).vecWen := true.B 1356 switch(vlmulReg) { 1357 is("b000".U ){ 1358 genCsBundle_RGATHER_VX(1) 1359 } 1360 is("b001".U ){ 1361 genCsBundle_RGATHER_VX(2) 1362 } 1363 is("b010".U ){ 1364 genCsBundle_RGATHER_VX(4) 1365 } 1366 is("b011".U ){ 1367 genCsBundle_RGATHER_VX(8) 1368 } 1369 } 1370 } 1371 is(UopSplitType.VEC_RGATHEREI16) { 1372 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1373 for (i <- 0 until len) 1374 for (j <- 0 until len) { 1375 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1376 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1377 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1378 // csBundle(i * len + j).srcType(1) := SrcType.vp 1379 // csBundle(i * len + j).srcType(2) := SrcType.vp 1380 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1381 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1382 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1383 csBundle((i * len + j)*2+0).ldest := vd0 1384 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1385 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1386 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1387 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1388 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1389 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1390 csBundle((i * len + j)*2+1).ldest := vd1 1391 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1392 } 1393 } 1394 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1395 for (i <- 0 until len) 1396 for (j <- 0 until len) { 1397 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1398 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1399 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1400 // csBundle(i * len + j).srcType(1) := SrcType.vp 1401 // csBundle(i * len + j).srcType(2) := SrcType.vp 1402 csBundle(i * len + j).lsrc(0) := src1 + i.U 1403 csBundle(i * len + j).lsrc(1) := src2 + j.U 1404 csBundle(i * len + j).lsrc(2) := vd_old 1405 csBundle(i * len + j).ldest := vd 1406 csBundle(i * len + j).uopIdx := (i * len + j).U 1407 } 1408 } 1409 switch(vlmulReg) { 1410 is("b000".U ){ 1411 when(!vsewReg.orR){ 1412 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1413 } .otherwise{ 1414 genCsBundle_VEC_RGATHEREI16(1) 1415 } 1416 } 1417 is("b001".U) { 1418 when(!vsewReg.orR) { 1419 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1420 }.otherwise { 1421 genCsBundle_VEC_RGATHEREI16(2) 1422 } 1423 } 1424 is("b010".U) { 1425 when(!vsewReg.orR) { 1426 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1427 }.otherwise { 1428 genCsBundle_VEC_RGATHEREI16(4) 1429 } 1430 } 1431 is("b011".U) { 1432 genCsBundle_VEC_RGATHEREI16(8) 1433 } 1434 } 1435 } 1436 is(UopSplitType.VEC_COMPRESS) { 1437 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1438 for (i <- 0 until len){ 1439 val jlen = if (i == len-1) i+1 else i+2 1440 for (j <- 0 until jlen) { 1441 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1442 val vd = if(i==len-1) (dest + j.U) else{ 1443 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1444 } 1445 val src23Type = if (j == i+1) DontCare else SrcType.vp 1446 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1447 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1448 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1449 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1450 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1451 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1452 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1453 csBundle(i*(i+3)/2 + j).ldest := vd 1454 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1455 } 1456 } 1457 } 1458 switch(vlmulReg) { 1459 is("b001".U ){ 1460 genCsBundle_VEC_COMPRESS(2) 1461 } 1462 is("b010".U ){ 1463 genCsBundle_VEC_COMPRESS(4) 1464 } 1465 is("b011".U ){ 1466 genCsBundle_VEC_COMPRESS(8) 1467 } 1468 } 1469 } 1470 is(UopSplitType.VEC_MVNR) { 1471 for (i <- 0 until MAX_VLMUL) { 1472 csBundle(i).lsrc(0) := src1 + i.U 1473 csBundle(i).lsrc(1) := src2 + i.U 1474 csBundle(i).lsrc(2) := dest + i.U 1475 csBundle(i).ldest := dest + i.U 1476 csBundle(i).uopIdx := i.U 1477 } 1478 } 1479 is(UopSplitType.VEC_US_LDST) { 1480 /* 1481 FMV.D.X 1482 */ 1483 csBundle(0).srcType(0) := SrcType.reg 1484 csBundle(0).srcType(1) := SrcType.imm 1485 csBundle(0).lsrc(1) := 0.U 1486 csBundle(0).ldest := FP_TMP_REG_MV.U 1487 csBundle(0).fuType := FuType.i2f.U 1488 csBundle(0).rfWen := false.B 1489 csBundle(0).fpWen := true.B 1490 csBundle(0).vecWen := false.B 1491 csBundle(0).fpu.isAddSub := false.B 1492 csBundle(0).fpu.typeTagIn := FPU.D 1493 csBundle(0).fpu.typeTagOut := FPU.D 1494 csBundle(0).fpu.fromInt := true.B 1495 csBundle(0).fpu.wflags := false.B 1496 csBundle(0).fpu.fpWen := true.B 1497 csBundle(0).fpu.div := false.B 1498 csBundle(0).fpu.sqrt := false.B 1499 csBundle(0).fpu.fcvt := false.B 1500 csBundle(0).vlsInstr := true.B 1501 //LMUL 1502 for (i <- 0 until MAX_VLMUL) { 1503 csBundle(i + 1).srcType(0) := SrcType.fp 1504 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1505 csBundle(i + 1).lsrc(2) := dest + i.U // old vd 1506 csBundle(i + 1).ldest := dest + i.U 1507 csBundle(i + 1).uopIdx := i.U 1508 csBundle(i + 1).vlsInstr := true.B 1509 } 1510 } 1511 is(UopSplitType.VEC_S_LDST) { 1512 /* 1513 FMV.D.X 1514 */ 1515 csBundle(0).srcType(0) := SrcType.reg 1516 csBundle(0).srcType(1) := SrcType.imm 1517 csBundle(0).lsrc(1) := 0.U 1518 csBundle(0).ldest := FP_TMP_REG_MV.U 1519 csBundle(0).fuType := FuType.i2f.U 1520 csBundle(0).rfWen := false.B 1521 csBundle(0).fpWen := true.B 1522 csBundle(0).vecWen := false.B 1523 csBundle(0).fpu.isAddSub := false.B 1524 csBundle(0).fpu.typeTagIn := FPU.D 1525 csBundle(0).fpu.typeTagOut := FPU.D 1526 csBundle(0).fpu.fromInt := true.B 1527 csBundle(0).fpu.wflags := false.B 1528 csBundle(0).fpu.fpWen := true.B 1529 csBundle(0).fpu.div := false.B 1530 csBundle(0).fpu.sqrt := false.B 1531 csBundle(0).fpu.fcvt := false.B 1532 csBundle(0).vlsInstr := true.B 1533 1534 csBundle(1).srcType(0) := SrcType.reg 1535 csBundle(1).srcType(1) := SrcType.imm 1536 csBundle(1).lsrc(0) := latchedInst.lsrc(1) 1537 csBundle(1).lsrc(1) := 0.U 1538 csBundle(1).ldest := VECTOR_TMP_REG_LMUL.U 1539 csBundle(1).fuType := FuType.i2f.U 1540 csBundle(1).rfWen := false.B 1541 csBundle(1).fpWen := true.B 1542 csBundle(1).vecWen := false.B 1543 csBundle(1).fpu.isAddSub := false.B 1544 csBundle(1).fpu.typeTagIn := FPU.D 1545 csBundle(1).fpu.typeTagOut := FPU.D 1546 csBundle(1).fpu.fromInt := true.B 1547 csBundle(1).fpu.wflags := false.B 1548 csBundle(1).fpu.fpWen := true.B 1549 csBundle(1).fpu.div := false.B 1550 csBundle(1).fpu.sqrt := false.B 1551 csBundle(1).fpu.fcvt := false.B 1552 csBundle(1).vlsInstr := true.B 1553 1554 //LMUL 1555 for (i <- 0 until MAX_VLMUL) { 1556 csBundle(i + 2).srcType(0) := SrcType.fp 1557 csBundle(i + 2).srcType(1) := SrcType.fp 1558 csBundle(i + 2).lsrc(0) := FP_TMP_REG_MV.U 1559 csBundle(i + 2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 1560 csBundle(i + 2).lsrc(2) := dest + i.U // old vd 1561 csBundle(i + 2).ldest := dest + i.U 1562 csBundle(i + 2).uopIdx := i.U 1563 csBundle(i + 2).vlsInstr := true.B 1564 } 1565 } 1566 is(UopSplitType.VEC_I_LDST) { 1567 /* 1568 FMV.D.X 1569 */ 1570 val vlmul = vlmulReg 1571 val vsew = Cat(0.U(1.W), vsewReg) 1572 val veew = Cat(0.U(1.W), width) 1573 val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 1574 val simple_lmul = MuxLookup(vlmul, 0.U(2.W), Array( 1575 "b001".U -> 1.U, 1576 "b010".U -> 2.U, 1577 "b011".U -> 3.U 1578 )) 1579 val simple_emul = MuxLookup(vemul, 0.U(2.W), Array( 1580 "b001".U -> 1.U, 1581 "b010".U -> 2.U, 1582 "b011".U -> 3.U 1583 )) 1584 csBundle(0).srcType(0) := SrcType.reg 1585 csBundle(0).srcType(1) := SrcType.imm 1586 csBundle(0).lsrc(1) := 0.U 1587 csBundle(0).ldest := FP_TMP_REG_MV.U 1588 csBundle(0).fuType := FuType.i2f.U 1589 csBundle(0).rfWen := false.B 1590 csBundle(0).fpWen := true.B 1591 csBundle(0).vecWen := false.B 1592 csBundle(0).fpu.isAddSub := false.B 1593 csBundle(0).fpu.typeTagIn := FPU.D 1594 csBundle(0).fpu.typeTagOut := FPU.D 1595 csBundle(0).fpu.fromInt := true.B 1596 csBundle(0).fpu.wflags := false.B 1597 csBundle(0).fpu.fpWen := true.B 1598 csBundle(0).fpu.div := false.B 1599 csBundle(0).fpu.sqrt := false.B 1600 csBundle(0).fpu.fcvt := false.B 1601 csBundle(0).vlsInstr := true.B 1602 1603 //LMUL 1604 for (i <- 0 until MAX_INDEXED_LS_UOPNUM) { 1605 indexedLSRegOffset(i).src := Cat(simple_emul, simple_lmul, nf) 1606 val offsetVs2 = indexedLSRegOffset(i).outOffsetVs2 1607 val offsetVd = indexedLSRegOffset(i).outOffsetVd 1608 val isFirstUopInVd = indexedLSRegOffset(i).outIsFirstUopInVd 1609 csBundle(i + 1).srcType(0) := SrcType.fp 1610 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1611 csBundle(i + 1).lsrc(1) := Mux1H(UIntToOH(offsetVs2, MAX_VLMUL), (0 until MAX_VLMUL).map(j => src2 + j.U)) 1612 /** 1613 * For indexed instructions, VLSU will concatenate all the uops that write the same logic vd register and 1614 * writeback only once for all these uops. However, these uops share the same lsrc(2)/old vd and the same 1615 * ldest/vd that is equal to old vd, which leads to data dependence between the uops. Therefore there will be 1616 * deadlock for indexed instructions with emul > lmul. 1617 * 1618 * Assume N = emul/lmul. To break the deadlock, only the first uop will read old vd as lsrc(2), and the rest 1619 * N-1 uops will read temporary vector register. 1620 */ 1621 // csBundle(i + 1).lsrc(2) := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1622 csBundle(i + 1).lsrc(2) := Mux( 1623 isFirstUopInVd, 1624 Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)), 1625 VECTOR_TMP_REG_LMUL.U 1626 ) 1627 csBundle(i + 1).ldest := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1628 csBundle(i + 1).uopIdx := i.U 1629 csBundle(i + 1).vlsInstr := true.B 1630 } 1631 } 1632 } 1633 1634 //readyFromRename Counter 1635 val readyCounter = PriorityMuxDefault(outReadys.map(x => !x).zip((0 until RenameWidth).map(_.U)), RenameWidth.U) 1636 1637 // The left uops of the complex inst in ComplexDecoder can be send out this cycle 1638 val thisAllOut = uopRes <= readyCounter 1639 1640 switch(state) { 1641 is(s_idle) { 1642 when (inValid) { 1643 stateNext := s_active 1644 uopResNext := inUopInfo.numOfUop 1645 } 1646 } 1647 is(s_active) { 1648 when (thisAllOut) { 1649 when (inValid) { 1650 stateNext := s_active 1651 uopResNext := inUopInfo.numOfUop 1652 }.otherwise { 1653 stateNext := s_idle 1654 uopResNext := 0.U 1655 } 1656 }.otherwise { 1657 stateNext := s_active 1658 uopResNext := uopRes - readyCounter 1659 } 1660 } 1661 } 1662 1663 state := Mux(io.redirect, s_idle, stateNext) 1664 uopRes := Mux(io.redirect, 0.U, uopResNext) 1665 1666 val complexNum = Mux(uopRes > readyCounter, readyCounter, uopRes) 1667 1668 for(i <- 0 until RenameWidth) { 1669 outValids(i) := complexNum > i.U 1670 outDecodedInsts(i) := Mux((i.U + numOfUop - uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1671 } 1672 1673 outComplexNum := Mux(state === s_active, complexNum, 0.U) 1674 inReady := state === s_idle || state === s_active && thisAllOut 1675 1676// val validSimple = Wire(Vec(DecodeWidth, Bool())) 1677// validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1678// val notInf = Wire(Vec(DecodeWidth, Bool())) 1679// notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1680// notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 1681// val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1682// notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1683// 1684// complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1685// Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1686// 0.U) 1687// validToRename.zipWithIndex.foreach{ 1688// case(dst, i) => 1689// val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 1690// dst := MuxCase(false.B, Seq( 1691// (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 1692// (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1693// ).toSeq) 1694// } 1695// 1696// readyToIBuf.zipWithIndex.foreach { 1697// case (dst, i) => 1698// val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 1699// dst := MuxCase(true.B, Seq( 1700// (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 1701// (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 1702// ).toSeq) 1703// } 1704// 1705// io.deq.decodedInsts := decodedInsts 1706// io.deq.complexNum := complexNum 1707// io.deq.validToRename := validToRename 1708// io.deq.readyToIBuf := readyToIBuf 1709} 1710