1/*************************************************************************************** 2 * Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3 * Copyright (c) 2020-2021 Peng Cheng Laboratory 4 * 5 * XiangShan is licensed under Mulan PSL v2. 6 * You can use this software according to the terms and conditions of the Mulan PSL v2. 7 * You may obtain a copy of Mulan PSL v2 at: 8 * http://license.coscl.org.cn/MulanPSL2 9 * 10 * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11 * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12 * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13 * 14 * See the Mulan PSL v2 for more details. 15 ***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions 23import freechips.rocketchip.util.uintToBitPat 24import utils._ 25import utility._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.fpu.FPU 29import xiangshan.backend.fu.FuType 30import freechips.rocketchip.rocket.Instructions._ 31import xiangshan.backend.Bundles.{DecodedInst, StaticInst} 32import xiangshan.backend.decode.isa.bitfield.XSInstBitFields 33import xiangshan.backend.fu.vector.Bundles.VType 34import yunsuan.VpermType 35 36import scala.collection.Seq 37 38trait VectorConstants { 39 val MAX_VLMUL = 8 40 val FP_TMP_REG_MV = 32 41 val VECTOR_TMP_REG_LMUL = 33 // 33~47 -> 15 42} 43 44class DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 45 val enq = new Bundle { val staticInst = Input(new StaticInst) } 46 val vtype = Input(new VType) 47 val isComplex = Input(Vec(DecodeWidth - 1, Bool())) 48 val validFromIBuf = Input(Vec(DecodeWidth, Bool())) 49 val readyFromRename = Input(Vec(RenameWidth, Bool())) 50 val deq = new Bundle { 51 val decodedInsts = Output(Vec(RenameWidth, new DecodedInst)) 52 val isVset = Output(Bool()) 53 val readyToIBuf = Output(Vec(DecodeWidth, Bool())) 54 val validToRename = Output(Vec(RenameWidth, Bool())) 55 val complexNum = Output(UInt(3.W)) 56 } 57 val csrCtrl = Input(new CustomCSRCtrlIO) 58} 59 60/** 61 * @author zly 62 */ 63class DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 64 val io = IO(new DecodeUnitCompIO) 65 66 val maxUopSize = MaxUopSize 67 //input bits 68 val staticInst = Wire(new StaticInst) 69 70 71 staticInst := io.enq.staticInst 72 private val inst: XSInstBitFields = staticInst.instr.asTypeOf(new XSInstBitFields) 73 74 val src1 = Cat(0.U(1.W), inst.RS1) 75 val src2 = Cat(0.U(1.W), inst.RS2) 76 val dest = Cat(0.U(1.W), inst.RD) 77 78 79 //output bits 80 val decodedInsts = Wire(Vec(RenameWidth, new DecodedInst)) 81 val validToRename = Wire(Vec(RenameWidth, Bool())) 82 val readyToIBuf = Wire(Vec(DecodeWidth, Bool())) 83 val complexNum = Wire(UInt(3.W)) 84 85 //output of DecodeUnit 86 val decodedInstsSimple = Wire(new DecodedInst) 87 val numOfUop = Wire(UInt(log2Up(maxUopSize+1).W)) 88 val lmul = Wire(UInt(4.W)) 89 val isVsetSimple = Wire(Bool()) 90 91 //pre decode 92 val simple = Module(new DecodeUnit) 93 simple.io.enq.ctrlFlow := staticInst 94 simple.io.enq.vtype := io.vtype 95 simple.io.csrCtrl := io.csrCtrl 96 decodedInstsSimple := simple.io.deq.decodedInst 97 lmul := simple.io.deq.uopInfo.lmul 98 isVsetSimple := simple.io.deq.decodedInst.isVset 99 when(isVsetSimple) { 100 when(dest === 0.U && src1 === 0.U) { 101 decodedInstsSimple.fuOpType := VSETOpType.keepVl(simple.io.deq.decodedInst.fuOpType) 102 }.elsewhen(src1 === 0.U) { 103 decodedInstsSimple.fuOpType := VSETOpType.setVlmax(simple.io.deq.decodedInst.fuOpType) 104 } 105 when(io.vtype.illegal){ 106 decodedInstsSimple.flushPipe := true.B 107 } 108 } 109 //Type of uop Div 110 val typeOfSplit = decodedInstsSimple.uopSplitType 111 112 when(typeOfSplit === UopSplitType.DIR) { 113 numOfUop := Mux(dest =/= 0.U, 2.U, 114 Mux(src1 =/= 0.U, 1.U, 115 Mux(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType), 2.U, 1.U))) 116 } .otherwise { 117 numOfUop := simple.io.deq.uopInfo.numOfUop 118 } 119 120 121 //uop div up to maxUopSize 122 val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 123 csBundle.map { case dst => 124 dst := decodedInstsSimple 125 dst.firstUop := false.B 126 dst.lastUop := false.B 127 } 128 129 csBundle(0).numUops := numOfUop 130 csBundle(0).firstUop := true.B 131 csBundle(numOfUop - 1.U).lastUop := true.B 132 133 switch(typeOfSplit) { 134 is(UopSplitType.DIR) { 135 when(isVsetSimple) { 136 when(dest =/= 0.U) { 137 csBundle(0).fuType := FuType.vsetiwi.U 138 csBundle(0).fuOpType := VSETOpType.switchDest(decodedInstsSimple.fuOpType) 139 csBundle(0).flushPipe := false.B 140 csBundle(0).rfWen := true.B 141 csBundle(0).vecWen := false.B 142 csBundle(1).ldest := VCONFIG_IDX.U 143 csBundle(1).rfWen := false.B 144 csBundle(1).vecWen := true.B 145 }.elsewhen(src1 =/= 0.U) { 146 csBundle(0).ldest := VCONFIG_IDX.U 147 }.elsewhen(VSETOpType.isVsetvli(decodedInstsSimple.fuOpType)) { 148 csBundle(0).fuType := FuType.vsetfwf.U 149 csBundle(0).srcType(0) := SrcType.vp 150 csBundle(0).lsrc(0) := VCONFIG_IDX.U 151 }.elsewhen(VSETOpType.isVsetvl(decodedInstsSimple.fuOpType)) { 152 csBundle(0).srcType(0) := SrcType.reg 153 csBundle(0).srcType(1) := SrcType.imm 154 csBundle(0).lsrc(1) := 0.U 155 csBundle(0).ldest := FP_TMP_REG_MV.U 156 csBundle(0).fuType := FuType.i2f.U 157 csBundle(0).rfWen := false.B 158 csBundle(0).fpWen := true.B 159 csBundle(0).vecWen := false.B 160 csBundle(0).fpu.isAddSub := false.B 161 csBundle(0).fpu.typeTagIn := FPU.D 162 csBundle(0).fpu.typeTagOut := FPU.D 163 csBundle(0).fpu.fromInt := true.B 164 csBundle(0).fpu.wflags := false.B 165 csBundle(0).fpu.fpWen := true.B 166 csBundle(0).fpu.div := false.B 167 csBundle(0).fpu.sqrt := false.B 168 csBundle(0).fpu.fcvt := false.B 169 csBundle(0).flushPipe := false.B 170 csBundle(1).fuType := FuType.vsetfwf.U 171 csBundle(1).srcType(0) := SrcType.vp 172 csBundle(1).lsrc(0) := VCONFIG_IDX.U 173 csBundle(1).srcType(1) := SrcType.fp 174 csBundle(1).lsrc(1) := FP_TMP_REG_MV.U 175 csBundle(1).ldest := VCONFIG_IDX.U 176 } 177 } 178 } 179 is(UopSplitType.VEC_VVV) { 180 for (i <- 0 until MAX_VLMUL) { 181 csBundle(i).lsrc(0) := src1 + i.U 182 csBundle(i).lsrc(1) := src2 + i.U 183 csBundle(i).lsrc(2) := dest + i.U 184 csBundle(i).ldest := dest + i.U 185 csBundle(i).uopIdx := i.U 186 } 187 } 188 is(UopSplitType.VEC_VFV) { 189 for (i <- 0 until MAX_VLMUL) { 190 csBundle(i).lsrc(1) := src2 + i.U 191 csBundle(i).lsrc(2) := dest + i.U 192 csBundle(i).ldest := dest + i.U 193 csBundle(i).uopIdx := i.U 194 } 195 } 196 is(UopSplitType.VEC_EXT2) { 197 for (i <- 0 until MAX_VLMUL / 2) { 198 csBundle(2 * i).lsrc(1) := src2 + i.U 199 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 200 csBundle(2 * i).ldest := dest + (2 * i).U 201 csBundle(2 * i).uopIdx := (2 * i).U 202 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 203 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 204 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 205 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 206 } 207 } 208 is(UopSplitType.VEC_EXT4) { 209 for (i <- 0 until MAX_VLMUL / 4) { 210 csBundle(4 * i).lsrc(1) := src2 + i.U 211 csBundle(4 * i).lsrc(2) := dest + (4 * i).U 212 csBundle(4 * i).ldest := dest + (4 * i).U 213 csBundle(4 * i).uopIdx := (4 * i).U 214 csBundle(4 * i + 1).lsrc(1) := src2 + i.U 215 csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 216 csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 217 csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 218 csBundle(4 * i + 2).lsrc(1) := src2 + i.U 219 csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 220 csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 221 csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 222 csBundle(4 * i + 3).lsrc(1) := src2 + i.U 223 csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 224 csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 225 csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 226 } 227 } 228 is(UopSplitType.VEC_EXT8) { 229 for (i <- 0 until MAX_VLMUL) { 230 csBundle(i).lsrc(1) := src2 231 csBundle(i).lsrc(2) := dest + i.U 232 csBundle(i).ldest := dest + i.U 233 csBundle(i).uopIdx := i.U 234 } 235 } 236 is(UopSplitType.VEC_0XV) { 237 /* 238 FMV.D.X 239 */ 240 csBundle(0).srcType(0) := SrcType.reg 241 csBundle(0).srcType(1) := SrcType.imm 242 csBundle(0).lsrc(1) := 0.U 243 csBundle(0).ldest := FP_TMP_REG_MV.U 244 csBundle(0).fuType := FuType.i2f.U 245 csBundle(0).rfWen := false.B 246 csBundle(0).fpWen := true.B 247 csBundle(0).vecWen := false.B 248 csBundle(0).fpu.isAddSub := false.B 249 csBundle(0).fpu.typeTagIn := FPU.D 250 csBundle(0).fpu.typeTagOut := FPU.D 251 csBundle(0).fpu.fromInt := true.B 252 csBundle(0).fpu.wflags := false.B 253 csBundle(0).fpu.fpWen := true.B 254 csBundle(0).fpu.div := false.B 255 csBundle(0).fpu.sqrt := false.B 256 csBundle(0).fpu.fcvt := false.B 257 /* 258 vfmv.s.f 259 */ 260 csBundle(1).srcType(0) := SrcType.fp 261 csBundle(1).srcType(1) := SrcType.vp 262 csBundle(1).srcType(2) := SrcType.vp 263 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 264 csBundle(1).lsrc(1) := 0.U 265 csBundle(1).lsrc(2) := dest 266 csBundle(1).ldest := dest 267 csBundle(1).fuType := FuType.vppu.U 268 csBundle(1).fuOpType := VpermType.dummy 269 csBundle(1).rfWen := false.B 270 csBundle(1).fpWen := false.B 271 csBundle(1).vecWen := true.B 272 } 273 is(UopSplitType.VEC_VXV) { 274 /* 275 FMV.D.X 276 */ 277 csBundle(0).srcType(0) := SrcType.reg 278 csBundle(0).srcType(1) := SrcType.imm 279 csBundle(0).lsrc(1) := 0.U 280 csBundle(0).ldest := FP_TMP_REG_MV.U 281 csBundle(0).fuType := FuType.i2f.U 282 csBundle(0).rfWen := false.B 283 csBundle(0).fpWen := true.B 284 csBundle(0).vecWen := false.B 285 csBundle(0).fpu.isAddSub := false.B 286 csBundle(0).fpu.typeTagIn := FPU.D 287 csBundle(0).fpu.typeTagOut := FPU.D 288 csBundle(0).fpu.fromInt := true.B 289 csBundle(0).fpu.wflags := false.B 290 csBundle(0).fpu.fpWen := true.B 291 csBundle(0).fpu.div := false.B 292 csBundle(0).fpu.sqrt := false.B 293 csBundle(0).fpu.fcvt := false.B 294 /* 295 LMUL 296 */ 297 for (i <- 0 until MAX_VLMUL) { 298 csBundle(i + 1).srcType(0) := SrcType.fp 299 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 300 csBundle(i + 1).lsrc(1) := src2 + i.U 301 csBundle(i + 1).lsrc(2) := dest + i.U 302 csBundle(i + 1).ldest := dest + i.U 303 csBundle(i + 1).uopIdx := i.U 304 } 305 } 306 is(UopSplitType.VEC_VVW) { 307 for (i <- 0 until MAX_VLMUL / 2) { 308 csBundle(2 * i).lsrc(0) := src1 + i.U 309 csBundle(2 * i).lsrc(1) := src2 + i.U 310 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 311 csBundle(2 * i).ldest := dest + (2 * i).U 312 csBundle(2 * i).uopIdx := (2 * i).U 313 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 314 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 315 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 316 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 317 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 318 } 319 } 320 is(UopSplitType.VEC_VFW) { 321 for (i <- 0 until MAX_VLMUL / 2) { 322 csBundle(2 * i).lsrc(0) := src1 323 csBundle(2 * i).lsrc(1) := src2 + i.U 324 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 325 csBundle(2 * i).ldest := dest + (2 * i).U 326 csBundle(2 * i).uopIdx := (2 * i).U 327 csBundle(2 * i + 1).lsrc(0) := src1 328 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 329 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 330 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 331 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 332 } 333 } 334 is(UopSplitType.VEC_WVW) { 335 for (i <- 0 until MAX_VLMUL / 2) { 336 csBundle(2 * i).lsrc(0) := src1 + i.U 337 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 338 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 339 csBundle(2 * i).ldest := dest + (2 * i).U 340 csBundle(2 * i).uopIdx := (2 * i).U 341 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 342 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 343 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 344 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 345 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 346 } 347 } 348 is(UopSplitType.VEC_VXW) { 349 /* 350 FMV.D.X 351 */ 352 csBundle(0).srcType(0) := SrcType.reg 353 csBundle(0).srcType(1) := SrcType.imm 354 csBundle(0).lsrc(1) := 0.U 355 csBundle(0).ldest := FP_TMP_REG_MV.U 356 csBundle(0).fuType := FuType.i2f.U 357 csBundle(0).rfWen := false.B 358 csBundle(0).fpWen := true.B 359 csBundle(0).vecWen := false.B 360 csBundle(0).fpu.isAddSub := false.B 361 csBundle(0).fpu.typeTagIn := FPU.D 362 csBundle(0).fpu.typeTagOut := FPU.D 363 csBundle(0).fpu.fromInt := true.B 364 csBundle(0).fpu.wflags := false.B 365 csBundle(0).fpu.fpWen := true.B 366 csBundle(0).fpu.div := false.B 367 csBundle(0).fpu.sqrt := false.B 368 csBundle(0).fpu.fcvt := false.B 369 370 for (i <- 0 until MAX_VLMUL / 2) { 371 csBundle(2 * i + 1).srcType(0) := SrcType.fp 372 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 373 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 374 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 375 csBundle(2 * i + 1).ldest := dest + (2 * i).U 376 csBundle(2 * i + 1).uopIdx := (2 * i).U 377 csBundle(2 * i + 2).srcType(0) := SrcType.fp 378 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 379 csBundle(2 * i + 2).lsrc(1) := src2 + i.U 380 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 381 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 382 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 383 } 384 } 385 is(UopSplitType.VEC_WXW) { 386 /* 387 FMV.D.X 388 */ 389 csBundle(0).srcType(0) := SrcType.reg 390 csBundle(0).srcType(1) := SrcType.imm 391 csBundle(0).lsrc(1) := 0.U 392 csBundle(0).ldest := FP_TMP_REG_MV.U 393 csBundle(0).fuType := FuType.i2f.U 394 csBundle(0).rfWen := false.B 395 csBundle(0).fpWen := true.B 396 csBundle(0).vecWen := false.B 397 csBundle(0).fpu.isAddSub := false.B 398 csBundle(0).fpu.typeTagIn := FPU.D 399 csBundle(0).fpu.typeTagOut := FPU.D 400 csBundle(0).fpu.fromInt := true.B 401 csBundle(0).fpu.wflags := false.B 402 csBundle(0).fpu.fpWen := true.B 403 csBundle(0).fpu.div := false.B 404 csBundle(0).fpu.sqrt := false.B 405 csBundle(0).fpu.fcvt := false.B 406 407 for (i <- 0 until MAX_VLMUL / 2) { 408 csBundle(2 * i + 1).srcType(0) := SrcType.fp 409 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 410 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 411 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 412 csBundle(2 * i + 1).ldest := dest + (2 * i).U 413 csBundle(2 * i + 1).uopIdx := (2 * i).U 414 csBundle(2 * i + 2).srcType(0) := SrcType.fp 415 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 416 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 417 csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 418 csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 419 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 420 } 421 } 422 is(UopSplitType.VEC_WVV) { 423 for (i <- 0 until MAX_VLMUL / 2) { 424 425 csBundle(2 * i).lsrc(0) := src1 + i.U 426 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 427 csBundle(2 * i).lsrc(2) := dest + i.U 428 csBundle(2 * i).ldest := dest + i.U 429 csBundle(2 * i).uopIdx := (2 * i).U 430 csBundle(2 * i + 1).lsrc(0) := src1 + i.U 431 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 432 csBundle(2 * i + 1).lsrc(2) := dest + i.U 433 csBundle(2 * i + 1).ldest := dest + i.U 434 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 435 } 436 } 437 is(UopSplitType.VEC_WFW) { 438 for (i <- 0 until MAX_VLMUL / 2) { 439 csBundle(2 * i).lsrc(0) := src1 440 csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 441 csBundle(2 * i).lsrc(2) := dest + (2 * i).U 442 csBundle(2 * i).ldest := dest + (2 * i).U 443 csBundle(2 * i).uopIdx := (2 * i).U 444 csBundle(2 * i + 1).lsrc(0) := src1 445 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 446 csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 447 csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 448 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 449 } 450 } 451 is(UopSplitType.VEC_WXV) { 452 /* 453 FMV.D.X 454 */ 455 csBundle(0).srcType(0) := SrcType.reg 456 csBundle(0).srcType(1) := SrcType.imm 457 csBundle(0).lsrc(1) := 0.U 458 csBundle(0).ldest := FP_TMP_REG_MV.U 459 csBundle(0).fuType := FuType.i2f.U 460 csBundle(0).rfWen := false.B 461 csBundle(0).fpWen := true.B 462 csBundle(0).vecWen := false.B 463 csBundle(0).fpu.isAddSub := false.B 464 csBundle(0).fpu.typeTagIn := FPU.D 465 csBundle(0).fpu.typeTagOut := FPU.D 466 csBundle(0).fpu.fromInt := true.B 467 csBundle(0).fpu.wflags := false.B 468 csBundle(0).fpu.fpWen := true.B 469 csBundle(0).fpu.div := false.B 470 csBundle(0).fpu.sqrt := false.B 471 csBundle(0).fpu.fcvt := false.B 472 473 for (i <- 0 until MAX_VLMUL / 2) { 474 csBundle(2 * i + 1).srcType(0) := SrcType.fp 475 csBundle(2 * i + 1).lsrc(0) := FP_TMP_REG_MV.U 476 csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 477 csBundle(2 * i + 1).lsrc(2) := dest + i.U 478 csBundle(2 * i + 1).ldest := dest + i.U 479 csBundle(2 * i + 1).uopIdx := (2 * i).U 480 csBundle(2 * i + 2).srcType(0) := SrcType.fp 481 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 482 csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 483 csBundle(2 * i + 2).lsrc(2) := dest + i.U 484 csBundle(2 * i + 2).ldest := dest + i.U 485 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 486 } 487 } 488 is(UopSplitType.VEC_VVM) { 489 csBundle(0).lsrc(2) := dest 490 csBundle(0).ldest := dest 491 csBundle(0).uopIdx := 0.U 492 for (i <- 1 until MAX_VLMUL) { 493 csBundle(i).lsrc(0) := src1 + i.U 494 csBundle(i).lsrc(1) := src2 + i.U 495 csBundle(i).lsrc(2) := dest 496 csBundle(i).ldest := dest 497 csBundle(i).uopIdx := i.U 498 } 499 csBundle(numOfUop - 1.U).ldest := dest 500 } 501 is(UopSplitType.VEC_VFM) { 502 csBundle(0).lsrc(2) := dest 503 csBundle(0).ldest := dest 504 csBundle(0).uopIdx := 0.U 505 for (i <- 1 until MAX_VLMUL) { 506 csBundle(i).lsrc(0) := src1 507 csBundle(i).lsrc(1) := src2 + i.U 508 csBundle(i).lsrc(2) := dest 509 csBundle(i).ldest := dest 510 csBundle(i).uopIdx := i.U 511 } 512 csBundle(numOfUop - 1.U).ldest := dest 513 } 514 is(UopSplitType.VEC_VXM) { 515 /* 516 FMV.D.X 517 */ 518 csBundle(0).srcType(0) := SrcType.reg 519 csBundle(0).srcType(1) := SrcType.imm 520 csBundle(0).lsrc(1) := 0.U 521 csBundle(0).ldest := FP_TMP_REG_MV.U 522 csBundle(0).fuType := FuType.i2f.U 523 csBundle(0).rfWen := false.B 524 csBundle(0).fpWen := true.B 525 csBundle(0).vecWen := false.B 526 csBundle(0).fpu.isAddSub := false.B 527 csBundle(0).fpu.typeTagIn := FPU.D 528 csBundle(0).fpu.typeTagOut := FPU.D 529 csBundle(0).fpu.fromInt := true.B 530 csBundle(0).fpu.wflags := false.B 531 csBundle(0).fpu.fpWen := true.B 532 csBundle(0).fpu.div := false.B 533 csBundle(0).fpu.sqrt := false.B 534 csBundle(0).fpu.fcvt := false.B 535 //LMUL 536 csBundle(1).srcType(0) := SrcType.fp 537 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 538 csBundle(1).lsrc(2) := dest 539 csBundle(1).ldest := dest 540 csBundle(1).uopIdx := 0.U 541 for (i <- 1 until MAX_VLMUL) { 542 csBundle(i + 1).srcType(0) := SrcType.fp 543 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 544 csBundle(i + 1).lsrc(1) := src2 + i.U 545 csBundle(i + 1).lsrc(2) := dest 546 csBundle(i + 1).ldest := dest 547 csBundle(i + 1).uopIdx := i.U 548 } 549 csBundle(numOfUop - 1.U).ldest := dest 550 } 551 is(UopSplitType.VEC_SLIDE1UP) { 552 /* 553 FMV.D.X 554 */ 555 csBundle(0).srcType(0) := SrcType.reg 556 csBundle(0).srcType(1) := SrcType.imm 557 csBundle(0).lsrc(1) := 0.U 558 csBundle(0).ldest := FP_TMP_REG_MV.U 559 csBundle(0).fuType := FuType.i2f.U 560 csBundle(0).rfWen := false.B 561 csBundle(0).fpWen := true.B 562 csBundle(0).vecWen := false.B 563 csBundle(0).fpu.isAddSub := false.B 564 csBundle(0).fpu.typeTagIn := FPU.D 565 csBundle(0).fpu.typeTagOut := FPU.D 566 csBundle(0).fpu.fromInt := true.B 567 csBundle(0).fpu.wflags := false.B 568 csBundle(0).fpu.fpWen := true.B 569 csBundle(0).fpu.div := false.B 570 csBundle(0).fpu.sqrt := false.B 571 csBundle(0).fpu.fcvt := false.B 572 //LMUL 573 csBundle(1).srcType(0) := SrcType.fp 574 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 575 csBundle(1).lsrc(2) := dest 576 csBundle(1).ldest := dest 577 csBundle(1).uopIdx := 0.U 578 for (i <- 1 until MAX_VLMUL) { 579 csBundle(i + 1).srcType(0) := SrcType.vp 580 csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 581 csBundle(i + 1).lsrc(1) := src2 + i.U 582 csBundle(i + 1).lsrc(2) := dest + i.U 583 csBundle(i + 1).ldest := dest + i.U 584 csBundle(i + 1).uopIdx := i.U 585 } 586 } 587 is(UopSplitType.VEC_FSLIDE1UP) { 588 //LMUL 589 csBundle(0).srcType(0) := SrcType.fp 590 csBundle(0).lsrc(0) := src1 591 csBundle(0).lsrc(1) := src2 592 csBundle(0).lsrc(2) := dest 593 csBundle(0).ldest := dest 594 csBundle(0).uopIdx := 0.U 595 for (i <- 1 until MAX_VLMUL) { 596 csBundle(i).srcType(0) := SrcType.vp 597 csBundle(i).lsrc(0) := src2 + (i - 1).U 598 csBundle(i).lsrc(1) := src2 + i.U 599 csBundle(i).lsrc(2) := dest + i.U 600 csBundle(i).ldest := dest + i.U 601 csBundle(i).uopIdx := i.U 602 } 603 } 604 is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 605 /* 606 FMV.D.X 607 */ 608 csBundle(0).srcType(0) := SrcType.reg 609 csBundle(0).srcType(1) := SrcType.imm 610 csBundle(0).lsrc(1) := 0.U 611 csBundle(0).ldest := FP_TMP_REG_MV.U 612 csBundle(0).fuType := FuType.i2f.U 613 csBundle(0).rfWen := false.B 614 csBundle(0).fpWen := true.B 615 csBundle(0).vecWen := false.B 616 csBundle(0).fpu.isAddSub := false.B 617 csBundle(0).fpu.typeTagIn := FPU.D 618 csBundle(0).fpu.typeTagOut := FPU.D 619 csBundle(0).fpu.fromInt := true.B 620 csBundle(0).fpu.wflags := false.B 621 csBundle(0).fpu.fpWen := true.B 622 csBundle(0).fpu.div := false.B 623 csBundle(0).fpu.sqrt := false.B 624 csBundle(0).fpu.fcvt := false.B 625 //LMUL 626 for (i <- 0 until MAX_VLMUL) { 627 csBundle(2 * i + 1).srcType(0) := SrcType.vp 628 csBundle(2 * i + 1).srcType(1) := SrcType.vp 629 csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 630 csBundle(2 * i + 1).lsrc(1) := src2 + i.U 631 csBundle(2 * i + 1).lsrc(2) := dest + i.U 632 csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U 633 csBundle(2 * i + 1).uopIdx := (2 * i).U 634 if (2 * i + 2 < MAX_VLMUL * 2) { 635 csBundle(2 * i + 2).srcType(0) := SrcType.fp 636 csBundle(2 * i + 2).lsrc(0) := FP_TMP_REG_MV.U 637 // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 638 csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U 639 csBundle(2 * i + 2).ldest := dest + i.U 640 csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 641 } 642 } 643 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 644 csBundle(numOfUop - 1.U).lsrc(0) := FP_TMP_REG_MV.U 645 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 646 } 647 is(UopSplitType.VEC_FSLIDE1DOWN) { 648 //LMUL 649 for (i <- 0 until MAX_VLMUL) { 650 csBundle(2 * i).srcType(0) := SrcType.vp 651 csBundle(2 * i).srcType(1) := SrcType.vp 652 csBundle(2 * i).lsrc(0) := src2 + (i + 1).U 653 csBundle(2 * i).lsrc(1) := src2 + i.U 654 csBundle(2 * i).lsrc(2) := dest + i.U 655 csBundle(2 * i).ldest := VECTOR_TMP_REG_LMUL.U 656 csBundle(2 * i).uopIdx := (2 * i).U 657 csBundle(2 * i + 1).srcType(0) := SrcType.fp 658 csBundle(2 * i + 1).lsrc(0) := src1 659 csBundle(2 * i + 1).lsrc(2) := VECTOR_TMP_REG_LMUL.U 660 csBundle(2 * i + 1).ldest := dest + i.U 661 csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 662 } 663 csBundle(numOfUop - 1.U).srcType(0) := SrcType.fp 664 csBundle(numOfUop - 1.U).lsrc(0) := src1 665 csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 666 } 667 is(UopSplitType.VEC_VRED) { 668 when(simple.io.enq.vtype.vlmul === "b001".U) { 669 csBundle(0).srcType(2) := SrcType.DC 670 csBundle(0).lsrc(0) := src2 + 1.U 671 csBundle(0).lsrc(1) := src2 672 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 673 csBundle(0).uopIdx := 0.U 674 } 675 when(simple.io.enq.vtype.vlmul === "b010".U) { 676 csBundle(0).srcType(2) := SrcType.DC 677 csBundle(0).lsrc(0) := src2 + 1.U 678 csBundle(0).lsrc(1) := src2 679 csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 680 csBundle(0).uopIdx := 0.U 681 682 csBundle(1).srcType(2) := SrcType.DC 683 csBundle(1).lsrc(0) := src2 + 3.U 684 csBundle(1).lsrc(1) := src2 + 2.U 685 csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 686 csBundle(1).uopIdx := 1.U 687 688 csBundle(2).srcType(2) := SrcType.DC 689 csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 690 csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 691 csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 692 csBundle(2).uopIdx := 2.U 693 } 694 when(simple.io.enq.vtype.vlmul === "b011".U) { 695 for (i <- 0 until MAX_VLMUL) { 696 if (i < MAX_VLMUL - MAX_VLMUL / 2) { 697 csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 698 csBundle(i).lsrc(1) := src2 + (i * 2).U 699 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 700 } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 701 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 702 csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 703 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 704 } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 705 csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 706 csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 707 csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 708 } 709 csBundle(i).srcType(2) := SrcType.DC 710 csBundle(i).uopIdx := i.U 711 } 712 } 713 when(simple.io.enq.vtype.vlmul.orR()) { 714 csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 715 csBundle(numOfUop - 1.U).lsrc(0) := src1 716 csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 717 csBundle(numOfUop - 1.U).lsrc(2) := dest 718 csBundle(numOfUop - 1.U).ldest := dest 719 csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 720 } 721 } 722 723 is(UopSplitType.VEC_SLIDEUP) { 724 // FMV.D.X 725 csBundle(0).srcType(0) := SrcType.reg 726 csBundle(0).srcType(1) := SrcType.imm 727 csBundle(0).lsrc(1) := 0.U 728 csBundle(0).ldest := FP_TMP_REG_MV.U 729 csBundle(0).fuType := FuType.i2f.U 730 csBundle(0).rfWen := false.B 731 csBundle(0).fpWen := true.B 732 csBundle(0).vecWen := false.B 733 csBundle(0).fpu.isAddSub := false.B 734 csBundle(0).fpu.typeTagIn := FPU.D 735 csBundle(0).fpu.typeTagOut := FPU.D 736 csBundle(0).fpu.fromInt := true.B 737 csBundle(0).fpu.wflags := false.B 738 csBundle(0).fpu.fpWen := true.B 739 csBundle(0).fpu.div := false.B 740 csBundle(0).fpu.sqrt := false.B 741 csBundle(0).fpu.fcvt := false.B 742 // LMUL 743 for (i <- 0 until MAX_VLMUL) 744 for (j <- 0 to i) { 745 val old_vd = if (j == 0) { 746 dest + i.U 747 } else (VECTOR_TMP_REG_LMUL + j - 1).U 748 val vd = if (j == i) { 749 dest + i.U 750 } else (VECTOR_TMP_REG_LMUL + j).U 751 csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.fp 752 csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := FP_TMP_REG_MV.U 753 csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 754 csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 755 csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 756 csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 757 } 758 } 759 760 is(UopSplitType.VEC_ISLIDEUP) { 761 // LMUL 762 for (i <- 0 until MAX_VLMUL) 763 for (j <- 0 to i) { 764 val old_vd = if (j == 0) { 765 dest + i.U 766 } else (VECTOR_TMP_REG_LMUL + j - 1).U 767 val vd = if (j == i) { 768 dest + i.U 769 } else (VECTOR_TMP_REG_LMUL + j).U 770 csBundle(i * (i + 1) / 2 + j).lsrc(1) := src2 + j.U 771 csBundle(i * (i + 1) / 2 + j).lsrc(2) := old_vd 772 csBundle(i * (i + 1) / 2 + j).ldest := vd 773 csBundle(i * (i + 1) / 2 + j).uopIdx := (i * (i + 1) / 2 + j).U 774 } 775 } 776 777 is(UopSplitType.VEC_SLIDEDOWN) { 778 // FMV.D.X 779 csBundle(0).srcType(0) := SrcType.reg 780 csBundle(0).srcType(1) := SrcType.imm 781 csBundle(0).lsrc(1) := 0.U 782 csBundle(0).ldest := FP_TMP_REG_MV.U 783 csBundle(0).fuType := FuType.i2f.U 784 csBundle(0).rfWen := false.B 785 csBundle(0).fpWen := true.B 786 csBundle(0).vecWen := false.B 787 csBundle(0).fpu.isAddSub := false.B 788 csBundle(0).fpu.typeTagIn := FPU.D 789 csBundle(0).fpu.typeTagOut := FPU.D 790 csBundle(0).fpu.fromInt := true.B 791 csBundle(0).fpu.wflags := false.B 792 csBundle(0).fpu.fpWen := true.B 793 csBundle(0).fpu.div := false.B 794 csBundle(0).fpu.sqrt := false.B 795 csBundle(0).fpu.fcvt := false.B 796 // LMUL 797 for (i <- 0 until MAX_VLMUL) 798 for (j <- (0 to i).reverse) { 799 when(i.U < lmul) { 800 val old_vd = if (j == 0) { 801 dest + lmul - 1.U - i.U 802 } else (VECTOR_TMP_REG_LMUL + j - 1).U 803 val vd = if (j == i) { 804 dest + lmul - 1.U - i.U 805 } else (VECTOR_TMP_REG_LMUL + j).U 806 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.fp 807 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := FP_TMP_REG_MV.U 808 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 809 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 810 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 811 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 812 } 813 } 814 } 815 816 is(UopSplitType.VEC_ISLIDEDOWN) { 817 // LMUL 818 for (i <- 0 until MAX_VLMUL) 819 for (j <- (0 to i).reverse) { 820 when(i.U < lmul) { 821 val old_vd = if (j == 0) { 822 dest + lmul - 1.U - i.U 823 } else (VECTOR_TMP_REG_LMUL + j - 1).U 824 val vd = if (j == i) { 825 dest + lmul - 1.U - i.U 826 } else (VECTOR_TMP_REG_LMUL + j).U 827 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 828 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 829 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 830 csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 1).U 831 } 832 } 833 } 834 835 is(UopSplitType.VEC_M0X) { 836 // LMUL 837 for (i <- 0 until MAX_VLMUL) { 838 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 839 val ldest = (VECTOR_TMP_REG_LMUL + i).U 840 csBundle(i).srcType(0) := srcType0 841 csBundle(i).srcType(1) := SrcType.vp 842 csBundle(i).rfWen := false.B 843 csBundle(i).vecWen := true.B 844 csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 845 csBundle(i).lsrc(1) := src2 846 // csBundle(i).lsrc(2) := dest + i.U DontCare 847 csBundle(i).ldest := ldest 848 csBundle(i).uopIdx := i.U 849 } 850 csBundle(lmul - 1.U).vecWen := false.B 851 csBundle(lmul - 1.U).fpWen := true.B 852 csBundle(lmul - 1.U).ldest := FP_TMP_REG_MV.U 853 // FMV_X_D 854 csBundle(lmul).srcType(0) := SrcType.fp 855 csBundle(lmul).srcType(1) := SrcType.imm 856 csBundle(lmul).lsrc(0) := FP_TMP_REG_MV.U 857 csBundle(lmul).lsrc(1) := 0.U 858 csBundle(lmul).ldest := dest 859 csBundle(lmul).fuType := FuType.fmisc.U 860 csBundle(lmul).rfWen := true.B 861 csBundle(lmul).fpWen := false.B 862 csBundle(lmul).vecWen := false.B 863 csBundle(lmul).fpu.isAddSub := false.B 864 csBundle(lmul).fpu.typeTagIn := FPU.D 865 csBundle(lmul).fpu.typeTagOut := FPU.D 866 csBundle(lmul).fpu.fromInt := false.B 867 csBundle(lmul).fpu.wflags := false.B 868 csBundle(lmul).fpu.fpWen := false.B 869 csBundle(lmul).fpu.div := false.B 870 csBundle(lmul).fpu.sqrt := false.B 871 csBundle(lmul).fpu.fcvt := false.B 872 } 873 874 is(UopSplitType.VEC_MVV) { 875 // LMUL 876 for (i <- 0 until MAX_VLMUL) { 877 val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 878 csBundle(i * 2 + 0).srcType(0) := srcType0 879 csBundle(i * 2 + 0).srcType(1) := SrcType.vp 880 csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 881 csBundle(i * 2 + 0).lsrc(1) := src2 882 csBundle(i * 2 + 0).lsrc(2) := dest + i.U 883 csBundle(i * 2 + 0).ldest := dest + i.U 884 csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 885 886 csBundle(i * 2 + 1).srcType(0) := srcType0 887 csBundle(i * 2 + 1).srcType(1) := SrcType.vp 888 csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 889 csBundle(i * 2 + 1).lsrc(1) := src2 890 // csBundle(i).lsrc(2) := dest + i.U DontCare 891 csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 892 csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 893 } 894 } 895 896 is(UopSplitType.VEC_M0X_VFIRST) { 897 // LMUL 898 csBundle(0).rfWen := false.B 899 csBundle(0).fpWen := true.B 900 csBundle(0).ldest := FP_TMP_REG_MV.U 901 // FMV_X_D 902 csBundle(1).srcType(0) := SrcType.fp 903 csBundle(1).srcType(1) := SrcType.imm 904 csBundle(1).lsrc(0) := FP_TMP_REG_MV.U 905 csBundle(1).lsrc(1) := 0.U 906 csBundle(1).ldest := dest 907 csBundle(1).fuType := FuType.fmisc.U 908 csBundle(1).rfWen := true.B 909 csBundle(1).fpWen := false.B 910 csBundle(1).vecWen := false.B 911 csBundle(1).fpu.isAddSub := false.B 912 csBundle(1).fpu.typeTagIn := FPU.D 913 csBundle(1).fpu.typeTagOut := FPU.D 914 csBundle(1).fpu.fromInt := false.B 915 csBundle(1).fpu.wflags := false.B 916 csBundle(1).fpu.fpWen := false.B 917 csBundle(1).fpu.div := false.B 918 csBundle(1).fpu.sqrt := false.B 919 csBundle(1).fpu.fcvt := false.B 920 } 921 is(UopSplitType.VEC_VWW) { 922 for (i <- 0 until MAX_VLMUL*2) { 923 when(i.U < lmul){ 924 csBundle(i).srcType(2) := SrcType.DC 925 csBundle(i).lsrc(0) := src2 + i.U 926 csBundle(i).lsrc(1) := src2 + i.U 927 // csBundle(i).lsrc(2) := dest + (2 * i).U 928 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 929 csBundle(i).uopIdx := i.U 930 } otherwise { 931 csBundle(i).srcType(2) := SrcType.DC 932 csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 933 csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 934 // csBundle(i).lsrc(2) := dest + (2 * i).U 935 csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 936 csBundle(i).uopIdx := i.U 937 } 938 csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 939 csBundle(numOfUop-1.U).lsrc(0) := src1 940 csBundle(numOfUop-1.U).lsrc(2) := dest 941 csBundle(numOfUop-1.U).ldest := dest 942 } 943 } 944 is(UopSplitType.VEC_RGATHER) { 945 def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 946 for (i <- 0 until len) 947 for (j <- 0 until len) { 948 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 949 // csBundle(i * len + j).srcType(1) := SrcType.vp 950 // csBundle(i * len + j).srcType(2) := SrcType.vp 951 csBundle(i * len + j).lsrc(0) := src1 + i.U 952 csBundle(i * len + j).lsrc(1) := src2 + j.U 953 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 954 csBundle(i * len + j).lsrc(2) := vd_old 955 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 956 csBundle(i * len + j).ldest := vd 957 csBundle(i * len + j).uopIdx := (i * len + j).U 958 } 959 } 960 switch(simple.io.enq.vtype.vlmul) { 961 is("b001".U ){ 962 genCsBundle_VEC_RGATHER(2) 963 } 964 is("b010".U ){ 965 genCsBundle_VEC_RGATHER(4) 966 } 967 is("b011".U ){ 968 genCsBundle_VEC_RGATHER(8) 969 } 970 } 971 } 972 is(UopSplitType.VEC_RGATHER_VX) { 973 def genCsBundle_RGATHER_VX(len:Int): Unit ={ 974 for (i <- 0 until len) 975 for (j <- 0 until len) { 976 csBundle(i * len + j + 1).srcType(0) := SrcType.fp 977 // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 978 // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 979 csBundle(i * len + j + 1).lsrc(0) := FP_TMP_REG_MV.U 980 csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 981 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 982 csBundle(i * len + j + 1).lsrc(2) := vd_old 983 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 984 csBundle(i * len + j + 1).ldest := vd 985 csBundle(i * len + j + 1).uopIdx := (i * len + j).U 986 } 987 } 988 // FMV.D.X 989 csBundle(0).srcType(0) := SrcType.reg 990 csBundle(0).srcType(1) := SrcType.imm 991 csBundle(0).lsrc(1) := 0.U 992 csBundle(0).ldest := FP_TMP_REG_MV.U 993 csBundle(0).fuType := FuType.i2f.U 994 csBundle(0).rfWen := false.B 995 csBundle(0).fpWen := true.B 996 csBundle(0).vecWen := false.B 997 csBundle(0).fpu.isAddSub := false.B 998 csBundle(0).fpu.typeTagIn := FPU.D 999 csBundle(0).fpu.typeTagOut := FPU.D 1000 csBundle(0).fpu.fromInt := true.B 1001 csBundle(0).fpu.wflags := false.B 1002 csBundle(0).fpu.fpWen := true.B 1003 csBundle(0).fpu.div := false.B 1004 csBundle(0).fpu.sqrt := false.B 1005 csBundle(0).fpu.fcvt := false.B 1006 switch(simple.io.enq.vtype.vlmul) { 1007 is("b000".U ){ 1008 genCsBundle_RGATHER_VX(1) 1009 } 1010 is("b001".U ){ 1011 genCsBundle_RGATHER_VX(2) 1012 } 1013 is("b010".U ){ 1014 genCsBundle_RGATHER_VX(4) 1015 } 1016 is("b011".U ){ 1017 genCsBundle_RGATHER_VX(8) 1018 } 1019 } 1020 } 1021 is(UopSplitType.VEC_RGATHEREI16) { 1022 def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1023 for (i <- 0 until len) 1024 for (j <- 0 until len) { 1025 val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1026 val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1027 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1028 // csBundle(i * len + j).srcType(1) := SrcType.vp 1029 // csBundle(i * len + j).srcType(2) := SrcType.vp 1030 csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1031 csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1032 csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1033 csBundle((i * len + j)*2+0).ldest := vd0 1034 csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1035 val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1036 val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1037 csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1038 csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1039 csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1040 csBundle((i * len + j)*2+1).ldest := vd1 1041 csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1042 } 1043 } 1044 def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1045 for (i <- 0 until len) 1046 for (j <- 0 until len) { 1047 val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1048 val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1049 // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1050 // csBundle(i * len + j).srcType(1) := SrcType.vp 1051 // csBundle(i * len + j).srcType(2) := SrcType.vp 1052 csBundle(i * len + j).lsrc(0) := src1 + i.U 1053 csBundle(i * len + j).lsrc(1) := src2 + j.U 1054 csBundle(i * len + j).lsrc(2) := vd_old 1055 csBundle(i * len + j).ldest := vd 1056 csBundle(i * len + j).uopIdx := (i * len + j).U 1057 } 1058 } 1059 switch(simple.io.enq.vtype.vlmul) { 1060 is("b000".U ){ 1061 when(!simple.io.enq.vtype.vsew.orR){ 1062 genCsBundle_VEC_RGATHEREI16_SEW8(1) 1063 } .otherwise{ 1064 genCsBundle_VEC_RGATHEREI16(1) 1065 } 1066 } 1067 is("b001".U) { 1068 when(!simple.io.enq.vtype.vsew.orR) { 1069 genCsBundle_VEC_RGATHEREI16_SEW8(2) 1070 }.otherwise { 1071 genCsBundle_VEC_RGATHEREI16(2) 1072 } 1073 } 1074 is("b010".U) { 1075 when(!simple.io.enq.vtype.vsew.orR) { 1076 genCsBundle_VEC_RGATHEREI16_SEW8(4) 1077 }.otherwise { 1078 genCsBundle_VEC_RGATHEREI16(4) 1079 } 1080 } 1081 is("b011".U) { 1082 genCsBundle_VEC_RGATHEREI16(8) 1083 } 1084 } 1085 } 1086 is(UopSplitType.VEC_COMPRESS) { 1087 def genCsBundle_VEC_COMPRESS(len:Int): Unit ={ 1088 for (i <- 0 until len){ 1089 val jlen = if (i == len-1) i+1 else i+2 1090 for (j <- 0 until jlen) { 1091 val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1092 val vd = if(i==len-1) (dest + j.U) else{ 1093 if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1094 } 1095 val src23Type = if (j == i+1) DontCare else SrcType.vp 1096 csBundle(i*(i+3)/2 + j).srcType(0) := SrcType.vp 1097 csBundle(i*(i+3)/2 + j).srcType(1) := src23Type 1098 csBundle(i*(i+3)/2 + j).srcType(2) := src23Type 1099 csBundle(i*(i+3)/2 + j).lsrc(0) := src1 1100 csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1101 csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1102 // csBundle(i*(i+3)/2 + j).lsrc(3) := VECTOR_TMP_REG_LMUL.U 1103 csBundle(i*(i+3)/2 + j).ldest := vd 1104 csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1105 } 1106 } 1107 } 1108 switch(simple.io.enq.vtype.vlmul) { 1109 is("b001".U ){ 1110 genCsBundle_VEC_COMPRESS(2) 1111 } 1112 is("b010".U ){ 1113 genCsBundle_VEC_COMPRESS(4) 1114 } 1115 is("b011".U ){ 1116 genCsBundle_VEC_COMPRESS(8) 1117 } 1118 } 1119 } 1120 is(UopSplitType.VEC_US_LD) { 1121 /* 1122 FMV.D.X 1123 */ 1124 csBundle(0).srcType(0) := SrcType.reg 1125 csBundle(0).srcType(1) := SrcType.imm 1126 csBundle(0).lsrc(1) := 0.U 1127 csBundle(0).ldest := FP_TMP_REG_MV.U 1128 csBundle(0).fuType := FuType.i2f.U 1129 csBundle(0).rfWen := false.B 1130 csBundle(0).fpWen := true.B 1131 csBundle(0).vecWen := false.B 1132 csBundle(0).fpu.isAddSub := false.B 1133 csBundle(0).fpu.typeTagIn := FPU.D 1134 csBundle(0).fpu.typeTagOut := FPU.D 1135 csBundle(0).fpu.fromInt := true.B 1136 csBundle(0).fpu.wflags := false.B 1137 csBundle(0).fpu.fpWen := true.B 1138 csBundle(0).fpu.div := false.B 1139 csBundle(0).fpu.sqrt := false.B 1140 csBundle(0).fpu.fcvt := false.B 1141 //LMUL 1142 for (i <- 0 until MAX_VLMUL) { 1143 csBundle(i + 1).srcType(0) := SrcType.fp 1144 csBundle(i + 1).lsrc(0) := FP_TMP_REG_MV.U 1145 csBundle(i + 1).ldest := dest + i.U 1146 csBundle(i + 1).uopIdx := i.U 1147 } 1148 } 1149 } 1150 1151 //uops dispatch 1152 val s_normal :: s_ext :: Nil = Enum(2) 1153 val state = RegInit(s_normal) 1154 val state_next = WireDefault(state) 1155 val uopRes = RegInit(0.U) 1156 1157 //readyFromRename Counter 1158 val readyCounter = PriorityMuxDefault(io.readyFromRename.map(x => !x).zip((0 to (RenameWidth - 1)).map(_.U)), RenameWidth.U) 1159 1160 switch(state) { 1161 is(s_normal) { 1162 state_next := Mux(io.validFromIBuf(0) && (numOfUop > readyCounter) && (readyCounter =/= 0.U), s_ext, s_normal) 1163 } 1164 is(s_ext) { 1165 state_next := Mux(io.validFromIBuf(0) && (uopRes > readyCounter), s_ext, s_normal) 1166 } 1167 } 1168 1169 state := state_next 1170 1171 val uopRes0 = Mux(state === s_normal, numOfUop, uopRes) 1172 val uopResJudge = Mux(state === s_normal, 1173 io.validFromIBuf(0) && (readyCounter =/= 0.U) && (uopRes0 > readyCounter), 1174 io.validFromIBuf(0) && (uopRes0 > readyCounter)) 1175 uopRes := Mux(uopResJudge, uopRes0 - readyCounter, 0.U) 1176 1177 for(i <- 0 until RenameWidth) { 1178 decodedInsts(i) := MuxCase(csBundle(i), Seq( 1179 (state === s_normal) -> csBundle(i), 1180 (state === s_ext) -> Mux((i.U + numOfUop -uopRes) < maxUopSize.U, csBundle(i.U + numOfUop - uopRes), csBundle(maxUopSize - 1)) 1181 )) 1182 } 1183 1184 1185 val validSimple = Wire(Vec(DecodeWidth - 1, Bool())) 1186 validSimple.zip(io.validFromIBuf.drop(1).zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 1187 val notInf = Wire(Vec(DecodeWidth - 1, Bool())) 1188 notInf.zip(io.validFromIBuf.drop(1).zip(validSimple)).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 1189 val notInfVec = Wire(Vec(DecodeWidth, Bool())) 1190 notInfVec.drop(1).zip(0 until DecodeWidth - 1).map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 1191 notInfVec(0) := true.B 1192 1193 complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 1194 Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 1195 1.U) 1196 validToRename.zipWithIndex.foreach{ 1197 case(dst, i) => 1198 dst := MuxCase(false.B, Seq( 1199 (io.validFromIBuf(0) && uopRes0 > readyCounter ) -> Mux(readyCounter > i.U, true.B, false.B), 1200 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validSimple(i.U - complexNum) && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 1201 )) 1202 } 1203 1204 readyToIBuf.zipWithIndex.foreach { 1205 case (dst, i) => 1206 dst := MuxCase(true.B, Seq( 1207 (io.validFromIBuf(0) && uopRes0 > readyCounter) -> false.B, 1208 (io.validFromIBuf(0) && !(uopRes0 > readyCounter)) -> (if (i==0) true.B else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i - 1) && validSimple(i - 1) && io.readyFromRename(i), false.B)), 1209 )) 1210 } 1211 1212 io.deq.decodedInsts := decodedInsts 1213 io.deq.isVset := isVsetSimple 1214 io.deq.complexNum := complexNum 1215 io.deq.validToRename := validToRename 1216 io.deq.readyToIBuf := readyToIBuf 1217 1218} 1219