1d91483a6Sfdy/*************************************************************************************** 2e3da8badSTang Haojin * Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3e3da8badSTang Haojin * Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences 4d91483a6Sfdy * Copyright (c) 2020-2021 Peng Cheng Laboratory 5d91483a6Sfdy * 6d91483a6Sfdy * XiangShan is licensed under Mulan PSL v2. 7d91483a6Sfdy * You can use this software according to the terms and conditions of the Mulan PSL v2. 8d91483a6Sfdy * You may obtain a copy of Mulan PSL v2 at: 9d91483a6Sfdy * http://license.coscl.org.cn/MulanPSL2 10d91483a6Sfdy * 11d91483a6Sfdy * THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 12d91483a6Sfdy * EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 13d91483a6Sfdy * MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 14d91483a6Sfdy * 15d91483a6Sfdy * See the Mulan PSL v2 for more details. 16d91483a6Sfdy ***************************************************************************************/ 17d91483a6Sfdy 18d91483a6Sfdypackage xiangshan.backend.decode 19d91483a6Sfdy 2083ba63b3SXuan Huimport org.chipsalliance.cde.config.Parameters 21d91483a6Sfdyimport chisel3._ 22d91483a6Sfdyimport chisel3.util._ 23d91483a6Sfdyimport freechips.rocketchip.rocket.Instructions 24d91483a6Sfdyimport freechips.rocketchip.util.uintToBitPat 25d91483a6Sfdyimport utils._ 26d91483a6Sfdyimport utility._ 27d91483a6Sfdyimport xiangshan.ExceptionNO.illegalInstr 28d91483a6Sfdyimport xiangshan._ 29d91483a6Sfdyimport xiangshan.backend.fu.fpu.FPU 30d91483a6Sfdyimport xiangshan.backend.fu.FuType 31d91483a6Sfdyimport freechips.rocketchip.rocket.Instructions._ 32d91483a6Sfdyimport xiangshan.backend.Bundles.{DecodedInst, StaticInst} 3398cfe81bSxgkiriimport xiangshan.backend.decode.isa.bitfield.XSInstBitFields 349fabe323SZiyue Zhangimport xiangshan.backend.fu.vector.Bundles.{VSew, VType, VLmul, Vl} 35d91483a6Sfdyimport yunsuan.VpermType 36c4501a6fSZiyue-Zhangimport chisel3.util.experimental.decode.{QMCMinimizer, TruthTable, decoder} 37c4501a6fSZiyue-Zhang 38c4501a6fSZiyue-Zhangclass indexedLSUopTable(uopIdx:Int) extends Module { 3955f7bedaSZiyue Zhang val src = IO(Input(UInt(4.W))) 40c4501a6fSZiyue-Zhang val outOffsetVs2 = IO(Output(UInt(3.W))) 41c4501a6fSZiyue-Zhang val outOffsetVd = IO(Output(UInt(3.W))) 4255f7bedaSZiyue Zhang def genCsBundle_VEC_INDEXED_LDST(lmul:Int, emul:Int, uopIdx:Int): (Int, Int) ={ 4355f7bedaSZiyue Zhang // only consider non segment indexed load/store 44c4501a6fSZiyue-Zhang if (lmul < emul) { // lmul < emul, uop num is depend on emul * nf 45c4501a6fSZiyue-Zhang var offset = 1 << (emul - lmul) 46de785770Szhanglinjuan for (i <- 0 until (1 << emul)) { 4755f7bedaSZiyue Zhang if (uopIdx == i) { 4855f7bedaSZiyue Zhang return (i, i / offset) 49c4501a6fSZiyue-Zhang } 50c4501a6fSZiyue-Zhang } 51c379dcbeSZiyue-Zhang } else { // lmul > emul, uop num is depend on lmul * nf 52c4501a6fSZiyue-Zhang var offset = 1 << (lmul - emul) 53de785770Szhanglinjuan for (i <- 0 until (1 << lmul)) { 5455f7bedaSZiyue Zhang if (uopIdx == i) { 5555f7bedaSZiyue Zhang return (i / offset, i) 56c4501a6fSZiyue-Zhang } 57c4501a6fSZiyue-Zhang } 58c4501a6fSZiyue-Zhang } 5955f7bedaSZiyue Zhang return (0, 0) 60c4501a6fSZiyue-Zhang } 61c4501a6fSZiyue-Zhang // strided load/store 6255f7bedaSZiyue Zhang var combVemulNf : Seq[(Int, Int, Int, Int)] = Seq() 63c4501a6fSZiyue-Zhang for (emul <- 0 until 4) { 64c4501a6fSZiyue-Zhang for (lmul <- 0 until 4) { 6555f7bedaSZiyue Zhang var offset = genCsBundle_VEC_INDEXED_LDST(lmul, emul, uopIdx) 66c4501a6fSZiyue-Zhang var offsetVs2 = offset._1 67c4501a6fSZiyue-Zhang var offsetVd = offset._2 6855f7bedaSZiyue Zhang combVemulNf :+= (emul, lmul, offsetVs2, offsetVd) 69c4501a6fSZiyue-Zhang } 70c4501a6fSZiyue-Zhang } 710cd00663SzhanglyGit val out = decoder(QMCMinimizer, src, TruthTable(combVemulNf.map { 7255f7bedaSZiyue Zhang case (emul, lmul, offsetVs2, offsetVd) => 7355f7bedaSZiyue Zhang (BitPat((emul << 2 | lmul).U(4.W)), BitPat((offsetVs2 << 3 | offsetVd).U(6.W))) 7455f7bedaSZiyue Zhang }, BitPat.N(6))) 75c4501a6fSZiyue-Zhang outOffsetVs2 := out(5, 3) 76c4501a6fSZiyue-Zhang outOffsetVd := out(2, 0) 77c4501a6fSZiyue-Zhang} 78d91483a6Sfdy 79d91483a6Sfdytrait VectorConstants { 80d91483a6Sfdy val MAX_VLMUL = 8 81ac0f8299SZiyue Zhang val VECTOR_TMP_REG_LMUL = 32 // 32~46 -> 15 82e4e68f86Sxiaofeibao val VECTOR_COMPRESS = 1 // in v0 regfile 83c4501a6fSZiyue-Zhang val MAX_INDEXED_LS_UOPNUM = 64 84d91483a6Sfdy} 85d91483a6Sfdy 86d91483a6Sfdyclass DecodeUnitCompIO(implicit p: Parameters) extends XSBundle { 87e25c13faSXuan Hu val redirect = Input(Bool()) 88d91483a6Sfdy val csrCtrl = Input(new CustomCSRCtrlIO) 8996a12457Ssinsanction val vtypeBypass = Input(new VType) 90e25c13faSXuan Hu // When the first inst in decode vector is complex inst, pass it in 91e25c13faSXuan Hu val in = Flipped(DecoupledIO(new Bundle { 92e25c13faSXuan Hu val simpleDecodedInst = new DecodedInst 93e25c13faSXuan Hu val uopInfo = new UopInfo 94e25c13faSXuan Hu })) 95e25c13faSXuan Hu val out = new Bundle { 96e25c13faSXuan Hu val complexDecodedInsts = Vec(RenameWidth, DecoupledIO(new DecodedInst)) 97e25c13faSXuan Hu } 98e25c13faSXuan Hu val complexNum = Output(UInt(3.W)) 99d91483a6Sfdy} 10017ec87f2SXuan Hu 101d91483a6Sfdy/** 102d91483a6Sfdy * @author zly 103d91483a6Sfdy */ 104d91483a6Sfdyclass DecodeUnitComp()(implicit p : Parameters) extends XSModule with DecodeUnitConstants with VectorConstants { 105d91483a6Sfdy val io = IO(new DecodeUnitCompIO) 106d91483a6Sfdy 107e25c13faSXuan Hu // alias 108e25c13faSXuan Hu private val inReady = io.in.ready 109e25c13faSXuan Hu private val inValid = io.in.valid 110e25c13faSXuan Hu private val inDecodedInst = WireInit(io.in.bits.simpleDecodedInst) 111229ab603SXuan Hu private val inInstFields = io.in.bits.simpleDecodedInst.instr.asTypeOf(new XSInstBitFields) 112e25c13faSXuan Hu private val inUopInfo = io.in.bits.uopInfo 113e25c13faSXuan Hu private val outValids = io.out.complexDecodedInsts.map(_.valid) 114e25c13faSXuan Hu private val outReadys = io.out.complexDecodedInsts.map(_.ready) 115e25c13faSXuan Hu private val outDecodedInsts = io.out.complexDecodedInsts.map(_.bits) 116e25c13faSXuan Hu private val outComplexNum = io.complexNum 117e25c13faSXuan Hu 118d91483a6Sfdy val maxUopSize = MaxUopSize 119229ab603SXuan Hu when (io.in.fire && io.in.bits.simpleDecodedInst.isVset) { 120229ab603SXuan Hu when(inInstFields.RD === 0.U && inInstFields.RS1 === 0.U) { 121229ab603SXuan Hu inDecodedInst.fuOpType := VSETOpType.keepVl(io.in.bits.simpleDecodedInst.fuOpType) 122229ab603SXuan Hu }.elsewhen(inInstFields.RS1 === 0.U) { 123229ab603SXuan Hu inDecodedInst.fuOpType := VSETOpType.setVlmax(io.in.bits.simpleDecodedInst.fuOpType) 124229ab603SXuan Hu } 125229ab603SXuan Hu } 126229ab603SXuan Hu 127e25c13faSXuan Hu val latchedInst = RegEnable(inDecodedInst, inValid && inReady) 128e25c13faSXuan Hu val latchedUopInfo = RegEnable(inUopInfo, inValid && inReady) 129d91483a6Sfdy //input bits 130e25c13faSXuan Hu private val instFields: XSInstBitFields = latchedInst.instr.asTypeOf(new XSInstBitFields) 131d91483a6Sfdy 132e25c13faSXuan Hu val src1 = Cat(0.U(1.W), instFields.RS1) 133e25c13faSXuan Hu val src2 = Cat(0.U(1.W), instFields.RS2) 134e25c13faSXuan Hu val dest = Cat(0.U(1.W), instFields.RD) 1357f9f0a79SzhanglyGit 136e25c13faSXuan Hu val nf = instFields.NF 137e25c13faSXuan Hu val width = instFields.WIDTH(1, 0) 138d91483a6Sfdy 139d91483a6Sfdy //output of DecodeUnit 140e25c13faSXuan Hu val numOfUop = Wire(UInt(log2Up(maxUopSize).W)) 141e25c13faSXuan Hu val numOfWB = Wire(UInt(log2Up(maxUopSize).W)) 1427f9f0a79SzhanglyGit val lmul = Wire(UInt(4.W)) 143189ec863SzhanglyGit val isVsetSimple = Wire(Bool()) 144d91483a6Sfdy 14555f7bedaSZiyue Zhang val indexedLSRegOffset = Seq.tabulate(MAX_VLMUL)(i => Module(new indexedLSUopTable(i))) 146c4501a6fSZiyue-Zhang indexedLSRegOffset.map(_.src := 0.U) 147c4501a6fSZiyue-Zhang 148d91483a6Sfdy //pre decode 149e25c13faSXuan Hu lmul := latchedUopInfo.lmul 150e25c13faSXuan Hu isVsetSimple := latchedInst.isVset 151e25c13faSXuan Hu val vlmulReg = latchedInst.vpu.vlmul 152e25c13faSXuan Hu val vsewReg = latchedInst.vpu.vsew 1535110577fSZiyue Zhang val vstartReg = latchedInst.vpu.vstart 154229ab603SXuan Hu 155d91483a6Sfdy //Type of uop Div 156e25c13faSXuan Hu val typeOfSplit = latchedInst.uopSplitType 157e25c13faSXuan Hu val src1Type = latchedInst.srcType(0) 158d6059658SZiyue Zhang val src1IsImm = src1Type === SrcType.imm 159395c8649SZiyue-Zhang val src1IsFp = src1Type === SrcType.fp 160d91483a6Sfdy 1617635b2a1SZiyue Zhang val isVstore = FuType.isVStore(latchedInst.fuType) 1627635b2a1SZiyue Zhang 1639fabe323SZiyue Zhang // exception generator 1649fabe323SZiyue Zhang val vecException = Module(new VecExceptionGen) 1659fabe323SZiyue Zhang vecException.io.inst := latchedInst.instr 1669fabe323SZiyue Zhang vecException.io.decodedInst := latchedInst 1679fabe323SZiyue Zhang vecException.io.vtype := latchedInst.vpu.vtype 1689fabe323SZiyue Zhang vecException.io.vstart := latchedInst.vpu.vstart 1699fabe323SZiyue Zhang val illegalInst = vecException.io.illegalInst 1709fabe323SZiyue Zhang 171e25c13faSXuan Hu numOfUop := latchedUopInfo.numOfUop 172e25c13faSXuan Hu numOfWB := latchedUopInfo.numOfWB 173e25c13faSXuan Hu 174e25c13faSXuan Hu //uops dispatch 175e25c13faSXuan Hu val s_idle :: s_active :: Nil = Enum(2) 176e25c13faSXuan Hu val state = RegInit(s_idle) 177e25c13faSXuan Hu val stateNext = WireDefault(state) 178e25c13faSXuan Hu val numDecodedUop = RegInit(0.U(log2Up(maxUopSize).W)) 179e25c13faSXuan Hu val uopRes = RegInit(0.U(log2Up(maxUopSize).W)) 180e25c13faSXuan Hu val uopResNext = WireInit(uopRes) 181964d9a87SZiyue Zhang val e64 = 3.U(2.W) 182b0480352SZiyue Zhang val isUsSegment = instFields.MOP === 0.U && ((nf =/= 0.U && instFields.LUMOP === 0.U) || instFields.LUMOP === "b10000".U) 1834aa00286SXuan Hu val isIxSegment = instFields.MOP(0) === 1.U && nf =/= 0.U 1844aa00286SXuan Hu val isSdSegment = instFields.MOP === "b10".U && nf =/= 0.U 1857f9f0a79SzhanglyGit 186d91483a6Sfdy //uop div up to maxUopSize 187d91483a6Sfdy val csBundle = Wire(Vec(maxUopSize, new DecodedInst)) 1888e59a3a7SXuan Hu val fixedDecodedInst = Wire(Vec(maxUopSize, new DecodedInst)) 1898e59a3a7SXuan Hu 190e25c13faSXuan Hu csBundle.foreach { case dst => 191e25c13faSXuan Hu dst := latchedInst 192e25c13faSXuan Hu dst.numUops := latchedUopInfo.numOfUop 193e25c13faSXuan Hu dst.numWB := latchedUopInfo.numOfWB 1949fabe323SZiyue Zhang dst.exceptionVec(ExceptionNO.EX_II) := latchedInst.exceptionVec(ExceptionNO.EX_II) || illegalInst 195d91483a6Sfdy dst.firstUop := false.B 196d91483a6Sfdy dst.lastUop := false.B 19731c51290Szhanglinjuan dst.vlsInstr := false.B 198d91483a6Sfdy } 199d91483a6Sfdy 200d91483a6Sfdy csBundle(0).firstUop := true.B 201d91483a6Sfdy csBundle(numOfUop - 1.U).lastUop := true.B 202d91483a6Sfdy 2035110577fSZiyue Zhang // when vstart is not zero, the last uop will modify vstart to zero 2045110577fSZiyue Zhang // therefore, blockback and flush pipe 2055110577fSZiyue Zhang csBundle(numOfUop - 1.U).blockBackward := vstartReg =/= 0.U 20693df46dcSZiyue Zhang csBundle(0.U).flushPipe := vstartReg =/= 0.U 2075110577fSZiyue Zhang 208189ec863SzhanglyGit switch(typeOfSplit) { 20912861ac7Slinzhida is(UopSplitType.AMO_CAS_W) { 21012861ac7Slinzhida csBundle(0).uopIdx := 0.U 21112861ac7Slinzhida csBundle(0).fuOpType := Cat(0.U(3.W), LSUOpType.amocas_w) 21212861ac7Slinzhida csBundle(0).lsrc(0) := src1 21312861ac7Slinzhida csBundle(0).lsrc(1) := dest 21412861ac7Slinzhida csBundle(0).waitForward := true.B 21512861ac7Slinzhida csBundle(0).blockBackward := false.B 21612861ac7Slinzhida 21712861ac7Slinzhida csBundle(1).uopIdx := 1.U 21812861ac7Slinzhida csBundle(1).fuOpType := Cat(1.U(3.W), LSUOpType.amocas_w) 21912861ac7Slinzhida csBundle(1).lsrc(0) := src1 22012861ac7Slinzhida csBundle(1).lsrc(1) := src2 22112861ac7Slinzhida csBundle(1).rfWen := false.B 22212861ac7Slinzhida csBundle(1).waitForward := false.B 22312861ac7Slinzhida csBundle(1).blockBackward := true.B 22412861ac7Slinzhida } 22512861ac7Slinzhida is(UopSplitType.AMO_CAS_D) { 22612861ac7Slinzhida csBundle(0).uopIdx := 0.U 22712861ac7Slinzhida csBundle(0).fuOpType := Cat(0.U(3.W), LSUOpType.amocas_d) 22812861ac7Slinzhida csBundle(0).lsrc(0) := src1 22912861ac7Slinzhida csBundle(0).lsrc(1) := dest 23012861ac7Slinzhida csBundle(0).waitForward := true.B 23112861ac7Slinzhida csBundle(0).blockBackward := false.B 23212861ac7Slinzhida 23312861ac7Slinzhida csBundle(1).uopIdx := 1.U 23412861ac7Slinzhida csBundle(1).fuOpType := Cat(1.U(3.W), LSUOpType.amocas_d) 23512861ac7Slinzhida csBundle(1).lsrc(0) := src1 23612861ac7Slinzhida csBundle(1).lsrc(1) := src2 23712861ac7Slinzhida csBundle(1).rfWen := false.B 23812861ac7Slinzhida csBundle(1).waitForward := false.B 23912861ac7Slinzhida csBundle(1).blockBackward := true.B 24012861ac7Slinzhida } 24112861ac7Slinzhida is(UopSplitType.AMO_CAS_Q) { 24212861ac7Slinzhida csBundle(0).uopIdx := 0.U 24312861ac7Slinzhida csBundle(0).fuOpType := Cat(0.U(3.W), LSUOpType.amocas_q) 24412861ac7Slinzhida csBundle(0).lsrc(0) := src1 24512861ac7Slinzhida csBundle(0).lsrc(1) := dest 24612861ac7Slinzhida csBundle(0).waitForward := true.B 24712861ac7Slinzhida csBundle(0).blockBackward := false.B 24812861ac7Slinzhida 24912861ac7Slinzhida csBundle(1).uopIdx := 1.U 25012861ac7Slinzhida csBundle(1).fuOpType := Cat(1.U(3.W), LSUOpType.amocas_q) 25112861ac7Slinzhida csBundle(1).lsrc(0) := src1 25212861ac7Slinzhida csBundle(1).lsrc(1) := src2 25312861ac7Slinzhida csBundle(1).rfWen := false.B 25412861ac7Slinzhida csBundle(1).waitForward := false.B 25512861ac7Slinzhida csBundle(1).blockBackward := false.B 25612861ac7Slinzhida 25712861ac7Slinzhida csBundle(2).uopIdx := 2.U 25812861ac7Slinzhida csBundle(2).fuOpType := Cat(2.U(3.W), LSUOpType.amocas_q) 25912861ac7Slinzhida csBundle(2).lsrc(0) := src1 26012861ac7Slinzhida csBundle(2).lsrc(1) := Mux(dest === 0.U, 0.U, dest + 1.U) 26112861ac7Slinzhida csBundle(2).ldest := Mux(dest === 0.U, 0.U, dest + 1.U) 26212861ac7Slinzhida csBundle(2).waitForward := false.B 26312861ac7Slinzhida csBundle(2).blockBackward := false.B 26412861ac7Slinzhida 26512861ac7Slinzhida csBundle(3).uopIdx := 3.U 26612861ac7Slinzhida csBundle(3).fuOpType := Cat(3.U(3.W), LSUOpType.amocas_q) 26712861ac7Slinzhida csBundle(3).lsrc(0) := src1 26812861ac7Slinzhida csBundle(3).lsrc(1) := Mux(src2 === 0.U, 0.U, src2 + 1.U) 26912861ac7Slinzhida csBundle(3).rfWen := false.B 27012861ac7Slinzhida csBundle(3).waitForward := false.B 27112861ac7Slinzhida csBundle(3).blockBackward := true.B 27212861ac7Slinzhida } 273e25c13faSXuan Hu is(UopSplitType.VSET) { 2744cdab2a9SXuan Hu // In simple decoder, rfWen and vecWen are not set 275189ec863SzhanglyGit when(isVsetSimple) { 2764cdab2a9SXuan Hu // Default 2774cdab2a9SXuan Hu // uop0 set rd, never flushPipe 278d91483a6Sfdy csBundle(0).fuType := FuType.vsetiwi.U 27993df46dcSZiyue Zhang csBundle(0).flushPipe := Mux(VSETOpType.isVsetvl(latchedInst.fuOpType), true.B, vstartReg =/= 0.U) 2801436b764SZiyue Zhang csBundle(0).blockBackward := false.B 281d91483a6Sfdy csBundle(0).rfWen := true.B 2824cdab2a9SXuan Hu // uop1 set vl, vsetvl will flushPipe 283430c2c95Sxiaofeibao csBundle(1).ldest := Vl_IDX.U 284e4e68f86Sxiaofeibao csBundle(1).vecWen := false.B 285e4e68f86Sxiaofeibao csBundle(1).vlWen := true.B 28693df46dcSZiyue Zhang csBundle(1).flushPipe := false.B 28793df46dcSZiyue Zhang csBundle(1).blockBackward := Mux(VSETOpType.isVsetvl(latchedInst.fuOpType), true.B, vstartReg =/= 0.U) 2884cdab2a9SXuan Hu when(VSETOpType.isVsetvli(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 289d8ceb649SZiyue Zhang // write nothing, uop0 is a nop instruction 290d8ceb649SZiyue Zhang csBundle(0).rfWen := false.B 291d8ceb649SZiyue Zhang csBundle(0).fpWen := false.B 292d8ceb649SZiyue Zhang csBundle(0).vecWen := false.B 293e4e68f86Sxiaofeibao csBundle(0).vlWen := false.B 2944cdab2a9SXuan Hu csBundle(1).fuType := FuType.vsetfwf.U 295b37ee2eeSZiyue-Zhang csBundle(1).srcType(0) := SrcType.no 296b37ee2eeSZiyue-Zhang csBundle(1).srcType(2) := SrcType.no 297b37ee2eeSZiyue-Zhang csBundle(1).srcType(3) := SrcType.no 298b37ee2eeSZiyue-Zhang csBundle(1).srcType(4) := SrcType.vp 299b37ee2eeSZiyue-Zhang csBundle(1).lsrc(4) := Vl_IDX.U 3004cdab2a9SXuan Hu }.elsewhen(VSETOpType.isVsetvl(latchedInst.fuOpType) && dest === 0.U && src1 === 0.U) { 3014cdab2a9SXuan Hu // uop0: mv vtype gpr to vector region 3024cdab2a9SXuan Hu csBundle(0).srcType(0) := SrcType.xp 3034cdab2a9SXuan Hu csBundle(0).srcType(1) := SrcType.no 3040f423558SZiyue-Zhang csBundle(0).lsrc(0) := src2 305d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 306c8cff56fSsinsanction csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 307964d9a87SZiyue Zhang csBundle(0).fuType := FuType.i2v.U 308964d9a87SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 309964d9a87SZiyue Zhang csBundle(0).rfWen := false.B 310c8cff56fSsinsanction csBundle(0).fpWen := false.B 311c8cff56fSsinsanction csBundle(0).vecWen := true.B 312e4e68f86Sxiaofeibao csBundle(0).vlWen := false.B 3134cdab2a9SXuan Hu // uop1: uvsetvcfg_vv 314d91483a6Sfdy csBundle(1).fuType := FuType.vsetfwf.U 3154cdab2a9SXuan Hu // vl 316b37ee2eeSZiyue-Zhang csBundle(1).srcType(0) := SrcType.no 317b37ee2eeSZiyue-Zhang csBundle(1).srcType(2) := SrcType.no 318b37ee2eeSZiyue-Zhang csBundle(1).srcType(3) := SrcType.no 319b37ee2eeSZiyue-Zhang csBundle(1).srcType(4) := SrcType.vp 320b37ee2eeSZiyue-Zhang csBundle(1).lsrc(4) := Vl_IDX.U 3214cdab2a9SXuan Hu // vtype 322c8cff56fSsinsanction csBundle(1).srcType(1) := SrcType.vp 323c8cff56fSsinsanction csBundle(1).lsrc(1) := VECTOR_TMP_REG_LMUL.U 324e4e68f86Sxiaofeibao csBundle(1).vecWen := false.B 325e4e68f86Sxiaofeibao csBundle(1).vlWen := true.B 326430c2c95Sxiaofeibao csBundle(1).ldest := Vl_IDX.U 32717d9db4eSZiyue Zhang }.elsewhen(dest === 0.U) { 32817d9db4eSZiyue Zhang // write nothing, uop0 is a nop instruction 32917d9db4eSZiyue Zhang csBundle(0).rfWen := false.B 33017d9db4eSZiyue Zhang csBundle(0).fpWen := false.B 33117d9db4eSZiyue Zhang csBundle(0).vecWen := false.B 332e4e68f86Sxiaofeibao csBundle(0).vlWen := false.B 333e03e0c5bSZiyue Zhang }.elsewhen(VSETOpType.isVsetvl(latchedInst.fuOpType)) { 334e03e0c5bSZiyue Zhang // because vsetvl may modified src2 when src2 == rd, 335e03e0c5bSZiyue Zhang // we need to modify vd in second uop to avoid dependency 336e03e0c5bSZiyue Zhang // uop0 set vl 337e03e0c5bSZiyue Zhang csBundle(0).fuType := FuType.vsetiwf.U 338e03e0c5bSZiyue Zhang csBundle(0).ldest := Vl_IDX.U 339e03e0c5bSZiyue Zhang csBundle(0).rfWen := false.B 340e03e0c5bSZiyue Zhang csBundle(0).vlWen := true.B 341e03e0c5bSZiyue Zhang // uop1 set rd 342e03e0c5bSZiyue Zhang csBundle(1).fuType := FuType.vsetiwi.U 343e03e0c5bSZiyue Zhang csBundle(1).ldest := dest 344e03e0c5bSZiyue Zhang csBundle(1).rfWen := true.B 345e03e0c5bSZiyue Zhang csBundle(1).vlWen := false.B 346d91483a6Sfdy } 34796a12457Ssinsanction // use bypass vtype from vtypeGen 34896a12457Ssinsanction csBundle(0).vpu.connectVType(io.vtypeBypass) 34996a12457Ssinsanction csBundle(1).vpu.connectVType(io.vtypeBypass) 350d91483a6Sfdy } 351d91483a6Sfdy } 35217ec87f2SXuan Hu is(UopSplitType.VEC_VVV) { 353d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 354d91483a6Sfdy csBundle(i).lsrc(0) := src1 + i.U 355d91483a6Sfdy csBundle(i).lsrc(1) := src2 + i.U 356d91483a6Sfdy csBundle(i).lsrc(2) := dest + i.U 357d91483a6Sfdy csBundle(i).ldest := dest + i.U 358d91483a6Sfdy csBundle(i).uopIdx := i.U 359d91483a6Sfdy } 360d91483a6Sfdy } 361684d7aceSxiaofeibao-xjtu is(UopSplitType.VEC_VFV) { 362395c8649SZiyue-Zhang /* 363b50f8edeSsinsanction f to vector move 364395c8649SZiyue-Zhang */ 365395c8649SZiyue-Zhang csBundle(0).srcType(0) := SrcType.fp 366395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 367b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 368395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 369395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 370395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 371395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 372395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 373783a1d5fSlewislzh csBundle(0).vpu.isReverse := false.B 374395c8649SZiyue-Zhang /* 375395c8649SZiyue-Zhang LMUL 376395c8649SZiyue-Zhang */ 377684d7aceSxiaofeibao-xjtu for (i <- 0 until MAX_VLMUL) { 378395c8649SZiyue-Zhang csBundle(i + 1).srcType(0) := SrcType.vp 379395c8649SZiyue-Zhang csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 380395c8649SZiyue-Zhang csBundle(i + 1).lsrc(1) := src2 + i.U 381395c8649SZiyue-Zhang csBundle(i + 1).lsrc(2) := dest + i.U 382395c8649SZiyue-Zhang csBundle(i + 1).ldest := dest + i.U 383395c8649SZiyue-Zhang csBundle(i + 1).uopIdx := i.U 384684d7aceSxiaofeibao-xjtu } 385684d7aceSxiaofeibao-xjtu } 38617ec87f2SXuan Hu is(UopSplitType.VEC_EXT2) { 387d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 388d91483a6Sfdy csBundle(2 * i).lsrc(1) := src2 + i.U 389d91483a6Sfdy csBundle(2 * i).lsrc(2) := dest + (2 * i).U 390d91483a6Sfdy csBundle(2 * i).ldest := dest + (2 * i).U 391d91483a6Sfdy csBundle(2 * i).uopIdx := (2 * i).U 392d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + i.U 393d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 394d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 395d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 396d91483a6Sfdy } 397d91483a6Sfdy } 39817ec87f2SXuan Hu is(UopSplitType.VEC_EXT4) { 399d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 4) { 400d91483a6Sfdy csBundle(4 * i).lsrc(1) := src2 + i.U 401d91483a6Sfdy csBundle(4 * i).lsrc(2) := dest + (4 * i).U 402d91483a6Sfdy csBundle(4 * i).ldest := dest + (4 * i).U 403d91483a6Sfdy csBundle(4 * i).uopIdx := (4 * i).U 404d91483a6Sfdy csBundle(4 * i + 1).lsrc(1) := src2 + i.U 405d91483a6Sfdy csBundle(4 * i + 1).lsrc(2) := dest + (4 * i + 1).U 406d91483a6Sfdy csBundle(4 * i + 1).ldest := dest + (4 * i + 1).U 407d91483a6Sfdy csBundle(4 * i + 1).uopIdx := (4 * i + 1).U 408d91483a6Sfdy csBundle(4 * i + 2).lsrc(1) := src2 + i.U 409d91483a6Sfdy csBundle(4 * i + 2).lsrc(2) := dest + (4 * i + 2).U 410d91483a6Sfdy csBundle(4 * i + 2).ldest := dest + (4 * i + 2).U 411d91483a6Sfdy csBundle(4 * i + 2).uopIdx := (4 * i + 2).U 412d91483a6Sfdy csBundle(4 * i + 3).lsrc(1) := src2 + i.U 413d91483a6Sfdy csBundle(4 * i + 3).lsrc(2) := dest + (4 * i + 3).U 414d91483a6Sfdy csBundle(4 * i + 3).ldest := dest + (4 * i + 3).U 415d91483a6Sfdy csBundle(4 * i + 3).uopIdx := (4 * i + 3).U 416d91483a6Sfdy } 417d91483a6Sfdy } 41817ec87f2SXuan Hu is(UopSplitType.VEC_EXT8) { 419d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 420d91483a6Sfdy csBundle(i).lsrc(1) := src2 421d91483a6Sfdy csBundle(i).lsrc(2) := dest + i.U 422d91483a6Sfdy csBundle(i).ldest := dest + i.U 423d91483a6Sfdy csBundle(i).uopIdx := i.U 424d91483a6Sfdy } 425d91483a6Sfdy } 42617ec87f2SXuan Hu is(UopSplitType.VEC_0XV) { 427d91483a6Sfdy /* 428395c8649SZiyue-Zhang i/f to vector move 429d91483a6Sfdy */ 430395c8649SZiyue-Zhang csBundle(0).srcType(0) := Mux(src1IsFp, SrcType.fp, SrcType.reg) 431d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 432b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 433d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 4347c67deccSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 435395c8649SZiyue-Zhang csBundle(0).fuType := Mux(src1IsFp, FuType.f2v.U, FuType.i2v.U) 436395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(Mux(src1IsFp, IF2VectorType.fDup2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 437d91483a6Sfdy csBundle(0).rfWen := false.B 4387c67deccSZiyue Zhang csBundle(0).fpWen := false.B 4397c67deccSZiyue Zhang csBundle(0).vecWen := true.B 440d91483a6Sfdy /* 4417c67deccSZiyue Zhang vmv.s.x 442d91483a6Sfdy */ 4437c67deccSZiyue Zhang csBundle(1).srcType(0) := SrcType.vp 4447c67deccSZiyue Zhang csBundle(1).srcType(1) := SrcType.imm 445d91483a6Sfdy csBundle(1).srcType(2) := SrcType.vp 4467c67deccSZiyue Zhang csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 447d91483a6Sfdy csBundle(1).lsrc(1) := 0.U 448d91483a6Sfdy csBundle(1).lsrc(2) := dest 449d91483a6Sfdy csBundle(1).ldest := dest 450d91483a6Sfdy csBundle(1).rfWen := false.B 451d91483a6Sfdy csBundle(1).fpWen := false.B 452d91483a6Sfdy csBundle(1).vecWen := true.B 4537c67deccSZiyue Zhang csBundle(1).uopIdx := 0.U 454d91483a6Sfdy } 45517ec87f2SXuan Hu is(UopSplitType.VEC_VXV) { 456d91483a6Sfdy /* 457d6059658SZiyue Zhang i to vector move 458d91483a6Sfdy */ 459e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 460d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 461b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 462d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 463fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 464fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 465b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 466fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 467783a1d5fSlewislzh csBundle(0).vpu.isReverse := false.B 468fc85f18fSZiyue Zhang /* 469fc85f18fSZiyue Zhang LMUL 470fc85f18fSZiyue Zhang */ 471fc85f18fSZiyue Zhang for (i <- 0 until MAX_VLMUL) { 472fc85f18fSZiyue Zhang csBundle(i + 1).srcType(0) := SrcType.vp 473fc85f18fSZiyue Zhang csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 474d91483a6Sfdy csBundle(i + 1).lsrc(1) := src2 + i.U 475d91483a6Sfdy csBundle(i + 1).lsrc(2) := dest + i.U 476d91483a6Sfdy csBundle(i + 1).ldest := dest + i.U 477d91483a6Sfdy csBundle(i + 1).uopIdx := i.U 478d91483a6Sfdy } 479d91483a6Sfdy } 48017ec87f2SXuan Hu is(UopSplitType.VEC_VVW) { 481d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 482d91483a6Sfdy csBundle(2 * i).lsrc(0) := src1 + i.U 483d91483a6Sfdy csBundle(2 * i).lsrc(1) := src2 + i.U 484d91483a6Sfdy csBundle(2 * i).lsrc(2) := dest + (2 * i).U 485d91483a6Sfdy csBundle(2 * i).ldest := dest + (2 * i).U 486d91483a6Sfdy csBundle(2 * i).uopIdx := (2 * i).U 487d91483a6Sfdy csBundle(2 * i + 1).lsrc(0) := src1 + i.U 488d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + i.U 489d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 490d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 491d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 492d91483a6Sfdy } 493d91483a6Sfdy } 4943748ec56Sxiaofeibao-xjtu is(UopSplitType.VEC_VFW) { 495395c8649SZiyue-Zhang /* 496395c8649SZiyue-Zhang f to vector move 497395c8649SZiyue-Zhang */ 498395c8649SZiyue-Zhang csBundle(0).srcType(0) := SrcType.fp 499395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 500b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 501395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 502395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 503395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 504395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 505395c8649SZiyue-Zhang csBundle(0).rfWen := false.B 506395c8649SZiyue-Zhang csBundle(0).fpWen := false.B 507395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 508395c8649SZiyue-Zhang 5093748ec56Sxiaofeibao-xjtu for (i <- 0 until MAX_VLMUL / 2) { 510395c8649SZiyue-Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 511395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 5123748ec56Sxiaofeibao-xjtu csBundle(2 * i + 1).lsrc(1) := src2 + i.U 513395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 514395c8649SZiyue-Zhang csBundle(2 * i + 1).ldest := dest + (2 * i).U 515395c8649SZiyue-Zhang csBundle(2 * i + 1).uopIdx := (2 * i).U 516395c8649SZiyue-Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 517395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 518395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(1) := src2 + i.U 519395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 520395c8649SZiyue-Zhang csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 521395c8649SZiyue-Zhang csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 5223748ec56Sxiaofeibao-xjtu } 5233748ec56Sxiaofeibao-xjtu } 52417ec87f2SXuan Hu is(UopSplitType.VEC_WVW) { 525d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 526d91483a6Sfdy csBundle(2 * i).lsrc(0) := src1 + i.U 527d91483a6Sfdy csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 528d91483a6Sfdy csBundle(2 * i).lsrc(2) := dest + (2 * i).U 529d91483a6Sfdy csBundle(2 * i).ldest := dest + (2 * i).U 530d91483a6Sfdy csBundle(2 * i).uopIdx := (2 * i).U 531d91483a6Sfdy csBundle(2 * i + 1).lsrc(0) := src1 + i.U 532d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 533d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + (2 * i + 1).U 534d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + (2 * i + 1).U 535d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 536d91483a6Sfdy } 537d91483a6Sfdy } 53817ec87f2SXuan Hu is(UopSplitType.VEC_VXW) { 539d91483a6Sfdy /* 540d6059658SZiyue Zhang i to vector move 541d91483a6Sfdy */ 5424c8a449fSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 543d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 544b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 545d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 546fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 547fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 5484c8a449fSZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 549fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 550d91483a6Sfdy 551d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 552fc85f18fSZiyue Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 553fc85f18fSZiyue Zhang csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 554d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + i.U 555d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 556d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + (2 * i).U 557d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i).U 558fc85f18fSZiyue Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 559fc85f18fSZiyue Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 560d91483a6Sfdy csBundle(2 * i + 2).lsrc(1) := src2 + i.U 561d91483a6Sfdy csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 562d91483a6Sfdy csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 563d91483a6Sfdy csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 564d91483a6Sfdy } 565d91483a6Sfdy } 56617ec87f2SXuan Hu is(UopSplitType.VEC_WXW) { 567d91483a6Sfdy /* 568d6059658SZiyue Zhang i to vector move 569d91483a6Sfdy */ 570d91483a6Sfdy csBundle(0).srcType(0) := SrcType.reg 571d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 572b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 573d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 574fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 575fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 576b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 577fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 578d91483a6Sfdy 579d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 580fc85f18fSZiyue Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 581fc85f18fSZiyue Zhang csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 582d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 583d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 584d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + (2 * i).U 585d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i).U 586fc85f18fSZiyue Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 587fc85f18fSZiyue Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 588d91483a6Sfdy csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 589d91483a6Sfdy csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 590d91483a6Sfdy csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 591d91483a6Sfdy csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 592d91483a6Sfdy } 593d91483a6Sfdy } 59417ec87f2SXuan Hu is(UopSplitType.VEC_WVV) { 595d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 596d91483a6Sfdy 597d91483a6Sfdy csBundle(2 * i).lsrc(0) := src1 + i.U 598d91483a6Sfdy csBundle(2 * i).lsrc(1) := src2 + (2 * i).U 599d91483a6Sfdy csBundle(2 * i).lsrc(2) := dest + i.U 600d6f9198fSXuan Hu csBundle(2 * i).ldest := dest + i.U 601d91483a6Sfdy csBundle(2 * i).uopIdx := (2 * i).U 602d91483a6Sfdy csBundle(2 * i + 1).lsrc(0) := src1 + i.U 603d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i + 1).U 604d6f9198fSXuan Hu csBundle(2 * i + 1).lsrc(2) := dest + i.U 605d91483a6Sfdy csBundle(2 * i + 1).ldest := dest + i.U 606d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i + 1).U 607d91483a6Sfdy } 608d91483a6Sfdy } 6093748ec56Sxiaofeibao-xjtu is(UopSplitType.VEC_WFW) { 610395c8649SZiyue-Zhang /* 611395c8649SZiyue-Zhang f to vector move 612395c8649SZiyue-Zhang */ 613395c8649SZiyue-Zhang csBundle(0).srcType(0) := SrcType.fp 614395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 615b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 616395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 617395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 618395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 619395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 620395c8649SZiyue-Zhang csBundle(0).rfWen := false.B 621395c8649SZiyue-Zhang csBundle(0).fpWen := false.B 622395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 623395c8649SZiyue-Zhang 6243748ec56Sxiaofeibao-xjtu for (i <- 0 until MAX_VLMUL / 2) { 625395c8649SZiyue-Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 626395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 627395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 628395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(2) := dest + (2 * i).U 629395c8649SZiyue-Zhang csBundle(2 * i + 1).ldest := dest + (2 * i).U 630395c8649SZiyue-Zhang csBundle(2 * i + 1).uopIdx := (2 * i).U 631395c8649SZiyue-Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 632395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 633395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 634395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(2) := dest + (2 * i + 1).U 635395c8649SZiyue-Zhang csBundle(2 * i + 2).ldest := dest + (2 * i + 1).U 636395c8649SZiyue-Zhang csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 6373748ec56Sxiaofeibao-xjtu } 6383748ec56Sxiaofeibao-xjtu } 63917ec87f2SXuan Hu is(UopSplitType.VEC_WXV) { 640d91483a6Sfdy /* 641d6059658SZiyue Zhang i to vector move 642d91483a6Sfdy */ 643e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 644d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 645b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 646d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 647fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 648fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 649b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 650fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 651d91483a6Sfdy 652d91483a6Sfdy for (i <- 0 until MAX_VLMUL / 2) { 653fc85f18fSZiyue Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 654fc85f18fSZiyue Zhang csBundle(2 * i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 655d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + (2 * i).U 656d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + i.U 657d6f9198fSXuan Hu csBundle(2 * i + 1).ldest := dest + i.U 658d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i).U 659fc85f18fSZiyue Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 660fc85f18fSZiyue Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 661d91483a6Sfdy csBundle(2 * i + 2).lsrc(1) := src2 + (2 * i + 1).U 662d6f9198fSXuan Hu csBundle(2 * i + 2).lsrc(2) := dest + i.U 663d91483a6Sfdy csBundle(2 * i + 2).ldest := dest + i.U 664d91483a6Sfdy csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 665d91483a6Sfdy } 666d91483a6Sfdy } 66717ec87f2SXuan Hu is(UopSplitType.VEC_VVM) { 668d91483a6Sfdy csBundle(0).lsrc(2) := dest 669d6f9198fSXuan Hu csBundle(0).ldest := dest 670d91483a6Sfdy csBundle(0).uopIdx := 0.U 671d91483a6Sfdy for (i <- 1 until MAX_VLMUL) { 672d91483a6Sfdy csBundle(i).lsrc(0) := src1 + i.U 673d91483a6Sfdy csBundle(i).lsrc(1) := src2 + i.U 674d6f9198fSXuan Hu csBundle(i).lsrc(2) := dest 675d6f9198fSXuan Hu csBundle(i).ldest := dest 676d91483a6Sfdy csBundle(i).uopIdx := i.U 677d91483a6Sfdy } 678d91483a6Sfdy } 679f06d6d60Sxiaofeibao-xjtu is(UopSplitType.VEC_VFM) { 680395c8649SZiyue-Zhang /* 681395c8649SZiyue-Zhang f to vector move 682395c8649SZiyue-Zhang */ 683395c8649SZiyue-Zhang csBundle(0).srcType(0) := SrcType.fp 684395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 685b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 686395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 687395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 688395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 689395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 690395c8649SZiyue-Zhang csBundle(0).rfWen := false.B 691395c8649SZiyue-Zhang csBundle(0).fpWen := false.B 692395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 693395c8649SZiyue-Zhang //LMUL 694395c8649SZiyue-Zhang csBundle(1).srcType(0) := SrcType.vp 695395c8649SZiyue-Zhang csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 696395c8649SZiyue-Zhang csBundle(1).lsrc(2) := dest 697395c8649SZiyue-Zhang csBundle(1).ldest := dest 698395c8649SZiyue-Zhang csBundle(1).uopIdx := 0.U 699f06d6d60Sxiaofeibao-xjtu for (i <- 1 until MAX_VLMUL) { 700395c8649SZiyue-Zhang csBundle(i + 1).srcType(0) := SrcType.vp 701395c8649SZiyue-Zhang csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 702395c8649SZiyue-Zhang csBundle(i + 1).lsrc(1) := src2 + i.U 703395c8649SZiyue-Zhang csBundle(i + 1).lsrc(2) := dest 704395c8649SZiyue-Zhang csBundle(i + 1).ldest := dest 705395c8649SZiyue-Zhang csBundle(i + 1).uopIdx := i.U 706f06d6d60Sxiaofeibao-xjtu } 707f06d6d60Sxiaofeibao-xjtu csBundle(numOfUop - 1.U).ldest := dest 708f06d6d60Sxiaofeibao-xjtu } 70917ec87f2SXuan Hu is(UopSplitType.VEC_VXM) { 710d91483a6Sfdy /* 711d6059658SZiyue Zhang i to vector move 712d91483a6Sfdy */ 713e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 714d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 715b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 716d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 717fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 718fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 719b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.immDup2Vec(2, 0), IF2VectorType.iDup2Vec(2, 0)), vsewReg) 720fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 721d91483a6Sfdy //LMUL 722fc85f18fSZiyue Zhang csBundle(1).srcType(0) := SrcType.vp 723fc85f18fSZiyue Zhang csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 724d91483a6Sfdy csBundle(1).lsrc(2) := dest 725d6f9198fSXuan Hu csBundle(1).ldest := dest 726d91483a6Sfdy csBundle(1).uopIdx := 0.U 727d91483a6Sfdy for (i <- 1 until MAX_VLMUL) { 728fc85f18fSZiyue Zhang csBundle(i + 1).srcType(0) := SrcType.vp 729fc85f18fSZiyue Zhang csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 730d91483a6Sfdy csBundle(i + 1).lsrc(1) := src2 + i.U 731d6f9198fSXuan Hu csBundle(i + 1).lsrc(2) := dest 732d6f9198fSXuan Hu csBundle(i + 1).ldest := dest 733d91483a6Sfdy csBundle(i + 1).uopIdx := i.U 734d91483a6Sfdy } 735d91483a6Sfdy csBundle(numOfUop - 1.U).ldest := dest 736d91483a6Sfdy } 73717ec87f2SXuan Hu is(UopSplitType.VEC_SLIDE1UP) { 738d91483a6Sfdy /* 739d6059658SZiyue Zhang i to vector move 740d91483a6Sfdy */ 741d91483a6Sfdy csBundle(0).srcType(0) := SrcType.reg 742d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 743b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 744d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 745fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 746fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 747b8505463SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 748fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 749d91483a6Sfdy //LMUL 750fc85f18fSZiyue Zhang csBundle(1).srcType(0) := SrcType.vp 751fc85f18fSZiyue Zhang csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 752d91483a6Sfdy csBundle(1).lsrc(2) := dest 753d91483a6Sfdy csBundle(1).ldest := dest 754d91483a6Sfdy csBundle(1).uopIdx := 0.U 755d91483a6Sfdy for (i <- 1 until MAX_VLMUL) { 756d91483a6Sfdy csBundle(i + 1).srcType(0) := SrcType.vp 757d91483a6Sfdy csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 758d91483a6Sfdy csBundle(i + 1).lsrc(1) := src2 + i.U 759d91483a6Sfdy csBundle(i + 1).lsrc(2) := dest + i.U 760d91483a6Sfdy csBundle(i + 1).ldest := dest + i.U 761d91483a6Sfdy csBundle(i + 1).uopIdx := i.U 762d91483a6Sfdy } 763d91483a6Sfdy } 76417ec87f2SXuan Hu is(UopSplitType.VEC_FSLIDE1UP) { 765395c8649SZiyue-Zhang /* 766b50f8edeSsinsanction f to vector move 767395c8649SZiyue-Zhang */ 768d91483a6Sfdy csBundle(0).srcType(0) := SrcType.fp 769395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 770b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 771395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 772395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 773395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 774395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 775395c8649SZiyue-Zhang csBundle(0).rfWen := false.B 776395c8649SZiyue-Zhang csBundle(0).fpWen := false.B 777395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 778395c8649SZiyue-Zhang //LMUL 779395c8649SZiyue-Zhang csBundle(1).srcType(0) := SrcType.vp 780395c8649SZiyue-Zhang csBundle(1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 781395c8649SZiyue-Zhang csBundle(1).lsrc(1) := src2 782395c8649SZiyue-Zhang csBundle(1).lsrc(2) := dest 783395c8649SZiyue-Zhang csBundle(1).ldest := dest 784395c8649SZiyue-Zhang csBundle(1).uopIdx := 0.U 785d91483a6Sfdy for (i <- 1 until MAX_VLMUL) { 786395c8649SZiyue-Zhang csBundle(i + 1).srcType(0) := SrcType.vp 787395c8649SZiyue-Zhang csBundle(i + 1).lsrc(0) := src2 + (i - 1).U 788395c8649SZiyue-Zhang csBundle(i + 1).lsrc(1) := src2 + i.U 789395c8649SZiyue-Zhang csBundle(i + 1).lsrc(2) := dest + i.U 790395c8649SZiyue-Zhang csBundle(i + 1).ldest := dest + i.U 791395c8649SZiyue-Zhang csBundle(i + 1).uopIdx := i.U 792d91483a6Sfdy } 793d91483a6Sfdy } 79417ec87f2SXuan Hu is(UopSplitType.VEC_SLIDE1DOWN) { // lmul+lmul = 16 795d91483a6Sfdy /* 796d6059658SZiyue Zhang i to vector move 797d91483a6Sfdy */ 798d91483a6Sfdy csBundle(0).srcType(0) := SrcType.reg 799d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 800b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 801d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 802fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 803fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 804b8505463SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.iDup2Vec(2, 0), vsewReg) 805fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 806d91483a6Sfdy //LMUL 807d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 808d91483a6Sfdy csBundle(2 * i + 1).srcType(0) := SrcType.vp 809d91483a6Sfdy csBundle(2 * i + 1).srcType(1) := SrcType.vp 810d91483a6Sfdy csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 811d91483a6Sfdy csBundle(2 * i + 1).lsrc(1) := src2 + i.U 812d91483a6Sfdy csBundle(2 * i + 1).lsrc(2) := dest + i.U 813fc85f18fSZiyue Zhang csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 814d91483a6Sfdy csBundle(2 * i + 1).uopIdx := (2 * i).U 815d91483a6Sfdy if (2 * i + 2 < MAX_VLMUL * 2) { 816fc85f18fSZiyue Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 817fc85f18fSZiyue Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 818d91483a6Sfdy // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 819fc85f18fSZiyue Zhang csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 820d91483a6Sfdy csBundle(2 * i + 2).ldest := dest + i.U 821d91483a6Sfdy csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 822d91483a6Sfdy } 823d91483a6Sfdy } 8248cbcda9aSZiyue Zhang csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 8258cbcda9aSZiyue Zhang csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 826d91483a6Sfdy csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 827d91483a6Sfdy } 82817ec87f2SXuan Hu is(UopSplitType.VEC_FSLIDE1DOWN) { 829395c8649SZiyue-Zhang /* 830b50f8edeSsinsanction f to vector move 831395c8649SZiyue-Zhang */ 832395c8649SZiyue-Zhang csBundle(0).srcType(0) := SrcType.fp 833395c8649SZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 834b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 835395c8649SZiyue-Zhang csBundle(0).lsrc(1) := 0.U 836395c8649SZiyue-Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 837395c8649SZiyue-Zhang csBundle(0).fuType := FuType.f2v.U 838395c8649SZiyue-Zhang csBundle(0).fuOpType := Cat(IF2VectorType.fDup2Vec(2, 0), vsewReg) 839395c8649SZiyue-Zhang csBundle(0).rfWen := false.B 840395c8649SZiyue-Zhang csBundle(0).fpWen := false.B 841395c8649SZiyue-Zhang csBundle(0).vecWen := true.B 842d91483a6Sfdy //LMUL 843d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 844395c8649SZiyue-Zhang csBundle(2 * i + 1).srcType(0) := SrcType.vp 845395c8649SZiyue-Zhang csBundle(2 * i + 1).srcType(1) := SrcType.vp 846395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(0) := src2 + (i + 1).U 847395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(1) := src2 + i.U 848395c8649SZiyue-Zhang csBundle(2 * i + 1).lsrc(2) := dest + i.U 849395c8649SZiyue-Zhang csBundle(2 * i + 1).ldest := VECTOR_TMP_REG_LMUL.U + 1.U 850395c8649SZiyue-Zhang csBundle(2 * i + 1).uopIdx := (2 * i).U 851395c8649SZiyue-Zhang if (2 * i + 2 < MAX_VLMUL * 2) { 852395c8649SZiyue-Zhang csBundle(2 * i + 2).srcType(0) := SrcType.vp 853395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 854395c8649SZiyue-Zhang // csBundle(2 * i + 2).lsrc(1) := src2 + i.U // DontCare 855395c8649SZiyue-Zhang csBundle(2 * i + 2).lsrc(2) := VECTOR_TMP_REG_LMUL.U + 1.U 856395c8649SZiyue-Zhang csBundle(2 * i + 2).ldest := dest + i.U 857395c8649SZiyue-Zhang csBundle(2 * i + 2).uopIdx := (2 * i + 1).U 858d91483a6Sfdy } 859395c8649SZiyue-Zhang } 860395c8649SZiyue-Zhang csBundle(numOfUop - 1.U).srcType(0) := SrcType.vp 861395c8649SZiyue-Zhang csBundle(numOfUop - 1.U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 862d91483a6Sfdy csBundle(numOfUop - 1.U).ldest := dest + lmul - 1.U 863d91483a6Sfdy } 86417ec87f2SXuan Hu is(UopSplitType.VEC_VRED) { 865aaa08c5aSxiaofeibao-xjtu when(vlmulReg === "b001".U) { 866d91483a6Sfdy csBundle(0).srcType(2) := SrcType.DC 867d91483a6Sfdy csBundle(0).lsrc(0) := src2 + 1.U 868d91483a6Sfdy csBundle(0).lsrc(1) := src2 869d91483a6Sfdy csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 870d91483a6Sfdy csBundle(0).uopIdx := 0.U 871d91483a6Sfdy } 872aaa08c5aSxiaofeibao-xjtu when(vlmulReg === "b010".U) { 873d91483a6Sfdy csBundle(0).srcType(2) := SrcType.DC 874d91483a6Sfdy csBundle(0).lsrc(0) := src2 + 1.U 875d91483a6Sfdy csBundle(0).lsrc(1) := src2 876d91483a6Sfdy csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 877d91483a6Sfdy csBundle(0).uopIdx := 0.U 878d91483a6Sfdy 879d91483a6Sfdy csBundle(1).srcType(2) := SrcType.DC 880d91483a6Sfdy csBundle(1).lsrc(0) := src2 + 3.U 881d91483a6Sfdy csBundle(1).lsrc(1) := src2 + 2.U 882d91483a6Sfdy csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 883d91483a6Sfdy csBundle(1).uopIdx := 1.U 884d91483a6Sfdy 885d91483a6Sfdy csBundle(2).srcType(2) := SrcType.DC 886d91483a6Sfdy csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 887d91483a6Sfdy csBundle(2).lsrc(1) := VECTOR_TMP_REG_LMUL.U 888d91483a6Sfdy csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 889d91483a6Sfdy csBundle(2).uopIdx := 2.U 890d91483a6Sfdy } 891aaa08c5aSxiaofeibao-xjtu when(vlmulReg === "b011".U) { 892d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 893d91483a6Sfdy if (i < MAX_VLMUL - MAX_VLMUL / 2) { 894d91483a6Sfdy csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 895d91483a6Sfdy csBundle(i).lsrc(1) := src2 + (i * 2).U 896d91483a6Sfdy csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 897d91483a6Sfdy } else if (i < MAX_VLMUL - MAX_VLMUL / 4) { 898d91483a6Sfdy csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2 + 1).U 899d91483a6Sfdy csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - MAX_VLMUL / 2) * 2).U 900d91483a6Sfdy csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 901d91483a6Sfdy } else if (i < MAX_VLMUL - MAX_VLMUL / 8) { 902d91483a6Sfdy csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 903d91483a6Sfdy csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 904d91483a6Sfdy csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 905d91483a6Sfdy } 906d91483a6Sfdy csBundle(i).srcType(2) := SrcType.DC 907d91483a6Sfdy csBundle(i).uopIdx := i.U 908d91483a6Sfdy } 909d91483a6Sfdy } 910caa15984SZiyue Zhang when(vlmulReg(2) === 0.U && vlmulReg(1, 0).orR) { 911caa15984SZiyue Zhang /* 912caa15984SZiyue Zhang * 2 <= vlmul <= 8 913caa15984SZiyue Zhang */ 914d91483a6Sfdy csBundle(numOfUop - 1.U).srcType(2) := SrcType.vp 915d91483a6Sfdy csBundle(numOfUop - 1.U).lsrc(0) := src1 916d91483a6Sfdy csBundle(numOfUop - 1.U).lsrc(1) := VECTOR_TMP_REG_LMUL.U + numOfUop - 2.U 917d91483a6Sfdy csBundle(numOfUop - 1.U).lsrc(2) := dest 918d91483a6Sfdy csBundle(numOfUop - 1.U).ldest := dest 919d91483a6Sfdy csBundle(numOfUop - 1.U).uopIdx := numOfUop - 1.U 920d91483a6Sfdy } 921d91483a6Sfdy } 922582849ffSxiaofeibao-xjtu is(UopSplitType.VEC_VFRED) { 923aaa08c5aSxiaofeibao-xjtu val vlmul = vlmulReg 924aaa08c5aSxiaofeibao-xjtu val vsew = vsewReg 925582849ffSxiaofeibao-xjtu when(vlmul === VLmul.m8){ 926582849ffSxiaofeibao-xjtu for (i <- 0 until 4) { 927582849ffSxiaofeibao-xjtu csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 928582849ffSxiaofeibao-xjtu csBundle(i).lsrc(1) := src2 + (i * 2).U 929582849ffSxiaofeibao-xjtu csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 930582849ffSxiaofeibao-xjtu csBundle(i).uopIdx := i.U 931582849ffSxiaofeibao-xjtu } 932582849ffSxiaofeibao-xjtu for (i <- 4 until 6) { 933582849ffSxiaofeibao-xjtu csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2 + 1).U 934582849ffSxiaofeibao-xjtu csBundle(i).lsrc(1) := (VECTOR_TMP_REG_LMUL + (i - 4) * 2).U 935582849ffSxiaofeibao-xjtu csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 936582849ffSxiaofeibao-xjtu csBundle(i).uopIdx := i.U 937582849ffSxiaofeibao-xjtu } 938582849ffSxiaofeibao-xjtu csBundle(6).lsrc(0) := (VECTOR_TMP_REG_LMUL + 5).U 939582849ffSxiaofeibao-xjtu csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 940582849ffSxiaofeibao-xjtu csBundle(6).ldest := (VECTOR_TMP_REG_LMUL + 6).U 941582849ffSxiaofeibao-xjtu csBundle(6).uopIdx := 6.U 942582849ffSxiaofeibao-xjtu when(vsew === VSew.e64) { 943582849ffSxiaofeibao-xjtu csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 944582849ffSxiaofeibao-xjtu csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 945582849ffSxiaofeibao-xjtu csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 946582849ffSxiaofeibao-xjtu csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 947582849ffSxiaofeibao-xjtu csBundle(7).uopIdx := 7.U 948582849ffSxiaofeibao-xjtu csBundle(8).lsrc(0) := src1 949582849ffSxiaofeibao-xjtu csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 950582849ffSxiaofeibao-xjtu csBundle(8).ldest := dest 951582849ffSxiaofeibao-xjtu csBundle(8).uopIdx := 8.U 952582849ffSxiaofeibao-xjtu } 953582849ffSxiaofeibao-xjtu when(vsew === VSew.e32) { 954582849ffSxiaofeibao-xjtu csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 955582849ffSxiaofeibao-xjtu csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 956582849ffSxiaofeibao-xjtu csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 957582849ffSxiaofeibao-xjtu csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 958582849ffSxiaofeibao-xjtu csBundle(7).uopIdx := 7.U 959582849ffSxiaofeibao-xjtu csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 960582849ffSxiaofeibao-xjtu csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 961582849ffSxiaofeibao-xjtu csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 962582849ffSxiaofeibao-xjtu csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 963582849ffSxiaofeibao-xjtu csBundle(8).uopIdx := 8.U 964582849ffSxiaofeibao-xjtu csBundle(9).lsrc(0) := src1 965582849ffSxiaofeibao-xjtu csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 966582849ffSxiaofeibao-xjtu csBundle(9).ldest := dest 967582849ffSxiaofeibao-xjtu csBundle(9).uopIdx := 9.U 968582849ffSxiaofeibao-xjtu } 969582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 970582849ffSxiaofeibao-xjtu csBundle(7).lsrc(0) := (VECTOR_TMP_REG_LMUL + 6).U 971582849ffSxiaofeibao-xjtu csBundle(7).lsrc(1) := (VECTOR_TMP_REG_LMUL + 6).U 972582849ffSxiaofeibao-xjtu csBundle(7).ldest := (VECTOR_TMP_REG_LMUL + 7).U 973582849ffSxiaofeibao-xjtu csBundle(7).vpu.fpu.isFoldTo1_2 := true.B 974582849ffSxiaofeibao-xjtu csBundle(7).uopIdx := 7.U 975582849ffSxiaofeibao-xjtu csBundle(8).lsrc(0) := (VECTOR_TMP_REG_LMUL + 7).U 976582849ffSxiaofeibao-xjtu csBundle(8).lsrc(1) := (VECTOR_TMP_REG_LMUL + 7).U 977582849ffSxiaofeibao-xjtu csBundle(8).ldest := (VECTOR_TMP_REG_LMUL + 8).U 978582849ffSxiaofeibao-xjtu csBundle(8).vpu.fpu.isFoldTo1_4 := true.B 979582849ffSxiaofeibao-xjtu csBundle(8).uopIdx := 8.U 980582849ffSxiaofeibao-xjtu csBundle(9).lsrc(0) := (VECTOR_TMP_REG_LMUL + 8).U 981582849ffSxiaofeibao-xjtu csBundle(9).lsrc(1) := (VECTOR_TMP_REG_LMUL + 8).U 982582849ffSxiaofeibao-xjtu csBundle(9).ldest := (VECTOR_TMP_REG_LMUL + 9).U 983582849ffSxiaofeibao-xjtu csBundle(9).vpu.fpu.isFoldTo1_8 := true.B 984582849ffSxiaofeibao-xjtu csBundle(9).uopIdx := 9.U 985582849ffSxiaofeibao-xjtu csBundle(10).lsrc(0) := src1 986582849ffSxiaofeibao-xjtu csBundle(10).lsrc(1) := (VECTOR_TMP_REG_LMUL + 9).U 987582849ffSxiaofeibao-xjtu csBundle(10).ldest := dest 988582849ffSxiaofeibao-xjtu csBundle(10).uopIdx := 10.U 989582849ffSxiaofeibao-xjtu } 990582849ffSxiaofeibao-xjtu } 991582849ffSxiaofeibao-xjtu when(vlmul === VLmul.m4) { 992582849ffSxiaofeibao-xjtu for (i <- 0 until 2) { 993582849ffSxiaofeibao-xjtu csBundle(i).lsrc(0) := src2 + (i * 2 + 1).U 994582849ffSxiaofeibao-xjtu csBundle(i).lsrc(1) := src2 + (i * 2).U 995582849ffSxiaofeibao-xjtu csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 996582849ffSxiaofeibao-xjtu csBundle(i).uopIdx := i.U 997582849ffSxiaofeibao-xjtu } 998582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 999582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1000582849ffSxiaofeibao-xjtu csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 1001582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1002582849ffSxiaofeibao-xjtu when(vsew === VSew.e64) { 1003582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 1004582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1005582849ffSxiaofeibao-xjtu csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 1006582849ffSxiaofeibao-xjtu csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 1007582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1008582849ffSxiaofeibao-xjtu csBundle(4).lsrc(0) := src1 1009582849ffSxiaofeibao-xjtu csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 1010582849ffSxiaofeibao-xjtu csBundle(4).ldest := dest 1011582849ffSxiaofeibao-xjtu csBundle(4).uopIdx := 4.U 1012582849ffSxiaofeibao-xjtu } 1013582849ffSxiaofeibao-xjtu when(vsew === VSew.e32) { 1014582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 1015582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1016582849ffSxiaofeibao-xjtu csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 1017582849ffSxiaofeibao-xjtu csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 1018582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1019582849ffSxiaofeibao-xjtu csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 1020582849ffSxiaofeibao-xjtu csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 1021582849ffSxiaofeibao-xjtu csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 1022582849ffSxiaofeibao-xjtu csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 1023582849ffSxiaofeibao-xjtu csBundle(4).uopIdx := 4.U 1024582849ffSxiaofeibao-xjtu csBundle(5).lsrc(0) := src1 1025582849ffSxiaofeibao-xjtu csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 1026582849ffSxiaofeibao-xjtu csBundle(5).ldest := dest 1027582849ffSxiaofeibao-xjtu csBundle(5).uopIdx := 5.U 1028582849ffSxiaofeibao-xjtu } 1029582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 1030582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 1031582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1032582849ffSxiaofeibao-xjtu csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 1033582849ffSxiaofeibao-xjtu csBundle(3).vpu.fpu.isFoldTo1_2 := true.B 1034582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1035582849ffSxiaofeibao-xjtu csBundle(4).lsrc(0) := (VECTOR_TMP_REG_LMUL + 3).U 1036582849ffSxiaofeibao-xjtu csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 1037582849ffSxiaofeibao-xjtu csBundle(4).ldest := (VECTOR_TMP_REG_LMUL + 4).U 1038582849ffSxiaofeibao-xjtu csBundle(4).vpu.fpu.isFoldTo1_4 := true.B 1039582849ffSxiaofeibao-xjtu csBundle(4).uopIdx := 4.U 1040582849ffSxiaofeibao-xjtu csBundle(5).lsrc(0) := (VECTOR_TMP_REG_LMUL + 4).U 1041582849ffSxiaofeibao-xjtu csBundle(5).lsrc(1) := (VECTOR_TMP_REG_LMUL + 4).U 1042582849ffSxiaofeibao-xjtu csBundle(5).ldest := (VECTOR_TMP_REG_LMUL + 5).U 1043582849ffSxiaofeibao-xjtu csBundle(5).vpu.fpu.isFoldTo1_8 := true.B 1044582849ffSxiaofeibao-xjtu csBundle(5).uopIdx := 5.U 1045582849ffSxiaofeibao-xjtu csBundle(6).lsrc(0) := src1 1046582849ffSxiaofeibao-xjtu csBundle(6).lsrc(1) := (VECTOR_TMP_REG_LMUL + 5).U 1047582849ffSxiaofeibao-xjtu csBundle(6).ldest := dest 1048582849ffSxiaofeibao-xjtu csBundle(6).uopIdx := 6.U 1049582849ffSxiaofeibao-xjtu } 1050582849ffSxiaofeibao-xjtu } 1051582849ffSxiaofeibao-xjtu when(vlmul === VLmul.m2) { 1052582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 + 1.U 1053582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 + 0.U 1054582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1055582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1056582849ffSxiaofeibao-xjtu when(vsew === VSew.e64) { 1057582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1058582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1059582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1060582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 1061582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1062582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := src1 1063582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1064582849ffSxiaofeibao-xjtu csBundle(2).ldest := dest 1065582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1066582849ffSxiaofeibao-xjtu } 1067582849ffSxiaofeibao-xjtu when(vsew === VSew.e32) { 1068582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1069582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1070582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1071582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 1072582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1073582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 1074582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1075582849ffSxiaofeibao-xjtu csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 1076582849ffSxiaofeibao-xjtu csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 1077582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1078582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := src1 1079582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1080582849ffSxiaofeibao-xjtu csBundle(3).ldest := dest 1081582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1082582849ffSxiaofeibao-xjtu } 1083582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 1084582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1085582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1086582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1087582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_2 := true.B 1088582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1089582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 1090582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1091582849ffSxiaofeibao-xjtu csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 1092582849ffSxiaofeibao-xjtu csBundle(2).vpu.fpu.isFoldTo1_4 := true.B 1093582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1094582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := (VECTOR_TMP_REG_LMUL + 2).U 1095582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1096582849ffSxiaofeibao-xjtu csBundle(3).ldest := (VECTOR_TMP_REG_LMUL + 3).U 1097582849ffSxiaofeibao-xjtu csBundle(3).vpu.fpu.isFoldTo1_8 := true.B 1098582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1099582849ffSxiaofeibao-xjtu csBundle(4).lsrc(0) := src1 1100582849ffSxiaofeibao-xjtu csBundle(4).lsrc(1) := (VECTOR_TMP_REG_LMUL + 3).U 1101582849ffSxiaofeibao-xjtu csBundle(4).ldest := dest 1102582849ffSxiaofeibao-xjtu csBundle(4).uopIdx := 4.U 1103582849ffSxiaofeibao-xjtu } 1104582849ffSxiaofeibao-xjtu } 1105582849ffSxiaofeibao-xjtu when(vlmul === VLmul.m1) { 1106582849ffSxiaofeibao-xjtu when(vsew === VSew.e64) { 1107582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1108582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1109582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1110582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 1111582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1112582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := src1 1113582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1114582849ffSxiaofeibao-xjtu csBundle(1).ldest := dest 1115582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1116582849ffSxiaofeibao-xjtu } 1117582849ffSxiaofeibao-xjtu when(vsew === VSew.e32) { 1118582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1119582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1120582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1121582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 1122582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1123582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1124582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1125582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1126582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 1127582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1128582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := src1 1129582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1130582849ffSxiaofeibao-xjtu csBundle(2).ldest := dest 1131582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1132582849ffSxiaofeibao-xjtu } 1133582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 1134582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1135582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1136582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1137582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_2 := true.B 1138582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1139582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1140582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1141582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1142582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_4 := true.B 1143582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1144582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := (VECTOR_TMP_REG_LMUL + 1).U 1145582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1146582849ffSxiaofeibao-xjtu csBundle(2).ldest := (VECTOR_TMP_REG_LMUL + 2).U 1147582849ffSxiaofeibao-xjtu csBundle(2).vpu.fpu.isFoldTo1_8 := true.B 1148582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1149582849ffSxiaofeibao-xjtu csBundle(3).lsrc(0) := src1 1150582849ffSxiaofeibao-xjtu csBundle(3).lsrc(1) := (VECTOR_TMP_REG_LMUL + 2).U 1151582849ffSxiaofeibao-xjtu csBundle(3).ldest := dest 1152582849ffSxiaofeibao-xjtu csBundle(3).uopIdx := 3.U 1153582849ffSxiaofeibao-xjtu } 1154582849ffSxiaofeibao-xjtu } 1155582849ffSxiaofeibao-xjtu when(vlmul === VLmul.mf2) { 1156582849ffSxiaofeibao-xjtu when(vsew === VSew.e32) { 1157582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1158582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1159582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1160582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 1161582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1162582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := src1 1163582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1164582849ffSxiaofeibao-xjtu csBundle(1).ldest := dest 1165582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1166582849ffSxiaofeibao-xjtu } 1167582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 1168582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1169582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1170582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1171582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_4 := true.B 1172582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1173582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := (VECTOR_TMP_REG_LMUL + 0).U 1174582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1175582849ffSxiaofeibao-xjtu csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1176582849ffSxiaofeibao-xjtu csBundle(1).vpu.fpu.isFoldTo1_8 := true.B 1177582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1178582849ffSxiaofeibao-xjtu csBundle(2).lsrc(0) := src1 1179582849ffSxiaofeibao-xjtu csBundle(2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 1180582849ffSxiaofeibao-xjtu csBundle(2).ldest := dest 1181582849ffSxiaofeibao-xjtu csBundle(2).uopIdx := 2.U 1182582849ffSxiaofeibao-xjtu } 1183582849ffSxiaofeibao-xjtu } 1184582849ffSxiaofeibao-xjtu when(vlmul === VLmul.mf4) { 1185582849ffSxiaofeibao-xjtu when(vsew === VSew.e16) { 1186582849ffSxiaofeibao-xjtu csBundle(0).lsrc(0) := src2 1187582849ffSxiaofeibao-xjtu csBundle(0).lsrc(1) := src2 1188582849ffSxiaofeibao-xjtu csBundle(0).ldest := (VECTOR_TMP_REG_LMUL + 0).U 1189582849ffSxiaofeibao-xjtu csBundle(0).vpu.fpu.isFoldTo1_8 := true.B 1190582849ffSxiaofeibao-xjtu csBundle(0).uopIdx := 0.U 1191582849ffSxiaofeibao-xjtu csBundle(1).lsrc(0) := src1 1192582849ffSxiaofeibao-xjtu csBundle(1).lsrc(1) := (VECTOR_TMP_REG_LMUL + 0).U 1193582849ffSxiaofeibao-xjtu csBundle(1).ldest := dest 1194582849ffSxiaofeibao-xjtu csBundle(1).uopIdx := 1.U 1195582849ffSxiaofeibao-xjtu } 1196582849ffSxiaofeibao-xjtu } 1197582849ffSxiaofeibao-xjtu } 1198d91483a6Sfdy 1199b94b1889Sxiaofeibao-xjtu is(UopSplitType.VEC_VFREDOSUM) { 1200b94b1889Sxiaofeibao-xjtu import yunsuan.VfaluType 1201aaa08c5aSxiaofeibao-xjtu val vlmul = vlmulReg 1202aaa08c5aSxiaofeibao-xjtu val vsew = vsewReg 1203e25c13faSXuan Hu val isWiden = latchedInst.fuOpType === VfaluType.vfwredosum 1204b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.m8) { 1205b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e64) { 1206b94b1889Sxiaofeibao-xjtu val vlmax = 16 1207b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1208b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1209b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1210b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1211b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1212b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1213b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1214b94b1889Sxiaofeibao-xjtu } 1215b94b1889Sxiaofeibao-xjtu } 1216b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e32) { 1217b94b1889Sxiaofeibao-xjtu val vlmax = 32 1218b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1219b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1220b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 12218bbc295cSZiyue Zhang csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1222b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 12238bbc295cSZiyue Zhang csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 12248bbc295cSZiyue Zhang csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1225b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1226b94b1889Sxiaofeibao-xjtu } 1227b94b1889Sxiaofeibao-xjtu } 1228b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1229b94b1889Sxiaofeibao-xjtu val vlmax = 64 1230b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1231b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1232b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 12338bbc295cSZiyue Zhang csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1234b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 12358bbc295cSZiyue Zhang csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 12368bbc295cSZiyue Zhang csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1237b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1238b94b1889Sxiaofeibao-xjtu } 1239b94b1889Sxiaofeibao-xjtu } 1240b94b1889Sxiaofeibao-xjtu } 1241b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.m4) { 1242b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e64) { 1243b94b1889Sxiaofeibao-xjtu val vlmax = 8 1244b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1245b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1246b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1247b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1248b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1249b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1250b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1251b94b1889Sxiaofeibao-xjtu } 1252b94b1889Sxiaofeibao-xjtu } 1253b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e32) { 1254b94b1889Sxiaofeibao-xjtu val vlmax = 16 1255b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1256b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1257b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1258b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1259b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1260b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1261b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1262b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1263b94b1889Sxiaofeibao-xjtu } 1264b94b1889Sxiaofeibao-xjtu } 1265b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1266b94b1889Sxiaofeibao-xjtu val vlmax = 32 1267b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1268b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1269b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1270b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1271b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1272b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1273b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1274b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1275b94b1889Sxiaofeibao-xjtu } 1276b94b1889Sxiaofeibao-xjtu } 1277b94b1889Sxiaofeibao-xjtu } 1278b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.m2) { 1279b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e64) { 1280b94b1889Sxiaofeibao-xjtu val vlmax = 4 1281b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1282b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1283b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1284b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1285b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1286b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1287b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1288b94b1889Sxiaofeibao-xjtu } 1289b94b1889Sxiaofeibao-xjtu } 1290b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e32) { 1291b94b1889Sxiaofeibao-xjtu val vlmax = 8 1292b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1293b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1294b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1295b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1296b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1297b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1298b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1299b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1300b94b1889Sxiaofeibao-xjtu } 1301b94b1889Sxiaofeibao-xjtu } 1302b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1303b94b1889Sxiaofeibao-xjtu val vlmax = 16 1304b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1305b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1306b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1307b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1308b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1309b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1310b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1311b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1312b94b1889Sxiaofeibao-xjtu } 1313b94b1889Sxiaofeibao-xjtu } 1314b94b1889Sxiaofeibao-xjtu } 1315b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.m1) { 1316b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e64) { 1317b94b1889Sxiaofeibao-xjtu val vlmax = 2 1318b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1319b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1320b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 2 == 0) src2 + (i/2).U else VECTOR_TMP_REG_LMUL.U) 1321b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 2 == 0) src2 + (i/2).U else if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1322b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1323b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := (if (i % 2 == 0) false.B else true.B) 1324b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1325b94b1889Sxiaofeibao-xjtu } 1326b94b1889Sxiaofeibao-xjtu } 1327b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e32) { 1328b94b1889Sxiaofeibao-xjtu val vlmax = 4 1329b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1330b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1331b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1332b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1333b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1334b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1335b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1336b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1337b94b1889Sxiaofeibao-xjtu } 1338b94b1889Sxiaofeibao-xjtu } 1339b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1340b94b1889Sxiaofeibao-xjtu val vlmax = 8 1341b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1342b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1343b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1344b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1345b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1346b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1347b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1348b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1349b94b1889Sxiaofeibao-xjtu } 1350b94b1889Sxiaofeibao-xjtu } 1351b94b1889Sxiaofeibao-xjtu } 1352b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.mf2) { 1353b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e32) { 1354b94b1889Sxiaofeibao-xjtu val vlmax = 2 1355b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1356b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1357b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 4 == 0) src2 + (i/4).U else VECTOR_TMP_REG_LMUL.U) 1358b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 4 == 0) src2 + (i/4).U else if (i == vlmax - 1) dest else if (i % 4 == 1) Mux(isWiden, src2 + (i/4).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1359b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1360b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_2 := isWiden && (if (i % 4 == 0) false.B else true.B) 1361b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := !isWiden && (if (i % 4 == 0) false.B else true.B) 1362b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1363b94b1889Sxiaofeibao-xjtu } 1364b94b1889Sxiaofeibao-xjtu } 1365b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1366b94b1889Sxiaofeibao-xjtu val vlmax = 4 1367b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1368b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1369b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1370b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1371b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1372b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1373b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1374b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1375b94b1889Sxiaofeibao-xjtu } 1376b94b1889Sxiaofeibao-xjtu } 1377b94b1889Sxiaofeibao-xjtu } 1378b94b1889Sxiaofeibao-xjtu when(vlmul === VLmul.mf4) { 1379b94b1889Sxiaofeibao-xjtu when(vsew === VSew.e16) { 1380b94b1889Sxiaofeibao-xjtu val vlmax = 2 1381b94b1889Sxiaofeibao-xjtu for (i <- 0 until vlmax) { 1382b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(0) := (if (i == 0) src1 else VECTOR_TMP_REG_LMUL.U) 1383b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(1) := (if (i % 8 == 0) src2 + (i/8).U else VECTOR_TMP_REG_LMUL.U) 1384b94b1889Sxiaofeibao-xjtu csBundle(i).lsrc(2) := (if (i % 8 == 0) src2 + (i/8).U else if (i == vlmax - 1) dest else if (i % 8 == 1) Mux(isWiden, src2 + (i/8).U, VECTOR_TMP_REG_LMUL.U) else VECTOR_TMP_REG_LMUL.U) 1385b94b1889Sxiaofeibao-xjtu csBundle(i).ldest := (if (i == vlmax - 1) dest else VECTOR_TMP_REG_LMUL.U) 1386b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_4 := isWiden && (if (i % 8 == 0) false.B else true.B) 1387b94b1889Sxiaofeibao-xjtu csBundle(i).vpu.fpu.isFoldTo1_8 := !isWiden && (if (i % 8 == 0) false.B else true.B) 1388b94b1889Sxiaofeibao-xjtu csBundle(i).uopIdx := i.U 1389b94b1889Sxiaofeibao-xjtu } 1390b94b1889Sxiaofeibao-xjtu } 1391b94b1889Sxiaofeibao-xjtu } 1392b94b1889Sxiaofeibao-xjtu } 1393d6059658SZiyue Zhang 139417ec87f2SXuan Hu is(UopSplitType.VEC_SLIDEUP) { 1395d6059658SZiyue Zhang // i to vector move 1396e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 1397d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 1398b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 1399d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 1400fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1401fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1402b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1403fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 1404d91483a6Sfdy // LMUL 1405d91483a6Sfdy for (i <- 0 until MAX_VLMUL) 1406d91483a6Sfdy for (j <- 0 to i) { 14074ee69032SzhanglyGit val old_vd = if (j == 0) { 14084ee69032SzhanglyGit dest + i.U 1409fc85f18fSZiyue Zhang } else (VECTOR_TMP_REG_LMUL + j).U 14104ee69032SzhanglyGit val vd = if (j == i) { 14114ee69032SzhanglyGit dest + i.U 1412fc85f18fSZiyue Zhang } else (VECTOR_TMP_REG_LMUL + j + 1).U 1413fc85f18fSZiyue Zhang csBundle(i * (i + 1) / 2 + j + 1).srcType(0) := SrcType.vp 1414fc85f18fSZiyue Zhang csBundle(i * (i + 1) / 2 + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1415d91483a6Sfdy csBundle(i * (i + 1) / 2 + j + 1).lsrc(1) := src2 + j.U 1416d91483a6Sfdy csBundle(i * (i + 1) / 2 + j + 1).lsrc(2) := old_vd 1417d91483a6Sfdy csBundle(i * (i + 1) / 2 + j + 1).ldest := vd 1418d91483a6Sfdy csBundle(i * (i + 1) / 2 + j + 1).uopIdx := (i * (i + 1) / 2 + j).U 1419d91483a6Sfdy } 1420d91483a6Sfdy } 1421d91483a6Sfdy 142217ec87f2SXuan Hu is(UopSplitType.VEC_SLIDEDOWN) { 1423d6059658SZiyue Zhang // i to vector move 1424e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 1425d91483a6Sfdy csBundle(0).srcType(1) := SrcType.imm 1426b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 1427d91483a6Sfdy csBundle(0).lsrc(1) := 0.U 1428fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1429fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1430b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 1431fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 1432d91483a6Sfdy // LMUL 1433d91483a6Sfdy for (i <- 0 until MAX_VLMUL) 1434d91483a6Sfdy for (j <- (0 to i).reverse) { 1435d91483a6Sfdy when(i.U < lmul) { 14364ee69032SzhanglyGit val old_vd = if (j == 0) { 14374ee69032SzhanglyGit dest + lmul - 1.U - i.U 1438fc85f18fSZiyue Zhang } else (VECTOR_TMP_REG_LMUL + j).U 14394ee69032SzhanglyGit val vd = if (j == i) { 14404ee69032SzhanglyGit dest + lmul - 1.U - i.U 1441fc85f18fSZiyue Zhang } else (VECTOR_TMP_REG_LMUL + j + 1).U 1442fc85f18fSZiyue Zhang csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).srcType(0) := SrcType.vp 1443fc85f18fSZiyue Zhang csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1444d91483a6Sfdy csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(1) := src2 + lmul - 1.U - j.U 1445d91483a6Sfdy csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).lsrc(2) := old_vd 1446d91483a6Sfdy csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).ldest := vd 1447d91483a6Sfdy csBundle(numOfUop - (i * (i + 1) / 2 + i - j + 1).U).uopIdx := numOfUop - (i * (i + 1) / 2 + i - j + 2).U 1448d91483a6Sfdy } 1449d91483a6Sfdy } 1450d91483a6Sfdy } 1451d91483a6Sfdy 145217ec87f2SXuan Hu is(UopSplitType.VEC_M0X) { 1453d91483a6Sfdy // LMUL 1454d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 1455d91483a6Sfdy val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1456d91483a6Sfdy val ldest = (VECTOR_TMP_REG_LMUL + i).U 1457d91483a6Sfdy csBundle(i).srcType(0) := srcType0 1458d91483a6Sfdy csBundle(i).srcType(1) := SrcType.vp 1459d91483a6Sfdy csBundle(i).rfWen := false.B 1460cd2c45feSZiyue Zhang csBundle(i).fpWen := false.B 1461d91483a6Sfdy csBundle(i).vecWen := true.B 1462d91483a6Sfdy csBundle(i).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1463d91483a6Sfdy csBundle(i).lsrc(1) := src2 1464d91483a6Sfdy // csBundle(i).lsrc(2) := dest + i.U DontCare 1465d91483a6Sfdy csBundle(i).ldest := ldest 1466d91483a6Sfdy csBundle(i).uopIdx := i.U 1467d91483a6Sfdy } 1468762f2b39SZiyue Zhang csBundle(numOfUop - 1.U).rfWen := Mux(dest === 0.U, false.B, true.B) 1469762f2b39SZiyue Zhang csBundle(numOfUop - 1.U).fpWen := false.B 1470762f2b39SZiyue Zhang csBundle(numOfUop - 1.U).vecWen := false.B 1471762f2b39SZiyue Zhang csBundle(numOfUop - 1.U).ldest := dest 1472d91483a6Sfdy } 1473d91483a6Sfdy 147417ec87f2SXuan Hu is(UopSplitType.VEC_MVV) { 1475d91483a6Sfdy // LMUL 1476d91483a6Sfdy for (i <- 0 until MAX_VLMUL) { 1477d91483a6Sfdy val srcType0 = if (i == 0) SrcType.DC else SrcType.vp 1478d91483a6Sfdy csBundle(i * 2 + 0).srcType(0) := srcType0 1479d91483a6Sfdy csBundle(i * 2 + 0).srcType(1) := SrcType.vp 1480d91483a6Sfdy csBundle(i * 2 + 0).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1481d91483a6Sfdy csBundle(i * 2 + 0).lsrc(1) := src2 1482d91483a6Sfdy csBundle(i * 2 + 0).lsrc(2) := dest + i.U 1483d91483a6Sfdy csBundle(i * 2 + 0).ldest := dest + i.U 1484d91483a6Sfdy csBundle(i * 2 + 0).uopIdx := (i * 2 + 0).U 1485d91483a6Sfdy 1486d91483a6Sfdy csBundle(i * 2 + 1).srcType(0) := srcType0 1487d91483a6Sfdy csBundle(i * 2 + 1).srcType(1) := SrcType.vp 1488d91483a6Sfdy csBundle(i * 2 + 1).lsrc(0) := (VECTOR_TMP_REG_LMUL + i - 1).U 1489d91483a6Sfdy csBundle(i * 2 + 1).lsrc(1) := src2 1490d91483a6Sfdy // csBundle(i).lsrc(2) := dest + i.U DontCare 1491d91483a6Sfdy csBundle(i * 2 + 1).ldest := (VECTOR_TMP_REG_LMUL + i).U 1492d91483a6Sfdy csBundle(i * 2 + 1).uopIdx := (i * 2 + 1).U 1493d91483a6Sfdy } 1494d91483a6Sfdy } 1495189ec863SzhanglyGit is(UopSplitType.VEC_VWW) { 1496189ec863SzhanglyGit for (i <- 0 until MAX_VLMUL*2) { 1497189ec863SzhanglyGit when(i.U < lmul){ 1498189ec863SzhanglyGit csBundle(i).srcType(2) := SrcType.DC 1499189ec863SzhanglyGit csBundle(i).lsrc(0) := src2 + i.U 1500189ec863SzhanglyGit csBundle(i).lsrc(1) := src2 + i.U 1501189ec863SzhanglyGit // csBundle(i).lsrc(2) := dest + (2 * i).U 1502189ec863SzhanglyGit csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1503189ec863SzhanglyGit csBundle(i).uopIdx := i.U 1504189ec863SzhanglyGit } otherwise { 1505189ec863SzhanglyGit csBundle(i).srcType(2) := SrcType.DC 1506189ec863SzhanglyGit csBundle(i).lsrc(0) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) + 1.U 1507189ec863SzhanglyGit csBundle(i).lsrc(1) := VECTOR_TMP_REG_LMUL.U + Cat((i.U-lmul),0.U(1.W)) 1508189ec863SzhanglyGit // csBundle(i).lsrc(2) := dest + (2 * i).U 1509189ec863SzhanglyGit csBundle(i).ldest := (VECTOR_TMP_REG_LMUL + i).U 1510189ec863SzhanglyGit csBundle(i).uopIdx := i.U 1511189ec863SzhanglyGit } 1512189ec863SzhanglyGit csBundle(numOfUop-1.U).srcType(2) := SrcType.vp 1513189ec863SzhanglyGit csBundle(numOfUop-1.U).lsrc(0) := src1 1514189ec863SzhanglyGit csBundle(numOfUop-1.U).lsrc(2) := dest 1515189ec863SzhanglyGit csBundle(numOfUop-1.U).ldest := dest 1516189ec863SzhanglyGit } 1517189ec863SzhanglyGit } 1518189ec863SzhanglyGit is(UopSplitType.VEC_RGATHER) { 1519189ec863SzhanglyGit def genCsBundle_VEC_RGATHER(len:Int): Unit ={ 1520189ec863SzhanglyGit for (i <- 0 until len) 1521189ec863SzhanglyGit for (j <- 0 until len) { 1522189ec863SzhanglyGit // csBundle(i * len + j).srcType(0) := SrcType.vp // SrcType.imm 1523189ec863SzhanglyGit // csBundle(i * len + j).srcType(1) := SrcType.vp 1524189ec863SzhanglyGit // csBundle(i * len + j).srcType(2) := SrcType.vp 1525189ec863SzhanglyGit csBundle(i * len + j).lsrc(0) := src1 + i.U 1526189ec863SzhanglyGit csBundle(i * len + j).lsrc(1) := src2 + j.U 1527189ec863SzhanglyGit val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j - 1).U 1528189ec863SzhanglyGit csBundle(i * len + j).lsrc(2) := vd_old 1529189ec863SzhanglyGit val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1530189ec863SzhanglyGit csBundle(i * len + j).ldest := vd 1531189ec863SzhanglyGit csBundle(i * len + j).uopIdx := (i * len + j).U 1532189ec863SzhanglyGit } 1533189ec863SzhanglyGit } 1534aaa08c5aSxiaofeibao-xjtu switch(vlmulReg) { 1535189ec863SzhanglyGit is("b001".U ){ 1536189ec863SzhanglyGit genCsBundle_VEC_RGATHER(2) 1537189ec863SzhanglyGit } 1538189ec863SzhanglyGit is("b010".U ){ 1539189ec863SzhanglyGit genCsBundle_VEC_RGATHER(4) 1540189ec863SzhanglyGit } 1541189ec863SzhanglyGit is("b011".U ){ 1542189ec863SzhanglyGit genCsBundle_VEC_RGATHER(8) 1543189ec863SzhanglyGit } 1544189ec863SzhanglyGit } 1545189ec863SzhanglyGit } 1546189ec863SzhanglyGit is(UopSplitType.VEC_RGATHER_VX) { 1547189ec863SzhanglyGit def genCsBundle_RGATHER_VX(len:Int): Unit ={ 1548189ec863SzhanglyGit for (i <- 0 until len) 1549189ec863SzhanglyGit for (j <- 0 until len) { 1550fc85f18fSZiyue Zhang csBundle(i * len + j + 1).srcType(0) := SrcType.vp 1551189ec863SzhanglyGit // csBundle(i * len + j + 1).srcType(1) := SrcType.vp 1552189ec863SzhanglyGit // csBundle(i * len + j + 1).srcType(2) := SrcType.vp 1553fc85f18fSZiyue Zhang csBundle(i * len + j + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1554189ec863SzhanglyGit csBundle(i * len + j + 1).lsrc(1) := src2 + j.U 1555fc85f18fSZiyue Zhang val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1556189ec863SzhanglyGit csBundle(i * len + j + 1).lsrc(2) := vd_old 1557fc85f18fSZiyue Zhang val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1558189ec863SzhanglyGit csBundle(i * len + j + 1).ldest := vd 1559189ec863SzhanglyGit csBundle(i * len + j + 1).uopIdx := (i * len + j).U 1560189ec863SzhanglyGit } 1561189ec863SzhanglyGit } 1562d6059658SZiyue Zhang // i to vector move 1563e03e0c5bSZiyue Zhang csBundle(0).srcType(0) := Mux(src1IsImm, SrcType.imm, SrcType.reg) 1564189ec863SzhanglyGit csBundle(0).srcType(1) := SrcType.imm 1565b50f8edeSsinsanction csBundle(0).srcType(2) := SrcType.imm 1566189ec863SzhanglyGit csBundle(0).lsrc(1) := 0.U 1567fc85f18fSZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1568fc85f18fSZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1569b1712600SZiyue Zhang csBundle(0).fuOpType := Cat(Mux(src1IsImm, IF2VectorType.imm2Vec(2, 0), IF2VectorType.i2Vec(2, 0)), vsewReg) 157093a5bfb8SZiyue Zhang csBundle(0).rfWen := false.B 157193a5bfb8SZiyue Zhang csBundle(0).fpWen := false.B 1572fc85f18fSZiyue Zhang csBundle(0).vecWen := true.B 1573189ec863SzhanglyGit genCsBundle_RGATHER_VX(1) 1574783e318eSsinceforYy switch(vlmulReg) { 1575189ec863SzhanglyGit is("b001".U ){ 1576189ec863SzhanglyGit genCsBundle_RGATHER_VX(2) 1577189ec863SzhanglyGit } 1578189ec863SzhanglyGit is("b010".U ){ 1579189ec863SzhanglyGit genCsBundle_RGATHER_VX(4) 1580189ec863SzhanglyGit } 1581189ec863SzhanglyGit is("b011".U ){ 1582189ec863SzhanglyGit genCsBundle_RGATHER_VX(8) 1583189ec863SzhanglyGit } 1584189ec863SzhanglyGit } 1585189ec863SzhanglyGit } 1586189ec863SzhanglyGit is(UopSplitType.VEC_RGATHEREI16) { 1587189ec863SzhanglyGit def genCsBundle_VEC_RGATHEREI16_SEW8(len:Int): Unit ={ 1588189ec863SzhanglyGit for (i <- 0 until len) 1589189ec863SzhanglyGit for (j <- 0 until len) { 1590189ec863SzhanglyGit val vd_old0 = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2-1).U 1591189ec863SzhanglyGit val vd0 = (VECTOR_TMP_REG_LMUL + j*2 ).U 1592189ec863SzhanglyGit csBundle((i * len + j)*2+0).lsrc(0) := src1 + (i*2+0).U 1593189ec863SzhanglyGit csBundle((i * len + j)*2+0).lsrc(1) := src2 + j.U 1594189ec863SzhanglyGit csBundle((i * len + j)*2+0).lsrc(2) := vd_old0 1595189ec863SzhanglyGit csBundle((i * len + j)*2+0).ldest := vd0 1596189ec863SzhanglyGit csBundle((i * len + j)*2+0).uopIdx := ((i * len + j)*2+0).U 1597189ec863SzhanglyGit val vd_old1 = (VECTOR_TMP_REG_LMUL + j*2).U 1598189ec863SzhanglyGit val vd1 = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j*2+1 ).U 1599189ec863SzhanglyGit csBundle((i * len + j)*2+1).lsrc(0) := src1 + (i*2+1).U 1600189ec863SzhanglyGit csBundle((i * len + j)*2+1).lsrc(1) := src2 + j.U 1601189ec863SzhanglyGit csBundle((i * len + j)*2+1).lsrc(2) := vd_old1 1602189ec863SzhanglyGit csBundle((i * len + j)*2+1).ldest := vd1 1603189ec863SzhanglyGit csBundle((i * len + j)*2+1).uopIdx := ((i * len + j)*2+1).U 1604189ec863SzhanglyGit } 1605189ec863SzhanglyGit } 1606189ec863SzhanglyGit def genCsBundle_VEC_RGATHEREI16(len:Int): Unit ={ 1607189ec863SzhanglyGit for (i <- 0 until len) 1608189ec863SzhanglyGit for (j <- 0 until len) { 1609189ec863SzhanglyGit val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 1610189ec863SzhanglyGit val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 1611189ec863SzhanglyGit csBundle(i * len + j).lsrc(0) := src1 + i.U 1612189ec863SzhanglyGit csBundle(i * len + j).lsrc(1) := src2 + j.U 1613189ec863SzhanglyGit csBundle(i * len + j).lsrc(2) := vd_old 1614189ec863SzhanglyGit csBundle(i * len + j).ldest := vd 1615189ec863SzhanglyGit csBundle(i * len + j).uopIdx := (i * len + j).U 1616189ec863SzhanglyGit } 1617189ec863SzhanglyGit } 161893a5bfb8SZiyue Zhang def genCsBundle_VEC_RGATHEREI16_SEW32(len:Int): Unit ={ 161993a5bfb8SZiyue Zhang for (i <- 0 until len) 162093a5bfb8SZiyue Zhang for (j <- 0 until len) { 162193a5bfb8SZiyue Zhang val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 162293a5bfb8SZiyue Zhang val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 162393a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(0) := src1 + (i / 2).U 162493a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(1) := src2 + j.U 162593a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(2) := vd_old 162693a5bfb8SZiyue Zhang csBundle(i * len + j).ldest := vd 162793a5bfb8SZiyue Zhang csBundle(i * len + j).uopIdx := (i * len + j).U 162893a5bfb8SZiyue Zhang } 162993a5bfb8SZiyue Zhang } 163093a5bfb8SZiyue Zhang def genCsBundle_VEC_RGATHEREI16_SEW64(len:Int): Unit ={ 163193a5bfb8SZiyue Zhang for (i <- 0 until len) 163293a5bfb8SZiyue Zhang for (j <- 0 until len) { 163393a5bfb8SZiyue Zhang val vd_old = if(j==0) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j-1).U 163493a5bfb8SZiyue Zhang val vd = if(j==len-1) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j).U 163593a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(0) := src1 + (i / 4).U 163693a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(1) := src2 + j.U 163793a5bfb8SZiyue Zhang csBundle(i * len + j).lsrc(2) := vd_old 163893a5bfb8SZiyue Zhang csBundle(i * len + j).ldest := vd 163993a5bfb8SZiyue Zhang csBundle(i * len + j).uopIdx := (i * len + j).U 164093a5bfb8SZiyue Zhang } 164193a5bfb8SZiyue Zhang } 1642aaa08c5aSxiaofeibao-xjtu when(!vsewReg.orR){ 1643189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16_SEW8(1) 164493a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e32){ 164593a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW32(1) 164693a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e64){ 164793a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW64(1) 1648189ec863SzhanglyGit }.otherwise{ 1649189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16(1) 1650189ec863SzhanglyGit } 165193a5bfb8SZiyue Zhang switch(vlmulReg) { 1652189ec863SzhanglyGit is("b001".U) { 1653aaa08c5aSxiaofeibao-xjtu when(!vsewReg.orR) { 1654189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16_SEW8(2) 165593a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e32){ 165693a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW32(2) 165793a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e64){ 165893a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW64(2) 1659189ec863SzhanglyGit }.otherwise{ 1660189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16(2) 1661189ec863SzhanglyGit } 1662189ec863SzhanglyGit } 1663189ec863SzhanglyGit is("b010".U) { 1664aaa08c5aSxiaofeibao-xjtu when(!vsewReg.orR) { 1665189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16_SEW8(4) 166693a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e32){ 166793a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW32(4) 166893a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e64){ 166993a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW64(4) 1670189ec863SzhanglyGit }.otherwise{ 1671189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16(4) 1672189ec863SzhanglyGit } 1673189ec863SzhanglyGit } 1674189ec863SzhanglyGit is("b011".U) { 167593a5bfb8SZiyue Zhang when(vsewReg === VSew.e32){ 167693a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW32(8) 167793a5bfb8SZiyue Zhang }.elsewhen(vsewReg === VSew.e64){ 167893a5bfb8SZiyue Zhang genCsBundle_VEC_RGATHEREI16_SEW64(8) 167993a5bfb8SZiyue Zhang }.otherwise{ 1680189ec863SzhanglyGit genCsBundle_VEC_RGATHEREI16(8) 1681189ec863SzhanglyGit } 1682189ec863SzhanglyGit } 1683189ec863SzhanglyGit } 168493a5bfb8SZiyue Zhang } 1685189ec863SzhanglyGit is(UopSplitType.VEC_COMPRESS) { 1686189ec863SzhanglyGit def genCsBundle_VEC_COMPRESS(len:Int): Unit = { 1687189ec863SzhanglyGit for (i <- 0 until len) { 1688189ec863SzhanglyGit val jlen = if (i == len-1) i+1 else i+2 1689189ec863SzhanglyGit for (j <- 0 until jlen) { 1690189ec863SzhanglyGit val vd_old = if(i==j) (dest + i.U) else (VECTOR_TMP_REG_LMUL + j + 1).U 1691189ec863SzhanglyGit val vd = if(i==len-1) (dest + j.U) else { 16923bec463eSlewislzh if (j == i+1) VECTOR_TMP_REG_LMUL.U else (VECTOR_TMP_REG_LMUL + j + 1).U 1693189ec863SzhanglyGit } 16943bec463eSlewislzh csBundle(i*(i+3)/2 + j).vecWen := true.B 16953bec463eSlewislzh csBundle(i*(i+3)/2 + j).v0Wen := false.B 16965da52072SsinceforYy val src13Type = if (j == i+1) DontCare else SrcType.vp 16975da52072SsinceforYy csBundle(i*(i+3)/2 + j).srcType(0) := src13Type 16985da52072SsinceforYy csBundle(i*(i+3)/2 + j).srcType(1) := SrcType.vp 16995da52072SsinceforYy csBundle(i*(i+3)/2 + j).srcType(2) := src13Type 17003bec463eSlewislzh if (i == 0) { 1701189ec863SzhanglyGit csBundle(i*(i+3)/2 + j).lsrc(0) := src1 17023bec463eSlewislzh } else { 17033bec463eSlewislzh csBundle(i*(i+3)/2 + j).lsrc(0) := VECTOR_TMP_REG_LMUL.U 17043bec463eSlewislzh } 1705189ec863SzhanglyGit csBundle(i*(i+3)/2 + j).lsrc(1) := src2 + i.U 1706189ec863SzhanglyGit csBundle(i*(i+3)/2 + j).lsrc(2) := vd_old 1707189ec863SzhanglyGit csBundle(i*(i+3)/2 + j).ldest := vd 1708189ec863SzhanglyGit csBundle(i*(i+3)/2 + j).uopIdx := (i*(i+3)/2 + j).U 1709189ec863SzhanglyGit } 1710189ec863SzhanglyGit } 1711189ec863SzhanglyGit } 1712aaa08c5aSxiaofeibao-xjtu switch(vlmulReg) { 1713189ec863SzhanglyGit is("b001".U ){ 1714189ec863SzhanglyGit genCsBundle_VEC_COMPRESS(2) 1715189ec863SzhanglyGit } 1716189ec863SzhanglyGit is("b010".U ){ 1717189ec863SzhanglyGit genCsBundle_VEC_COMPRESS(4) 1718189ec863SzhanglyGit } 1719189ec863SzhanglyGit is("b011".U ){ 1720189ec863SzhanglyGit genCsBundle_VEC_COMPRESS(8) 1721189ec863SzhanglyGit } 1722189ec863SzhanglyGit } 1723189ec863SzhanglyGit } 17240a34fc22SZiyue Zhang is(UopSplitType.VEC_MVNR) { 17250a34fc22SZiyue Zhang for (i <- 0 until MAX_VLMUL) { 17260a34fc22SZiyue Zhang csBundle(i).lsrc(0) := src1 + i.U 17270a34fc22SZiyue Zhang csBundle(i).lsrc(1) := src2 + i.U 17280a34fc22SZiyue Zhang csBundle(i).lsrc(2) := dest + i.U 17290a34fc22SZiyue Zhang csBundle(i).ldest := dest + i.U 17300a34fc22SZiyue Zhang csBundle(i).uopIdx := i.U 17310a34fc22SZiyue Zhang } 17320a34fc22SZiyue Zhang } 1733c4501a6fSZiyue-Zhang is(UopSplitType.VEC_US_LDST) { 17344ee69032SzhanglyGit /* 17354ee69032SzhanglyGit FMV.D.X 17364ee69032SzhanglyGit */ 17374ee69032SzhanglyGit csBundle(0).srcType(0) := SrcType.reg 17384ee69032SzhanglyGit csBundle(0).srcType(1) := SrcType.imm 17394ee69032SzhanglyGit csBundle(0).lsrc(1) := 0.U 1740c8cff56fSsinsanction csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1741964d9a87SZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1742964d9a87SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 17434ee69032SzhanglyGit csBundle(0).rfWen := false.B 1744c8cff56fSsinsanction csBundle(0).fpWen := false.B 1745c8cff56fSsinsanction csBundle(0).vecWen := true.B 174631c51290Szhanglinjuan csBundle(0).vlsInstr := true.B 17474ee69032SzhanglyGit //LMUL 17484ee69032SzhanglyGit for (i <- 0 until MAX_VLMUL) { 1749c8cff56fSsinsanction csBundle(i + 1).srcType(0) := SrcType.vp 1750c8cff56fSsinsanction csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 17514dfab1f2Szhanglinjuan csBundle(i + 1).lsrc(2) := dest + i.U // old vd 17524ee69032SzhanglyGit csBundle(i + 1).ldest := dest + i.U 17534ee69032SzhanglyGit csBundle(i + 1).uopIdx := i.U 175431c51290Szhanglinjuan csBundle(i + 1).vlsInstr := true.B 17554ee69032SzhanglyGit } 17564aa00286SXuan Hu csBundle.head.waitForward := isUsSegment 17574aa00286SXuan Hu csBundle(numOfUop - 1.U).blockBackward := isUsSegment 17584ee69032SzhanglyGit } 1759b0480352SZiyue Zhang is(UopSplitType.VEC_US_FF_LD) { 1760b0480352SZiyue Zhang csBundle(0).srcType(0) := SrcType.reg 1761b0480352SZiyue Zhang csBundle(0).srcType(1) := SrcType.imm 1762b0480352SZiyue Zhang csBundle(0).lsrc(1) := 0.U 1763b0480352SZiyue Zhang csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1764b0480352SZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1765b0480352SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 1766b0480352SZiyue Zhang csBundle(0).rfWen := false.B 1767b0480352SZiyue Zhang csBundle(0).fpWen := false.B 1768b0480352SZiyue Zhang csBundle(0).vecWen := true.B 1769b0480352SZiyue Zhang csBundle(0).vlsInstr := true.B 1770b0480352SZiyue Zhang //LMUL 1771b0480352SZiyue Zhang for (i <- 0 until MAX_VLMUL) { 1772b0480352SZiyue Zhang csBundle(i + 1).srcType(0) := SrcType.vp 1773b0480352SZiyue Zhang csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1774b0480352SZiyue Zhang csBundle(i + 1).lsrc(2) := dest + i.U // old vd 1775b0480352SZiyue Zhang csBundle(i + 1).ldest := dest + i.U 1776b0480352SZiyue Zhang csBundle(i + 1).uopIdx := i.U 1777b0480352SZiyue Zhang csBundle(i + 1).vlsInstr := true.B 1778b0480352SZiyue Zhang } 1779b0480352SZiyue Zhang csBundle.head.waitForward := isUsSegment 1780b0480352SZiyue Zhang csBundle(numOfUop - 1.U).blockBackward := isUsSegment 1781b0480352SZiyue Zhang // last uop read vl and write vl 1782b0480352SZiyue Zhang csBundle(numOfUop - 1.U).srcType(0) := SrcType.no 1783b0480352SZiyue Zhang csBundle(numOfUop - 1.U).srcType(1) := SrcType.no 1784b0480352SZiyue Zhang csBundle(numOfUop - 1.U).srcType(2) := SrcType.no 1785b0480352SZiyue Zhang csBundle(numOfUop - 1.U).srcType(3) := SrcType.no 1786b0480352SZiyue Zhang csBundle(numOfUop - 1.U).srcType(4) := SrcType.vp 1787b0480352SZiyue Zhang csBundle(numOfUop - 1.U).lsrc(4) := Vl_IDX.U 1788b0480352SZiyue Zhang // vtype 1789b0480352SZiyue Zhang csBundle(numOfUop - 1.U).vecWen := false.B 1790b0480352SZiyue Zhang csBundle(numOfUop - 1.U).vlWen := true.B 1791b0480352SZiyue Zhang csBundle(numOfUop - 1.U).ldest := Vl_IDX.U 1792b0480352SZiyue Zhang } 1793c4501a6fSZiyue-Zhang is(UopSplitType.VEC_S_LDST) { 1794c4501a6fSZiyue-Zhang /* 1795c4501a6fSZiyue-Zhang FMV.D.X 1796c4501a6fSZiyue-Zhang */ 1797c4501a6fSZiyue-Zhang csBundle(0).srcType(0) := SrcType.reg 1798c4501a6fSZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 1799c4501a6fSZiyue-Zhang csBundle(0).lsrc(1) := 0.U 1800c8cff56fSsinsanction csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1801964d9a87SZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1802964d9a87SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 1803c4501a6fSZiyue-Zhang csBundle(0).rfWen := false.B 1804c8cff56fSsinsanction csBundle(0).fpWen := false.B 1805c8cff56fSsinsanction csBundle(0).vecWen := true.B 180631c51290Szhanglinjuan csBundle(0).vlsInstr := true.B 1807c4501a6fSZiyue-Zhang 18086a926cf7SXuan Hu csBundle(1).srcType(0) := SrcType.reg 18096a926cf7SXuan Hu csBundle(1).srcType(1) := SrcType.imm 1810e25c13faSXuan Hu csBundle(1).lsrc(0) := latchedInst.lsrc(1) 18116a926cf7SXuan Hu csBundle(1).lsrc(1) := 0.U 1812c8cff56fSsinsanction csBundle(1).ldest := (VECTOR_TMP_REG_LMUL + 1).U 1813964d9a87SZiyue Zhang csBundle(1).fuType := FuType.i2v.U 1814964d9a87SZiyue Zhang csBundle(1).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 1815c4501a6fSZiyue-Zhang csBundle(1).rfWen := false.B 1816c8cff56fSsinsanction csBundle(1).fpWen := false.B 1817c8cff56fSsinsanction csBundle(1).vecWen := true.B 181831c51290Szhanglinjuan csBundle(1).vlsInstr := true.B 1819c4501a6fSZiyue-Zhang 1820c4501a6fSZiyue-Zhang //LMUL 1821c4501a6fSZiyue-Zhang for (i <- 0 until MAX_VLMUL) { 1822c8cff56fSsinsanction csBundle(i + 2).srcType(0) := SrcType.vp 1823c8cff56fSsinsanction csBundle(i + 2).srcType(1) := SrcType.vp 1824c8cff56fSsinsanction csBundle(i + 2).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1825c8cff56fSsinsanction csBundle(i + 2).lsrc(1) := (VECTOR_TMP_REG_LMUL + 1).U 18264dfab1f2Szhanglinjuan csBundle(i + 2).lsrc(2) := dest + i.U // old vd 1827c4501a6fSZiyue-Zhang csBundle(i + 2).ldest := dest + i.U 1828c4501a6fSZiyue-Zhang csBundle(i + 2).uopIdx := i.U 182931c51290Szhanglinjuan csBundle(i + 2).vlsInstr := true.B 1830c4501a6fSZiyue-Zhang } 18314aa00286SXuan Hu csBundle.head.waitForward := isSdSegment 18324aa00286SXuan Hu csBundle(numOfUop - 1.U).blockBackward := isSdSegment 1833c4501a6fSZiyue-Zhang } 1834c4501a6fSZiyue-Zhang is(UopSplitType.VEC_I_LDST) { 18352de01baaSZiyue Zhang def genCsBundle_SEGMENT_INDEXED_LOADSTORE(lmul:Int, nf:Int): Unit ={ 183655f7bedaSZiyue Zhang for (i <- 0 until MAX_VLMUL) { 18372de01baaSZiyue Zhang val vecWen = if (i < lmul * nf) true.B else false.B 18382de01baaSZiyue Zhang val src2Type = if (i < lmul * nf) SrcType.vp else SrcType.no 1839c8cff56fSsinsanction csBundle(i + 1).srcType(0) := SrcType.vp 1840c8cff56fSsinsanction csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 18412de01baaSZiyue Zhang csBundle(i + 1).srcType(1) := SrcType.no 184255f7bedaSZiyue Zhang csBundle(i + 1).lsrc(1) := src2 + i.U 18432de01baaSZiyue Zhang csBundle(i + 1).srcType(2) := src2Type 18442de01baaSZiyue Zhang csBundle(i + 1).lsrc(2) := dest + i.U 184555f7bedaSZiyue Zhang csBundle(i + 1).ldest := dest + i.U 18462de01baaSZiyue Zhang csBundle(i + 1).rfWen := false.B 18472de01baaSZiyue Zhang csBundle(i + 1).fpWen := false.B 18482de01baaSZiyue Zhang csBundle(i + 1).vecWen := vecWen 184955f7bedaSZiyue Zhang csBundle(i + 1).uopIdx := i.U 185055f7bedaSZiyue Zhang csBundle(i + 1).vlsInstr := true.B 185155f7bedaSZiyue Zhang } 185255f7bedaSZiyue Zhang } 18532de01baaSZiyue Zhang def genCsBundle_SEGMENT_INDEXED_LOADSTORE_SRC1(emul:Int): Unit ={ 18542de01baaSZiyue Zhang for (i <- 0 until MAX_VLMUL) { 18552de01baaSZiyue Zhang val src1Type = if (i < emul) SrcType.vp else SrcType.no 18562de01baaSZiyue Zhang csBundle(i + 1).srcType(1) := src1Type 18572de01baaSZiyue Zhang csBundle(i + 1).lsrc(1) := src2 + i.U 18582de01baaSZiyue Zhang } 18592de01baaSZiyue Zhang } 186055f7bedaSZiyue Zhang 18610cd00663SzhanglyGit val vlmul = vlmulReg 18620cd00663SzhanglyGit val vsew = Cat(0.U(1.W), vsewReg) 18630cd00663SzhanglyGit val veew = Cat(0.U(1.W), width) 1864c4501a6fSZiyue-Zhang val vemul: UInt = veew.asUInt + 1.U + vlmul.asUInt + ~vsew.asUInt 1865e3da8badSTang Haojin val simple_lmul = MuxLookup(vlmul, 0.U(2.W))(Seq( 1866c4501a6fSZiyue-Zhang "b001".U -> 1.U, 1867c4501a6fSZiyue-Zhang "b010".U -> 2.U, 1868c4501a6fSZiyue-Zhang "b011".U -> 3.U 1869c4501a6fSZiyue-Zhang )) 1870e3da8badSTang Haojin val simple_emul = MuxLookup(vemul, 0.U(2.W))(Seq( 1871c4501a6fSZiyue-Zhang "b001".U -> 1.U, 1872c4501a6fSZiyue-Zhang "b010".U -> 2.U, 1873c4501a6fSZiyue-Zhang "b011".U -> 3.U 1874c4501a6fSZiyue-Zhang )) 1875c4501a6fSZiyue-Zhang csBundle(0).srcType(0) := SrcType.reg 1876c4501a6fSZiyue-Zhang csBundle(0).srcType(1) := SrcType.imm 1877c4501a6fSZiyue-Zhang csBundle(0).lsrc(1) := 0.U 1878c8cff56fSsinsanction csBundle(0).ldest := VECTOR_TMP_REG_LMUL.U 1879964d9a87SZiyue Zhang csBundle(0).fuType := FuType.i2v.U 1880964d9a87SZiyue Zhang csBundle(0).fuOpType := Cat(IF2VectorType.i2Vec(2, 0), e64) 1881c4501a6fSZiyue-Zhang csBundle(0).rfWen := false.B 1882c8cff56fSsinsanction csBundle(0).fpWen := false.B 1883c8cff56fSsinsanction csBundle(0).vecWen := true.B 188431c51290Szhanglinjuan csBundle(0).vlsInstr := true.B 1885c4501a6fSZiyue-Zhang 1886c4501a6fSZiyue-Zhang //LMUL 188755f7bedaSZiyue Zhang when(nf === 0.U) { 188855f7bedaSZiyue Zhang for (i <- 0 until MAX_VLMUL) { 188955f7bedaSZiyue Zhang indexedLSRegOffset(i).src := Cat(simple_emul, simple_lmul) 1890c4501a6fSZiyue-Zhang val offsetVs2 = indexedLSRegOffset(i).outOffsetVs2 1891c4501a6fSZiyue-Zhang val offsetVd = indexedLSRegOffset(i).outOffsetVd 1892c8cff56fSsinsanction csBundle(i + 1).srcType(0) := SrcType.vp 1893c8cff56fSsinsanction csBundle(i + 1).lsrc(0) := VECTOR_TMP_REG_LMUL.U 1894c4501a6fSZiyue-Zhang csBundle(i + 1).lsrc(1) := Mux1H(UIntToOH(offsetVs2, MAX_VLMUL), (0 until MAX_VLMUL).map(j => src2 + j.U)) 1895792b1339SAnzooooo csBundle(i + 1).srcType(2) := SrcType.vp 189655f7bedaSZiyue Zhang // lsrc2 is old vd 1897792b1339SAnzooooo csBundle(i + 1).lsrc(2) := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1898c4501a6fSZiyue-Zhang csBundle(i + 1).ldest := Mux1H(UIntToOH(offsetVd, MAX_VLMUL), (0 until MAX_VLMUL).map(j => dest + j.U)) 1899c4501a6fSZiyue-Zhang csBundle(i + 1).uopIdx := i.U 190031c51290Szhanglinjuan csBundle(i + 1).vlsInstr := true.B 1901c4501a6fSZiyue-Zhang } 190255f7bedaSZiyue Zhang }.otherwise{ 190355f7bedaSZiyue Zhang // nf > 1, is segment indexed load/store 19042de01baaSZiyue Zhang // gen src0, vd 19052de01baaSZiyue Zhang switch(simple_lmul) { 19062de01baaSZiyue Zhang is(0.U) { 19072de01baaSZiyue Zhang switch(nf) { 19082de01baaSZiyue Zhang is(1.U) { 19092de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 2) 191055f7bedaSZiyue Zhang } 19112de01baaSZiyue Zhang is(2.U) { 19122de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 3) 191355f7bedaSZiyue Zhang } 19142de01baaSZiyue Zhang is(3.U) { 19152de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 4) 19162de01baaSZiyue Zhang } 19172de01baaSZiyue Zhang is(4.U) { 19182de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 5) 19192de01baaSZiyue Zhang } 19202de01baaSZiyue Zhang is(5.U) { 19212de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 6) 19222de01baaSZiyue Zhang } 19232de01baaSZiyue Zhang is(6.U) { 19242de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 7) 19252de01baaSZiyue Zhang } 19262de01baaSZiyue Zhang is(7.U) { 19272de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(1, 8) 19282de01baaSZiyue Zhang } 19292de01baaSZiyue Zhang } 19302de01baaSZiyue Zhang } 19312de01baaSZiyue Zhang is(1.U) { 19322de01baaSZiyue Zhang switch(nf) { 19332de01baaSZiyue Zhang is(1.U) { 19342de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(2, 2) 19352de01baaSZiyue Zhang } 19362de01baaSZiyue Zhang is(2.U) { 19372de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(2, 3) 19382de01baaSZiyue Zhang } 19392de01baaSZiyue Zhang is(3.U) { 19402de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(2, 4) 19412de01baaSZiyue Zhang } 19422de01baaSZiyue Zhang } 19432de01baaSZiyue Zhang } 19442de01baaSZiyue Zhang is(2.U) { 19452de01baaSZiyue Zhang switch(nf) { 19462de01baaSZiyue Zhang is(1.U) { 19472de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE(4, 2) 19482de01baaSZiyue Zhang } 19492de01baaSZiyue Zhang } 19502de01baaSZiyue Zhang } 19512de01baaSZiyue Zhang } 19522de01baaSZiyue Zhang 19532de01baaSZiyue Zhang // gen src1 19542de01baaSZiyue Zhang switch(simple_emul) { 19552de01baaSZiyue Zhang is(0.U) { 19562de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE_SRC1(1) 19572de01baaSZiyue Zhang } 19582de01baaSZiyue Zhang is(1.U) { 19592de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE_SRC1(2) 19602de01baaSZiyue Zhang } 19612de01baaSZiyue Zhang is(2.U) { 19622de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE_SRC1(4) 19632de01baaSZiyue Zhang } 19642de01baaSZiyue Zhang is(3.U) { 19652de01baaSZiyue Zhang genCsBundle_SEGMENT_INDEXED_LOADSTORE_SRC1(8) 196655f7bedaSZiyue Zhang } 196755f7bedaSZiyue Zhang } 19687635b2a1SZiyue Zhang 19697635b2a1SZiyue Zhang // when is vstore instructions, not set vecwen 19707635b2a1SZiyue Zhang when(isVstore) { 19717635b2a1SZiyue Zhang for (i <- 0 until MAX_VLMUL) { 19727635b2a1SZiyue Zhang csBundle(i + 1).vecWen := false.B 19737635b2a1SZiyue Zhang } 19747635b2a1SZiyue Zhang } 197555f7bedaSZiyue Zhang } 19764aa00286SXuan Hu csBundle.head.waitForward := isIxSegment 19774aa00286SXuan Hu csBundle(numOfUop - 1.U).blockBackward := isIxSegment 1978c4501a6fSZiyue-Zhang } 1979d91483a6Sfdy } 1980d91483a6Sfdy 1981d91483a6Sfdy //readyFromRename Counter 1982d9cc7216Sxiaofeibao-xjtu val readyCounter = Mux(outReadys.head, RenameWidth.U, 0.U) 1983e25c13faSXuan Hu 1984e25c13faSXuan Hu // The left uops of the complex inst in ComplexDecoder can be send out this cycle 1985e25c13faSXuan Hu val thisAllOut = uopRes <= readyCounter 1986d91483a6Sfdy 1987*c7ca40e4SGuanghui Cheng val count = RegInit(0.U(log2Up(maxUopSize/RenameWidth + 1).W)) 1988*c7ca40e4SGuanghui Cheng val countNext = WireInit(count) 1989*c7ca40e4SGuanghui Cheng 1990189ec863SzhanglyGit switch(state) { 1991e25c13faSXuan Hu is(s_idle) { 1992e25c13faSXuan Hu when (inValid) { 1993e25c13faSXuan Hu stateNext := s_active 1994e25c13faSXuan Hu uopResNext := inUopInfo.numOfUop 1995*c7ca40e4SGuanghui Cheng countNext := 0.U 1996d91483a6Sfdy } 1997e25c13faSXuan Hu } 1998e25c13faSXuan Hu is(s_active) { 1999e25c13faSXuan Hu when (thisAllOut) { 2000e25c13faSXuan Hu when (inValid) { 2001e25c13faSXuan Hu stateNext := s_active 2002e25c13faSXuan Hu uopResNext := inUopInfo.numOfUop 2003e25c13faSXuan Hu }.otherwise { 2004e25c13faSXuan Hu stateNext := s_idle 2005e25c13faSXuan Hu uopResNext := 0.U 2006e25c13faSXuan Hu } 2007*c7ca40e4SGuanghui Cheng countNext := 0.U 2008e25c13faSXuan Hu }.otherwise { 2009e25c13faSXuan Hu stateNext := s_active 2010e25c13faSXuan Hu uopResNext := uopRes - readyCounter 2011*c7ca40e4SGuanghui Cheng countNext := count + outReadys.head.asUInt 2012e25c13faSXuan Hu } 2013d91483a6Sfdy } 2014d91483a6Sfdy } 2015d91483a6Sfdy 2016e25c13faSXuan Hu state := Mux(io.redirect, s_idle, stateNext) 2017e25c13faSXuan Hu uopRes := Mux(io.redirect, 0.U, uopResNext) 2018*c7ca40e4SGuanghui Cheng count := Mux(io.redirect, 0.U, countNext) 2019189ec863SzhanglyGit 2020e25c13faSXuan Hu val complexNum = Mux(uopRes > readyCounter, readyCounter, uopRes) 2021d91483a6Sfdy 20228e59a3a7SXuan Hu fixedDecodedInst := csBundle 20238e59a3a7SXuan Hu 20248e59a3a7SXuan Hu // when vstart is not zero, the last uop will modify vstart to zero 20258e59a3a7SXuan Hu // therefore, blockback and flush pipe 20268e59a3a7SXuan Hu fixedDecodedInst(numOfUop - 1.U).flushPipe := (vstartReg =/= 0.U) || latchedInst.flushPipe 2027*c7ca40e4SGuanghui Cheng val uopsSeq = (0 until RenameWidth).map(i => VecInit(fixedDecodedInst.zipWithIndex.filter(_._2 % RenameWidth == i).map(_._1))) 2028d91483a6Sfdy for(i <- 0 until RenameWidth) { 2029e25c13faSXuan Hu outValids(i) := complexNum > i.U 2030*c7ca40e4SGuanghui Cheng outDecodedInsts(i) := uopsSeq(i)(count) 2031d91483a6Sfdy } 2032d91483a6Sfdy 2033e25c13faSXuan Hu outComplexNum := Mux(state === s_active, complexNum, 0.U) 2034e25c13faSXuan Hu inReady := state === s_idle || state === s_active && thisAllOut 2035d91483a6Sfdy 2036ddc88dadSxiaofeibao 20373e10d835SXuan Hu XSError(inValid && inUopInfo.numOfUop === 0.U, 20383e10d835SXuan Hu p"uop number ${inUopInfo.numOfUop} is illegal, cannot be zero") 2039e25c13faSXuan Hu// val validSimple = Wire(Vec(DecodeWidth, Bool())) 2040e25c13faSXuan Hu// validSimple.zip(io.validFromIBuf.zip(io.isComplex)).map{ case (dst, (src1, src2)) => dst := src1 && !src2 } 2041e25c13faSXuan Hu// val notInf = Wire(Vec(DecodeWidth, Bool())) 2042e25c13faSXuan Hu// notInf.drop(1).zip(io.validFromIBuf.drop(1).zip(validSimple.drop(1))).map{ case (dst, (src1, src2)) => dst := !src1 || src2 } 2043e25c13faSXuan Hu// notInf(0) := !io.validFromIBuf(0) || validSimple(0) || (io.isComplex(0) && io.in0pc === io.simple.decodedInst.pc) 2044e25c13faSXuan Hu// val notInfVec = Wire(Vec(DecodeWidth, Bool())) 2045e25c13faSXuan Hu// notInfVec.zipWithIndex.map{ case (dst, i) => dst := Cat(notInf.take(i + 1)).andR} 2046e25c13faSXuan Hu// 2047e25c13faSXuan Hu// complexNum := Mux(io.validFromIBuf(0) && readyCounter.orR , 2048e25c13faSXuan Hu// Mux(uopRes0 > readyCounter, readyCounter, uopRes0), 2049e25c13faSXuan Hu// 0.U) 2050e25c13faSXuan Hu// validToRename.zipWithIndex.foreach{ 2051e25c13faSXuan Hu// case(dst, i) => 2052e25c13faSXuan Hu// val validFix = Mux(complexNum.orR, validSimple((i+1).U - complexNum), validSimple(i)) 2053e25c13faSXuan Hu// dst := MuxCase(false.B, Seq( 2054e25c13faSXuan Hu// (io.validFromIBuf(0) && readyCounter.orR && uopRes0 > readyCounter) -> Mux(readyCounter > i.U, true.B, false.B), 2055e25c13faSXuan Hu// (io.validFromIBuf(0) && readyCounter.orR && !(uopRes0 > readyCounter)) -> Mux(complexNum > i.U, true.B, validFix && notInfVec(i.U - complexNum) && io.readyFromRename(i)), 2056e25c13faSXuan Hu// ).toSeq) 2057e25c13faSXuan Hu// } 2058e25c13faSXuan Hu// 2059e25c13faSXuan Hu// readyToIBuf.zipWithIndex.foreach { 2060e25c13faSXuan Hu// case (dst, i) => 2061e25c13faSXuan Hu// val readyToIBuf0 = Mux(io.isComplex(0), io.in0pc === io.simple.decodedInst.pc, true.B) 2062e25c13faSXuan Hu// dst := MuxCase(true.B, Seq( 2063e25c13faSXuan Hu// (io.validFromIBuf(0) && uopRes0 > readyCounter || !readyCounter.orR) -> false.B, 2064e25c13faSXuan Hu// (io.validFromIBuf(0) && !(uopRes0 > readyCounter) && readyCounter.orR) -> (if (i==0) readyToIBuf0 else Mux(RenameWidth.U - complexNum >= i.U, notInfVec(i) && validSimple(i) && io.readyFromRename(i), false.B)) 2065e25c13faSXuan Hu// ).toSeq) 2066e25c13faSXuan Hu// } 2067e25c13faSXuan Hu// 2068e25c13faSXuan Hu// io.deq.decodedInsts := decodedInsts 2069e25c13faSXuan Hu// io.deq.complexNum := complexNum 2070e25c13faSXuan Hu// io.deq.validToRename := validToRename 2071e25c13faSXuan Hu// io.deq.readyToIBuf := readyToIBuf 2072d91483a6Sfdy} 2073