1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend.decode 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import freechips.rocketchip.rocket.Instructions._ 23import freechips.rocketchip.util.uintToBitPat 24import utility._ 25import utils._ 26import xiangshan.ExceptionNO.illegalInstr 27import xiangshan._ 28import xiangshan.backend.fu.FuType 29import xiangshan.backend.Bundles.{DecodedInst, DynInst, StaticInst} 30import xiangshan.backend.decode.isa.bitfield.{InstVType, XSInstBitFields} 31import xiangshan.backend.fu.vector.Bundles.{Category, VType} 32 33/** 34 * Abstract trait giving defaults and other relevant values to different Decode constants/ 35 */ 36abstract trait DecodeConstants { 37 // This X should be used only in 1-bit signal. Otherwise, use BitPat("b???") to align with the width of UInt. 38 def X = BitPat("b0") 39 def N = BitPat("b0") 40 def Y = BitPat("b1") 41 def T = true 42 def F = false 43 44 def decodeDefault: List[BitPat] = // illegal instruction 45 // srcType(0) srcType(1) srcType(2) fuType fuOpType rfWen 46 // | | | | | | fpWen 47 // | | | | | | | vecWen 48 // | | | | | | | | isXSTrap 49 // | | | | | | | | | noSpecExec 50 // | | | | | | | | | | blockBackward 51 // | | | | | | | | | | | flushPipe 52 // | | | | | | | | | | | | uopDivType 53 // | | | | | | | | | | | | | selImm 54 List(SrcType.X, SrcType.X, SrcType.X, FuType.X, FuOpType.X, N, N, N, N, N, N, N, UopSplitType.X, SelImm.INVALID_INSTR) // Use SelImm to indicate invalid instr 55 56 val decodeArray: Array[(BitPat, XSDecodeBase)] 57 final def table: Array[(BitPat, List[BitPat])] = decodeArray.map(x => (x._1, x._2.generate())) 58} 59 60trait DecodeUnitConstants 61{ 62 // abstract out instruction decode magic numbers 63 val RD_MSB = 11 64 val RD_LSB = 7 65 val RS1_MSB = 19 66 val RS1_LSB = 15 67 val RS2_MSB = 24 68 val RS2_LSB = 20 69 val RS3_MSB = 31 70 val RS3_LSB = 27 71} 72 73/** 74 * Decoded control signals 75 * See xiangshan/package.scala, xiangshan/backend/package.scala, Bundle.scala 76 */ 77 78abstract class XSDecodeBase { 79 def X = BitPat("b?") 80 def N = BitPat("b0") 81 def Y = BitPat("b1") 82 def T = true 83 def F = false 84 def generate() : List[BitPat] 85} 86 87case class XSDecode( 88 src1: BitPat, src2: BitPat, src3: BitPat, 89 fu: Int, fuOp: BitPat, selImm: BitPat, 90 uopSplitType: BitPat = UopSplitType.X, 91 xWen: Boolean = false, 92 fWen: Boolean = false, 93 vWen: Boolean = false, 94 mWen: Boolean = false, 95 xsTrap: Boolean = false, 96 noSpec: Boolean = false, 97 blockBack: Boolean = false, 98 flushPipe: Boolean = false, 99) extends XSDecodeBase { 100 def generate() : List[BitPat] = { 101 List (src1, src2, src3, BitPat(fu.U(FuType.num.W)), fuOp, xWen.B, fWen.B, (vWen || mWen).B, xsTrap.B, noSpec.B, blockBack.B, flushPipe.B, uopSplitType, selImm) 102 } 103} 104 105case class FDecode( 106 src1: BitPat, src2: BitPat, src3: BitPat, 107 fu: Int, fuOp: BitPat, selImm: BitPat = SelImm.X, 108 uopSplitType: BitPat = UopSplitType.X, 109 xWen: Boolean = false, 110 fWen: Boolean = false, 111 vWen: Boolean = false, 112 mWen: Boolean = false, 113 xsTrap: Boolean = false, 114 noSpec: Boolean = false, 115 blockBack: Boolean = false, 116 flushPipe: Boolean = false, 117) extends XSDecodeBase { 118 def generate() : List[BitPat] = { 119 XSDecode(src1, src2, src3, fu, fuOp, selImm, uopSplitType, xWen, fWen, vWen, mWen, xsTrap, noSpec, blockBack, flushPipe).generate() 120 } 121} 122 123/** 124 * Decode constants for RV64 125 */ 126object X64Decode extends DecodeConstants { 127 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 128 LD -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld , SelImm.IMM_I, xWen = T), 129 LWU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lwu , SelImm.IMM_I, xWen = T), 130 SD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sd , SelImm.IMM_S ), 131 132 SLLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.IMM_I, xWen = T), 133 SRLI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.IMM_I, xWen = T), 134 SRAI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.IMM_I, xWen = T), 135 136 ADDIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.IMM_I, xWen = T), 137 SLLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.IMM_I, xWen = T), 138 SRAIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.IMM_I, xWen = T), 139 SRLIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.IMM_I, xWen = T), 140 141 ADDW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.addw, SelImm.X , xWen = T), 142 SUBW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.subw, SelImm.X , xWen = T), 143 SLLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sllw, SelImm.X , xWen = T), 144 SRAW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sraw, SelImm.X , xWen = T), 145 SRLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srlw, SelImm.X , xWen = T), 146 147 RORW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.X , xWen = T), 148 RORIW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.rorw, SelImm.IMM_I, xWen = T), 149 ROLW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rolw, SelImm.X , xWen = T), 150 ) 151} 152 153/** 154 * Overall Decode constants 155 */ 156object XDecode extends DecodeConstants { 157 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 158 LW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw , SelImm.IMM_I, xWen = T), 159 LH -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lh , SelImm.IMM_I, xWen = T), 160 LHU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lhu , SelImm.IMM_I, xWen = T), 161 LB -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lb , SelImm.IMM_I, xWen = T), 162 LBU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lbu , SelImm.IMM_I, xWen = T), 163 SW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sw , SelImm.IMM_S ), 164 SH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sh , SelImm.IMM_S ), 165 SB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.stu, LSUOpType.sb , SelImm.IMM_S ), 166 LUI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_U, xWen = T), 167 ADDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add , SelImm.IMM_I, xWen = T), 168 ANDI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.and , SelImm.IMM_I, xWen = T), 169 ORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.or , SelImm.IMM_I, xWen = T), 170 XORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.IMM_I, xWen = T), 171 SLTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.IMM_I, xWen = T), 172 SLTIU -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.IMM_I, xWen = T), 173 SLL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sll , SelImm.X , xWen = T), 174 ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.add , SelImm.X , xWen = T), 175 SUB -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sub , SelImm.X , xWen = T), 176 SLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.slt , SelImm.X , xWen = T), 177 SLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sltu, SelImm.X , xWen = T), 178 AND -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.and , SelImm.X , xWen = T), 179 OR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.or , SelImm.X , xWen = T), 180 XOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xor , SelImm.X , xWen = T), 181 SRA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sra , SelImm.X , xWen = T), 182 SRL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.srl , SelImm.X , xWen = T), 183 184 MUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mul , SelImm.X, xWen = T), 185 MULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulh , SelImm.X, xWen = T), 186 MULHU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhu , SelImm.X, xWen = T), 187 MULHSU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulhsu, SelImm.X, xWen = T), 188 MULW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mul, MDUOpType.mulw , SelImm.X, xWen = T), 189 190 DIV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.div , SelImm.X, xWen = T), 191 DIVU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divu , SelImm.X, xWen = T), 192 REM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.rem , SelImm.X, xWen = T), 193 REMU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remu , SelImm.X, xWen = T), 194 DIVW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divw , SelImm.X, xWen = T), 195 DIVUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.divuw , SelImm.X, xWen = T), 196 REMW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remw , SelImm.X, xWen = T), 197 REMUW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.div, MDUOpType.remuw , SelImm.X, xWen = T), 198 199 AUIPC -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.auipc, SelImm.IMM_U , xWen = T), 200 JAL -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jal , SelImm.IMM_UJ, xWen = T), 201 JALR -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.jmp, JumpOpType.jalr , SelImm.IMM_I , uopSplitType = UopSplitType.SCA_SIM, xWen = T), 202 BEQ -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.beq , SelImm.IMM_SB ), 203 BNE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bne , SelImm.IMM_SB ), 204 BGE -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bge , SelImm.IMM_SB ), 205 BGEU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bgeu , SelImm.IMM_SB ), 206 BLT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.blt , SelImm.IMM_SB ), 207 BLTU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.brh, BRUOpType.bltu , SelImm.IMM_SB ), 208 209 // I-type, the immediate12 holds the CSR register. 210 CSRRW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrt , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 211 CSRRS -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.set , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 212 CSRRC -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clr , SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 213 214 CSRRWI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.wrti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 215 CSRRSI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.seti, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 216 CSRRCI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.clri, SelImm.IMM_Z, xWen = T, noSpec = T, blockBack = T), 217 218 EBREAK -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 219 ECALL -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 220 SRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 221 MRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 222 DRET -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.csr, CSROpType.jmp, SelImm.IMM_I, xWen = T, noSpec = T, blockBack = T), 223 WFI -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.csr, CSROpType.wfi, SelImm.X , xWen = T, noSpec = T, blockBack = T), 224 225 SFENCE_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 226 FENCE_I -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fencei, SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 227 FENCE -> XSDecode(SrcType.pc , SrcType.imm, SrcType.X, FuType.fence, FenceOpType.fence , SelImm.X, noSpec = T, blockBack = T, flushPipe = T), 228 229 // A-type 230 AMOADD_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 231 AMOXOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 232 AMOSWAP_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 233 AMOAND_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 234 AMOOR_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 235 AMOMIN_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 236 AMOMINU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 237 AMOMAX_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_w , SelImm.X, xWen = T, noSpec = T, blockBack = T), 238 AMOMAXU_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 239 240 AMOADD_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoadd_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 241 AMOXOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoxor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 242 AMOSWAP_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoswap_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 243 AMOAND_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoand_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 244 AMOOR_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amoor_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 245 AMOMIN_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomin_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 246 AMOMINU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amominu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 247 AMOMAX_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomax_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 248 AMOMAXU_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.amomaxu_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 249 250 LR_W -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 251 LR_D -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.mou, LSUOpType.lr_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 252 SC_W -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_w, SelImm.X, xWen = T, noSpec = T, blockBack = T), 253 SC_D -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.mou, LSUOpType.sc_d, SelImm.X, xWen = T, noSpec = T, blockBack = T), 254 255 ANDN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.andn, SelImm.X, xWen = T), 256 ORN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.orn , SelImm.X, xWen = T), 257 XNOR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.xnor, SelImm.X, xWen = T), 258 ORC_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.orcb, SelImm.X, xWen = T), 259 260 MIN -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.min , SelImm.X, xWen = T), 261 MINU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.minu, SelImm.X, xWen = T), 262 MAX -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.max , SelImm.X, xWen = T), 263 MAXU -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.maxu, SelImm.X, xWen = T), 264 265 SEXT_B -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sextb, SelImm.X, xWen = T), 266 PACKH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packh, SelImm.X, xWen = T), 267 SEXT_H -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.sexth, SelImm.X, xWen = T), 268 PACKW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.packw, SelImm.X, xWen = T), 269 BREV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.revb , SelImm.X, xWen = T), 270 REV8 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.alu, ALUOpType.rev8 , SelImm.X, xWen = T), 271 PACK -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.pack , SelImm.X, xWen = T), 272 273 BSET -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.X , xWen = T), 274 BSETI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bset, SelImm.IMM_I, xWen = T), 275 BCLR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.X , xWen = T), 276 BCLRI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bclr, SelImm.IMM_I, xWen = T), 277 BINV -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.X , xWen = T), 278 BINVI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.binv, SelImm.IMM_I, xWen = T), 279 BEXT -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.X , xWen = T), 280 BEXTI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.bext, SelImm.IMM_I, xWen = T), 281 282 ROR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.X , xWen = T), 283 RORI -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.ror, SelImm.IMM_I , xWen = T), 284 ROL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.rol, SelImm.X , xWen = T), 285 286 SH1ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1add , SelImm.X , xWen = T), 287 SH2ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2add , SelImm.X , xWen = T), 288 SH3ADD -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3add , SelImm.X , xWen = T), 289 SH1ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh1adduw, SelImm.X , xWen = T), 290 SH2ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh2adduw, SelImm.X , xWen = T), 291 SH3ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.sh3adduw, SelImm.X , xWen = T), 292 ADD_UW -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.alu, ALUOpType.adduw , SelImm.X , xWen = T), 293 SLLI_UW -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.slliuw , SelImm.IMM_I, xWen = T), 294 ) 295} 296 297/** 298 * FP Decode constants 299 */ 300object FpDecode extends DecodeConstants{ 301 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 302 FLW -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.lw, selImm = SelImm.IMM_I, fWen = T), 303 FLD -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.ldu, LSUOpType.ld, selImm = SelImm.IMM_I, fWen = T), 304 FSW -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sw, selImm = SelImm.IMM_S ), 305 FSD -> FDecode(SrcType.reg, SrcType.fp, SrcType.X, FuType.stu, LSUOpType.sd, selImm = SelImm.IMM_S ), 306 307 FCLASS_S-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 308 FCLASS_D-> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 309 310 FMV_X_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 311 FMV_X_W -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 312 313 FMV_D_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 314 FMV_W_X -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 315 316 FSGNJ_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 317 FSGNJ_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 318 FSGNJX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 319 FSGNJX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 320 FSGNJN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 321 FSGNJN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 322 323 // FP to FP 324 FCVT_S_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 325 FCVT_D_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 326 327 // Int to FP 328 FCVT_S_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 329 FCVT_S_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 330 FCVT_S_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 331 FCVT_S_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 332 333 FCVT_D_W -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 334 FCVT_D_WU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 335 FCVT_D_L -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 336 FCVT_D_LU -> FDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.i2f, FuOpType.X, fWen = T), 337 338 // FP to Int 339 FCVT_W_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 340 FCVT_WU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 341 FCVT_L_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 342 FCVT_LU_S -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 343 344 FCVT_W_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 345 FCVT_WU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 346 FCVT_L_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 347 FCVT_LU_D -> FDecode(SrcType.fp , SrcType.imm, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 348 349 FEQ_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 350 FLT_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 351 FLE_S -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 352 353 FEQ_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 354 FLT_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 355 FLE_D -> FDecode(SrcType.fp , SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, xWen = T), 356 357 FMIN_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 358 FMAX_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 359 FMIN_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 360 FMAX_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmisc, FuOpType.X, fWen = T), 361 362 FADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 363 FSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 364 FMUL_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 365 FADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 366 FSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 367 FMUL_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fmac, FuOpType.X, fWen = T), 368 369 FMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 370 FMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 371 FNMADD_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 372 FNMSUB_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 373 FMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 374 FMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 375 FNMADD_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 376 FNMSUB_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.fp, FuType.fmac, FuOpType.X, fWen = T), 377 ) 378} 379 380/** 381 * Bit Manipulation Decode 382 */ 383object BDecode extends DecodeConstants{ 384 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 385 // Basic bit manipulation 386 CLZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clz, SelImm.X, xWen = T), 387 CTZ -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctz, SelImm.X, xWen = T), 388 CPOP -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpop, SelImm.X, xWen = T), 389 XPERM8 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermb, SelImm.X, xWen = T), 390 XPERM4 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.xpermn, SelImm.X, xWen = T), 391 392 CLZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.clzw, SelImm.X, xWen = T), 393 CTZW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.ctzw, SelImm.X, xWen = T), 394 CPOPW -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.cpopw, SelImm.X, xWen = T), 395 396 CLMUL -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmul, SelImm.X, xWen = T), 397 CLMULH -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulh, SelImm.X, xWen = T), 398 CLMULR -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.clmulr, SelImm.X, xWen = T), 399 400 AES64ES -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64es, SelImm.X , xWen = T), 401 AES64ESM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64esm, SelImm.X , xWen = T), 402 AES64DS -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ds, SelImm.X , xWen = T), 403 AES64DSM -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64dsm, SelImm.X , xWen = T), 404 AES64IM -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.aes64im, SelImm.X , xWen = T), 405 AES64KS1I -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.bku, BKUOpType.aes64ks1i, SelImm.IMM_I, xWen = T), 406 AES64KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.aes64ks2, SelImm.X , xWen = T), 407 SHA256SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum0, SelImm.X , xWen = T), 408 SHA256SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sum1, SelImm.X , xWen = T), 409 SHA256SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig0, SelImm.X , xWen = T), 410 SHA256SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha256sig1, SelImm.X , xWen = T), 411 SHA512SUM0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum0, SelImm.X , xWen = T), 412 SHA512SUM1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sum1, SelImm.X , xWen = T), 413 SHA512SIG0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig0, SelImm.X , xWen = T), 414 SHA512SIG1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sha512sig1, SelImm.X , xWen = T), 415 SM3P0 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p0, SelImm.X , xWen = T), 416 SM3P1 -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.bku, BKUOpType.sm3p1, SelImm.X , xWen = T), 417 SM4KS0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks0, SelImm.X , xWen = T), 418 SM4KS1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks1, SelImm.X , xWen = T), 419 SM4KS2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks2, SelImm.X , xWen = T), 420 SM4KS3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ks3, SelImm.X , xWen = T), 421 SM4ED0 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed0, SelImm.X , xWen = T), 422 SM4ED1 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed1, SelImm.X , xWen = T), 423 SM4ED2 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed2, SelImm.X , xWen = T), 424 SM4ED3 -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.bku, BKUOpType.sm4ed3, SelImm.X , xWen = T), 425 ) 426} 427 428/** 429 * FP Divide SquareRoot Constants 430 */ 431object FDivSqrtDecode extends DecodeConstants { 432 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 433 FDIV_S -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 434 FDIV_D -> FDecode(SrcType.fp, SrcType.fp, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 435 FSQRT_S -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 436 FSQRT_D -> FDecode(SrcType.fp, SrcType.imm, SrcType.X, FuType.fDivSqrt, FuOpType.X, fWen = T), 437 ) 438} 439 440/** 441 * Svinval extension Constants 442 */ 443object SvinvalDecode extends DecodeConstants { 444 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 445 /* sinval_vma is like sfence.vma , but sinval_vma can be dispatched and issued like normal instructions while sfence.vma 446 * must assure it is the ONLY instrucion executing in backend. 447 */ 448 SINVAL_VMA -> XSDecode(SrcType.reg, SrcType.reg, SrcType.X, FuType.fence, FenceOpType.sfence, SelImm.X), 449 /* sfecne.w.inval is the begin instrucion of a TLB flush which set *noSpecExec* and *blockBackward* signals 450 * so when it comes to dispatch , it will block all instruction after itself until all instrucions ahead of it in rob commit 451 * then dispatch and issue this instrucion to flush sbuffer to dcache 452 * after this instrucion commits , issue following sinval_vma instructions (out of order) to flush TLB 453 */ 454 SFENCE_W_INVAL -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T), 455 /* sfecne.inval.ir is the end instrucion of a TLB flush which set *noSpecExec* *blockBackward* and *flushPipe* signals 456 * so when it comes to dispatch , it will wait until all sinval_vma ahead of it in rob commit 457 * then dispatch and issue this instrucion 458 * when it commit at the head of rob , flush the pipeline since some instrucions have been fetched to ibuffer using old TLB map 459 */ 460 SFENCE_INVAL_IR -> XSDecode(SrcType.DC, SrcType.DC, SrcType.X, FuType.fence, FenceOpType.nofence, SelImm.X, noSpec = T, blockBack = T, flushPipe = T) 461 /* what is Svinval extension ? 462 * -----> sfecne.w.inval 463 * sfence.vma vpn1 -----> sinval_vma vpn1 464 * sfence.vma vpn2 -----> sinval_vma vpn2 465 * -----> sfecne.inval.ir 466 * 467 * sfence.vma should be executed in-order and it flushes the pipeline after committing 468 * we can parallel sfence instrucions with this extension 469 */ 470 ) 471} 472 473/* 474 * CBO decode 475 */ 476object CBODecode extends DecodeConstants { 477 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 478 CBO_ZERO -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_zero , SelImm.IMM_S), 479 CBO_CLEAN -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_clean, SelImm.IMM_S), 480 CBO_FLUSH -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_flush, SelImm.IMM_S), 481 CBO_INVAL -> XSDecode(SrcType.reg, SrcType.DC, SrcType.X, FuType.stu, LSUOpType.cbo_inval, SelImm.IMM_S) 482 ) 483} 484 485/** 486 * XiangShan Trap Decode constants 487 */ 488object XSTrapDecode extends DecodeConstants { 489 def TRAP = BitPat("b000000000000?????000000001101011") 490 val decodeArray: Array[(BitPat, XSDecodeBase)] = Array( 491 TRAP -> XSDecode(SrcType.reg, SrcType.imm, SrcType.X, FuType.alu, ALUOpType.add, SelImm.IMM_I, xWen = T, xsTrap = T, noSpec = T, blockBack = T) 492 ) 493} 494 495abstract class Imm(val len: Int) extends Bundle { 496 def toImm32(minBits: UInt): UInt = do_toImm32(minBits(len - 1, 0)) 497 def do_toImm32(minBits: UInt): UInt 498 def minBitsFromInstr(instr: UInt): UInt 499} 500 501case class Imm_I() extends Imm(12) { 502 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits(len - 1, 0), 32) 503 504 override def minBitsFromInstr(instr: UInt): UInt = 505 Cat(instr(31, 20)) 506} 507 508case class Imm_S() extends Imm(12) { 509 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 510 511 override def minBitsFromInstr(instr: UInt): UInt = 512 Cat(instr(31, 25), instr(11, 7)) 513} 514 515case class Imm_B() extends Imm(12) { 516 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 517 518 override def minBitsFromInstr(instr: UInt): UInt = 519 Cat(instr(31), instr(7), instr(30, 25), instr(11, 8)) 520} 521 522case class Imm_U() extends Imm(20){ 523 override def do_toImm32(minBits: UInt): UInt = Cat(minBits(len - 1, 0), 0.U(12.W)) 524 525 override def minBitsFromInstr(instr: UInt): UInt = { 526 instr(31, 12) 527 } 528} 529 530case class Imm_J() extends Imm(20){ 531 override def do_toImm32(minBits: UInt): UInt = SignExt(Cat(minBits, 0.U(1.W)), 32) 532 533 override def minBitsFromInstr(instr: UInt): UInt = { 534 Cat(instr(31), instr(19, 12), instr(20), instr(30, 25), instr(24, 21)) 535 } 536} 537 538case class Imm_Z() extends Imm(12 + 5){ 539 override def do_toImm32(minBits: UInt): UInt = minBits 540 541 override def minBitsFromInstr(instr: UInt): UInt = { 542 Cat(instr(19, 15), instr(31, 20)) 543 } 544} 545 546case class Imm_B6() extends Imm(6){ 547 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 548 549 override def minBitsFromInstr(instr: UInt): UInt = { 550 instr(25, 20) 551 } 552} 553 554case class Imm_OPIVIS() extends Imm(5){ 555 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 556 557 override def minBitsFromInstr(instr: UInt): UInt = { 558 instr(19, 15) 559 } 560} 561 562case class Imm_OPIVIU() extends Imm(5){ 563 override def do_toImm32(minBits: UInt): UInt = ZeroExt(minBits, 32) 564 565 override def minBitsFromInstr(instr: UInt): UInt = { 566 instr(19, 15) 567 } 568} 569 570case class Imm_VSETVLI() extends Imm(11){ 571 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 572 573 override def minBitsFromInstr(instr: UInt): UInt = { 574 instr(30, 20) 575 } 576} 577 578case class Imm_VSETIVLI() extends Imm(13){ 579 override def do_toImm32(minBits: UInt): UInt = SignExt(minBits, 32) 580 581 override def minBitsFromInstr(instr: UInt): UInt = { 582 val rvInst: XSInstBitFields = instr.asTypeOf(new XSInstBitFields) 583 val uimm5 = rvInst.UIMM_VSETIVLI 584 val vtype8 = rvInst.ZIMM_VTYPE 585 Cat(uimm5, vtype8) 586 } 587 /** 588 * get VType from extended imm 589 * @param extedImm 590 * @return VType 591 */ 592 def getVType(extedImm: UInt): InstVType = { 593 val vtype = Wire(new InstVType) 594 vtype := extedImm(7, 0).asTypeOf(new InstVType) 595 vtype 596 } 597 598 def getAvl(extedImm: UInt): UInt = { 599 extedImm(12, 8) 600 } 601} 602object ImmUnion { 603 val I = Imm_I() 604 val S = Imm_S() 605 val B = Imm_B() 606 val U = Imm_U() 607 val J = Imm_J() 608 val Z = Imm_Z() 609 val B6 = Imm_B6() 610 val OPIVIS = Imm_OPIVIS() 611 val OPIVIU = Imm_OPIVIU() 612 val VSETVLI = Imm_VSETVLI() 613 val VSETIVLI = Imm_VSETIVLI() 614 615 val imms = Seq(I, S, B, U, J, Z, B6, OPIVIS, OPIVIU, VSETVLI, VSETIVLI) 616 val maxLen = imms.maxBy(_.len).len 617 val immSelMap = Seq( 618 SelImm.IMM_I, 619 SelImm.IMM_S, 620 SelImm.IMM_SB, 621 SelImm.IMM_U, 622 SelImm.IMM_UJ, 623 SelImm.IMM_Z, 624 SelImm.IMM_B6, 625 SelImm.IMM_OPIVIS, 626 SelImm.IMM_OPIVIU, 627 SelImm.IMM_VSETVLI, 628 SelImm.IMM_VSETIVLI 629 ).zip(imms) 630 println(s"ImmUnion max len: $maxLen") 631} 632 633case class Imm_LUI_LOAD() { 634 def immFromLuiLoad(lui_imm: UInt, load_imm: UInt): UInt = { 635 val loadImm = load_imm(Imm_I().len - 1, 0) 636 Cat(lui_imm(Imm_U().len - loadImm.getWidth - 1, 0), loadImm) 637 } 638 def getLuiImm(uop: DynInst): UInt = { 639 val loadImmLen = Imm_I().len 640 val imm_u = Cat(uop.psrc(1), uop.psrc(0), uop.imm(ImmUnion.maxLen - 1, loadImmLen)) 641 Imm_U().do_toImm32(imm_u) 642 } 643} 644 645/** 646 * IO bundle for the Decode unit 647 */ 648class DecodeUnitIO(implicit p: Parameters) extends XSBundle { 649 val enq = new Bundle { 650 val ctrlFlow = Input(new StaticInst) 651 val vtype = Input(new VType) 652 } 653// val vconfig = Input(UInt(XLEN.W)) 654 val deq = new Bundle { 655 val decodedInst = Output(new DecodedInst) 656 val isComplex = Output(Bool()) 657 val uopInfo = Output(new UopInfo) 658 } 659 val csrCtrl = Input(new CustomCSRCtrlIO) 660} 661 662/** 663 * Decode unit that takes in a single CtrlFlow and generates a CfCtrl. 664 */ 665class DecodeUnit(implicit p: Parameters) extends XSModule with DecodeUnitConstants { 666 val io = IO(new DecodeUnitIO) 667 668 val ctrl_flow = io.enq.ctrlFlow // input with RVC Expanded 669 670 private val inst: XSInstBitFields = io.enq.ctrlFlow.instr.asTypeOf(new XSInstBitFields) 671 672 val decode_table: Array[(BitPat, List[BitPat])] = XDecode.table ++ 673 FpDecode.table ++ 674 FDivSqrtDecode.table ++ 675 X64Decode.table ++ 676 XSTrapDecode.table ++ 677 BDecode.table ++ 678 CBODecode.table ++ 679 SvinvalDecode.table ++ 680 VecDecoder.table 681 682 require(decode_table.map(_._2.length == 14).reduce(_ && _), "Decode tables have different column size") 683 // assertion for LUI: only LUI should be assigned `selImm === SelImm.IMM_U && fuType === FuType.alu` 684 val luiMatch = (t: Seq[BitPat]) => t(3).value == FuType.alu && t.reverse.head.value == SelImm.IMM_U.litValue 685 val luiTable = decode_table.filter(t => luiMatch(t._2)).map(_._1).distinct 686 assert(luiTable.length == 1 && luiTable.head == LUI, "Conflicts: LUI is determined by FuType and SelImm in Dispatch") 687 688 // output 689 val decodedInst: DecodedInst = Wire(new DecodedInst()).decode(ctrl_flow.instr, decode_table) 690 691 val fpDecoder = Module(new FPDecoder) 692 fpDecoder.io.instr := ctrl_flow.instr 693 decodedInst.fpu := fpDecoder.io.fpCtrl 694 695 decodedInst.connectStaticInst(io.enq.ctrlFlow) 696 697 decodedInst.uopIdx := 0.U 698 decodedInst.firstUop := true.B 699 decodedInst.lastUop := true.B 700 decodedInst.numUops := 1.U 701 702 val isMove = BitPat("b000000000000_?????_000_?????_0010011") === ctrl_flow.instr 703 decodedInst.isMove := isMove && inst.RD =/= 0.U 704 705 private val v0Idx = 0 706 private val vconfigIdx = VCONFIG_IDX 707 708 // read src1~3 location 709 decodedInst.lsrc(0) := inst.RS1 710 decodedInst.lsrc(1) := inst.RS2 711 decodedInst.lsrc(2) := inst.FS3 712 decodedInst.lsrc(3) := v0Idx.U 713 decodedInst.lsrc(4) := vconfigIdx.U 714 decodedInst.srcType(3) := Mux(inst.VM.asBool, SrcType.DC, SrcType.vp) // mask src 715 decodedInst.srcType(4) := SrcType.vp // vconfig 716 717 // cs.lsrc(2) := Mux(FuType.isVecExu(cs.fuType), ctrl_flow.instr(RD_MSB, RD_LSB), ctrl_flow.instr(RS3_MSB, RS3_LSB)) 718 // read dest location 719 decodedInst.ldest := inst.RD 720 721 // fill in exception vector 722 decodedInst.exceptionVec(illegalInstr) := decodedInst.selImm === SelImm.INVALID_INSTR 723 724 when (!io.csrCtrl.svinval_enable) { 725 val base_ii = decodedInst.selImm === SelImm.INVALID_INSTR 726 val sinval = BitPat("b0001011_?????_?????_000_00000_1110011") === ctrl_flow.instr 727 val w_inval = BitPat("b0001100_00000_00000_000_00000_1110011") === ctrl_flow.instr 728 val inval_ir = BitPat("b0001100_00001_00000_000_00000_1110011") === ctrl_flow.instr 729 val svinval_ii = sinval || w_inval || inval_ir 730 decodedInst.exceptionVec(illegalInstr) := base_ii || svinval_ii 731 decodedInst.flushPipe := false.B 732 } 733 734 // fix frflags 735 // fflags zero csrrs rd csr 736 val isFrflags = BitPat("b000000000001_00000_010_?????_1110011") === ctrl_flow.instr 737 when (decodedInst.fuType === FuType.csr.U && isFrflags) { 738 decodedInst.blockBackward := false.B 739 } 740 741 decodedInst.imm := LookupTree(decodedInst.selImm, ImmUnion.immSelMap.map( 742 x => { 743 val minBits = x._2.minBitsFromInstr(ctrl_flow.instr) 744 require(minBits.getWidth == x._2.len) 745 x._1 -> minBits 746 } 747 )) 748 749 decodedInst.commitType := 0.U // Todo: remove it 750 751 decodedInst.isVset := FuType.isVset(decodedInst.fuType) 752 753 private val needReverseInsts = Seq(VRSUB_VI, VRSUB_VX, VREM_VV, VREM_VX, VREMU_VV, VFRDIV_VF, VFRSUB_VF) 754 private val vextInsts = Seq(VZEXT_VF2, VZEXT_VF4, VZEXT_VF8, VSEXT_VF2, VSEXT_VF4, VSEXT_VF8) 755 private val narrowInsts = Seq( 756 VNSRA_WV, VNSRA_WX, VNSRA_WI, VNSRL_WV, VNSRL_WX, VNSRL_WI, 757 VNCLIP_WV, VNCLIP_WX, VNCLIP_WI, VNCLIPU_WV, VNCLIPU_WX, VNCLIPU_WI, 758 ) 759 private val maskDstInsts = Seq( 760 VMADC_VV, VMADC_VX, VMADC_VI, VMADC_VVM, VMADC_VXM, VMADC_VIM, 761 VMSBC_VV, VMSBC_VX, VMSBC_VVM, VMSBC_VXM, 762 VMAND_MM, VMNAND_MM, VMANDN_MM, VMXOR_MM, VMOR_MM, VMNOR_MM, VMORN_MM, VMXNOR_MM, 763 VMSEQ_VV, VMSEQ_VX, VMSEQ_VI, VMSNE_VV, VMSNE_VX, VMSNE_VI, 764 VMSLE_VV, VMSLE_VX, VMSLE_VI, VMSLEU_VV, VMSLEU_VX, VMSLEU_VI, 765 VMSLT_VV, VMSLT_VX, VMSLTU_VV, VMSLTU_VX, 766 VMSGT_VX, VMSGT_VI, VMSGTU_VX, VMSGTU_VI, 767 ) 768 769 decodedInst.vpu := 0.U.asTypeOf(decodedInst.vpu) // Todo: Connect vpu decoder 770 decodedInst.vpu.vill := io.enq.vtype.illegal 771 decodedInst.vpu.vma := io.enq.vtype.vma 772 decodedInst.vpu.vta := io.enq.vtype.vta 773 decodedInst.vpu.vsew := io.enq.vtype.vsew 774 decodedInst.vpu.vlmul := io.enq.vtype.vlmul 775 decodedInst.vpu.vm := inst.VM 776 decodedInst.vpu.nf := inst.NF 777 decodedInst.vpu.needScalaSrc := Category.needScalaSrc(inst.VCATEGORY) 778 decodedInst.vpu.isReverse := needReverseInsts.map(_ === inst.ALL).reduce(_ || _) 779 decodedInst.vpu.isExt := vextInsts.map(_ === inst.ALL).reduce(_ || _) 780 decodedInst.vpu.isNarrow := narrowInsts.map(_ === inst.ALL).reduce(_ || _) 781 decodedInst.vpu.isDstMask := maskDstInsts.map(_ === inst.ALL).reduce(_ || _) 782 783 val uopInfoGen = Module(new UopInfoGen) 784 uopInfoGen.io.in.preInfo.typeOfSplit := decodedInst.uopSplitType 785 uopInfoGen.io.in.preInfo.vsew := decodedInst.vpu.vsew 786 uopInfoGen.io.in.preInfo.vlmul := decodedInst.vpu.vlmul 787 uopInfoGen.io.in.preInfo.vwidth := inst.RM 788 io.deq.isComplex := uopInfoGen.io.out.isComplex 789 io.deq.uopInfo.numOfUop := uopInfoGen.io.out.uopInfo.numOfUop 790 io.deq.uopInfo.lmul := uopInfoGen.io.out.uopInfo.lmul 791 792 io.deq.decodedInst := decodedInst 793 794 //------------------------------------------------------------- 795 // Debug Info 796// XSDebug("in: instr=%x pc=%x excepVec=%b crossPageIPFFix=%d\n", 797// io.enq.ctrl_flow.instr, io.enq.ctrl_flow.pc, io.enq.ctrl_flow.exceptionVec.asUInt, 798// io.enq.ctrl_flow.crossPageIPFFix) 799// XSDebug("out: srcType(0)=%b srcType(1)=%b srcType(2)=%b lsrc(0)=%d lsrc(1)=%d lsrc(2)=%d ldest=%d fuType=%b fuOpType=%b\n", 800// io.deq.cf_ctrl.ctrl.srcType(0), io.deq.cf_ctrl.ctrl.srcType(1), io.deq.cf_ctrl.ctrl.srcType(2), 801// io.deq.cf_ctrl.ctrl.lsrc(0), io.deq.cf_ctrl.ctrl.lsrc(1), io.deq.cf_ctrl.ctrl.lsrc(2), 802// io.deq.cf_ctrl.ctrl.ldest, io.deq.cf_ctrl.ctrl.fuType, io.deq.cf_ctrl.ctrl.fuOpType) 803// XSDebug("out: rfWen=%d fpWen=%d isXSTrap=%d noSpecExec=%d isBlocked=%d flushPipe=%d imm=%x\n", 804// io.deq.cf_ctrl.ctrl.rfWen, io.deq.cf_ctrl.ctrl.fpWen, io.deq.cf_ctrl.ctrl.isXSTrap, 805// io.deq.cf_ctrl.ctrl.noSpecExec, io.deq.cf_ctrl.ctrl.blockBackward, io.deq.cf_ctrl.ctrl.flushPipe, 806// io.deq.cf_ctrl.ctrl.imm) 807// XSDebug("out: excepVec=%b\n", io.deq.cf_ctrl.cf.exceptionVec.asUInt) 808} 809