xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala (revision f58472d918089db6c63caf78f989f93438ca0ecc) 
1package xiangshan.backend
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility._
8import xiangshan._
9import xiangshan.backend.datapath.DataConfig.VAddrData
10import xiangshan.frontend.{FtqPtr, FtqToCtrlIO, Ftq_RF_Components}
11
12class PcTargetMem(params: BackendParams)(implicit p: Parameters) extends LazyModule {
13  override def shouldBeInlined: Boolean = false
14
15  lazy val module = new PcTargetMemImp(this)(p, params)
16}
17
18class PcTargetMemImp(override val wrapper: PcTargetMem)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper) with HasXSParameter {
19
20  require(params.numTargetReadPort == params.numPcMemReadPort, "The EXUs which need PC must be the same as the EXUs which need Target PC.")
21  private val numTargetMemRead = params.numTargetReadPort + params.numPcMemReadPort
22
23  val io = IO(new PcTargetMemIO())
24  private val readValid = io.toDataPath.fromDataPathValid
25
26  private def hasRen: Boolean = true
27  private val targetMem = Module(new SyncDataModuleTemplate(new Ftq_RF_Components, FtqSize, numTargetMemRead, 1, hasRen = hasRen))
28  private val targetPCVec : Vec[UInt] = Wire(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W)))
29  private val pcVec       : Vec[UInt] = Wire(Vec(params.numPcMemReadPort, UInt(VAddrData().dataWidth.W)))
30
31  targetMem.io.wen.head := GatedValidRegNext(io.fromFrontendFtq.pc_mem_wen)
32  targetMem.io.waddr.head := RegEnable(io.fromFrontendFtq.pc_mem_waddr, io.fromFrontendFtq.pc_mem_wen)
33  targetMem.io.wdata.head := RegEnable(io.fromFrontendFtq.pc_mem_wdata, io.fromFrontendFtq.pc_mem_wen)
34
35  private val newestEn: Bool = io.fromFrontendFtq.newest_entry_en
36  private val newestTarget: UInt = io.fromFrontendFtq.newest_entry_target
37  for (i <- 0 until params.numTargetReadPort) {
38    val targetPtr = io.toDataPath.fromDataPathFtqPtr(i)
39    // target pc stored in next entry
40    targetMem.io.ren.get(i) := readValid(i)
41    targetMem.io.raddr(i) := (targetPtr + 1.U).value
42    val needNewestTarget = RegEnable(targetPtr === io.fromFrontendFtq.newest_entry_ptr, false.B, newestEn && readValid(i))
43    targetPCVec(i) := Mux(
44      needNewestTarget,
45      RegEnable(newestTarget, newestEn),
46      targetMem.io.rdata(i).startAddr
47    )
48  }
49
50  for (i <- 0 until params.numPcMemReadPort) {
51    val pcAddr = io.toDataPath.fromDataPathFtqPtr(i)
52    val offset = io.toDataPath.fromDataPathFtqOffset(i)
53    // pc stored in this entry
54    targetMem.io.ren.get(i + params.numTargetReadPort) := readValid(i)
55    targetMem.io.raddr(i + params.numTargetReadPort) := pcAddr.value
56    pcVec(i) := targetMem.io.rdata(i + params.numTargetReadPort).getPc(RegEnable(offset, readValid(i)))
57  }
58
59  io.toDataPath.toDataPathTargetPC := targetPCVec
60  io.toDataPath.toDataPathPC := pcVec
61}
62
63class PcToDataPathIO(params: BackendParams)(implicit p: Parameters) extends XSBundle {
64  //Ftq
65  val fromDataPathValid = Input(Vec(params.numPcMemReadPort, Bool()))
66  val fromDataPathFtqPtr = Input(Vec(params.numPcMemReadPort, new FtqPtr))
67  val fromDataPathFtqOffset = Input(Vec(params.numPcMemReadPort, UInt(log2Up(PredictWidth).W)))
68  //Target PC
69  val toDataPathTargetPC = Output(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W)))
70  //PC
71  val toDataPathPC = Output(Vec(params.numPcMemReadPort, UInt(VAddrData().dataWidth.W)))
72}
73
74class PcTargetMemIO()(implicit p: Parameters, params: BackendParams) extends XSBundle {
75  //from frontend
76  val fromFrontendFtq = Flipped(new FtqToCtrlIO)
77  //to backend
78  val toDataPath = new PcToDataPathIO(params)
79}