xref: /XiangShan/src/main/scala/xiangshan/backend/datapath/PcTargetMem.scala (revision 3827c997022cef4e62036aee3a6da36e36225af4) 
1package xiangshan.backend
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util._
6import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
7import utility._
8import xiangshan._
9import xiangshan.backend.datapath.DataConfig.VAddrData
10import xiangshan.frontend.{FtqPtr, FtqToCtrlIO, Ftq_RF_Components}
11
12class PcTargetMem(params: BackendParams)(implicit p: Parameters) extends LazyModule {
13  override def shouldBeInlined: Boolean = false
14
15  lazy val module = new PcTargetMemImp(this)(p, params)
16}
17
18class PcTargetMemImp(override val wrapper: PcTargetMem)(implicit p: Parameters, params: BackendParams) extends LazyModuleImp(wrapper) with HasXSParameter {
19
20  private val numTargetMemRead = params.numTargetReadPort
21  val io = IO(new PcTargetMemIO())
22
23  private val targetMem = Module(new SyncDataModuleTemplate(UInt(VAddrData().dataWidth.W), FtqSize, numTargetMemRead, 1))
24  private val jumpTargetReadVec : Vec[UInt] = Wire(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W)))
25  private val jumpTargetVec     : Vec[UInt] = Wire(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W)))
26
27  targetMem.io.wen.head := RegNext(io.fromFrontendFtq.pc_mem_wen)
28  targetMem.io.waddr.head := RegEnable(io.fromFrontendFtq.pc_mem_waddr, io.fromFrontendFtq.pc_mem_wen)
29  targetMem.io.wdata.head := RegEnable(io.fromFrontendFtq.pc_mem_wdata.startAddr, io.fromFrontendFtq.pc_mem_wen)
30
31  private val newestTarget: UInt = io.fromFrontendFtq.newest_entry_target
32  for (i <- 0 until numTargetMemRead) {
33    val targetPtr = io.fromDataPathFtq(i)
34    // target pc stored in next entry
35    targetMem.io.raddr(i) := (targetPtr + 1.U).value
36    jumpTargetReadVec(i) := targetMem.io.rdata(i)
37    val needNewestTarget = RegNext(targetPtr === io.fromFrontendFtq.newest_entry_ptr)
38    jumpTargetVec(i) := Mux(
39      needNewestTarget,
40      RegNext(newestTarget),
41      jumpTargetReadVec(i)
42    )
43  }
44
45  io.toExus := jumpTargetVec
46
47}
48
49class PcTargetMemIO()(implicit p: Parameters, params: BackendParams) extends XSBundle {
50  //input
51  val fromFrontendFtq = Flipped(new FtqToCtrlIO)
52  val fromDataPathFtq = Input(Vec(params.numTargetReadPort, new FtqPtr))
53  //output
54  val toExus = Output(Vec(params.numTargetReadPort, UInt(VAddrData().dataWidth.W)))
55}