1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24} 25 26class CtrlToFpBlockIO extends XSBundle { 27 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 28 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 29 // fp block uses port 0~11 30 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 31 val redirect = ValidIO(new Redirect) 32} 33 34class CtrlToLsBlockIO extends XSBundle { 35 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 36 val enqLsq = Flipped(new LsqEnqIO) 37 val redirect = ValidIO(new Redirect) 38} 39 40class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 41 val io = IO(new Bundle() { 42 val loadRelay = Flipped(ValidIO(new Redirect)) 43 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 44 val roqRedirect = Flipped(ValidIO(new Redirect)) 45 val stage2FtqRead = new FtqRead 46 val stage2Redirect = ValidIO(new Redirect) 47 val stage3Redirect = ValidIO(new Redirect) 48 }) 49 /* 50 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 51 | | | | | | | 52 |============= reg & compare =====| | ======== 53 | | 54 | | 55 | | Stage2 56 | | 57 redirect (flush backend) | 58 | | 59 === reg === | ======== 60 | | 61 |----- mux (exception first) -----| Stage3 62 | 63 redirect (send to frontend) 64 */ 65 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 66 Mux(isAfter(x.bits, y.bits) && y.valid, y, x) 67 } 68 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 69 Mux(isAfter(x.bits.redirect, y.bits.redirect) && y.valid, y, x) 70 } 71 val jumpOut = io.exuMispredict.head 72 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 73 val oldestExuOut = selectOlderExuOut(oldestAluOut, jumpOut) // select between jump and alu 74 75 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 76 val redirect = Wire(Valid(new Redirect)) 77 redirect.valid := oldestExuOut.valid 78 redirect.bits := oldestExuOut.bits.redirect 79 redirect 80 }) 81 82 val s1_isJalr = RegEnable(JumpOpType.jumpOpisJalr(jumpOut.bits.uop.ctrl.fuOpType), jumpOut.valid) 83 val s1_JalrTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 84 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 85 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 86 val s1_redirect_bits_reg = Reg(new Redirect) 87 val s1_redirect_valid_reg = RegInit(false.B) 88 89 // stage1 -> stage2 90 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect)){ 91 s1_redirect_bits_reg := oldestMispredict.bits 92 s1_redirect_valid_reg := true.B 93 }.otherwise({ 94 s1_redirect_valid_reg := false.B 95 }) 96 io.stage2Redirect.valid := s1_redirect_valid_reg 97 io.stage2Redirect.bits := s1_redirect_bits_reg 98 io.stage2Redirect.bits.cfiUpdate := DontCare 99 // at stage2, we read ftq to get pc 100 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 101 102 // stage3, calculate redirect target 103 val s2_isJalr = RegEnable(s1_isJalr, s1_redirect_valid_reg) 104 val s2_JalrTarget = RegEnable(s1_JalrTarget, s1_redirect_valid_reg) 105 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 106 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 107 val s2_redirect_bits_reg = Reg(new Redirect) 108 val s2_redirect_valid_reg = RegInit(false.B) 109 110 val ftqRead = io.stage2FtqRead.entry 111 val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset) 112 val brTarget = pc + SignExt(s2_imm12_reg, XLEN) 113 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 114 val target = Mux(isReplay, 115 pc, // repaly from itself 116 Mux(s2_isJalr, 117 s2_JalrTarget, // jalr already save target 118 brTarget // branch 119 ) 120 ) 121 io.stage3Redirect.valid := s2_redirect_valid_reg 122 io.stage3Redirect.bits := s2_redirect_bits_reg 123 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 124 stage3CfiUpdate.pc := pc 125 stage3CfiUpdate.pd := s2_pd 126 stage3CfiUpdate.rasSp := ftqRead.rasSp 127 stage3CfiUpdate.rasEntry := ftqRead.rasTop 128 stage3CfiUpdate.hist := ftqRead.hist 129 stage3CfiUpdate.predHist := ftqRead.predHist 130 stage3CfiUpdate.specCnt := ftqRead.specCnt 131 stage3CfiUpdate.predTaken := 132 ftqRead.cfiIndex.valid && s2_redirect_bits_reg.ftqOffset === ftqRead.cfiIndex.bits 133 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 134 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i-1)).orR() 135 })(s2_redirect_bits_reg.ftqOffset) 136 stage3CfiUpdate.target := target 137 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 138 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 139} 140 141class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 142 val io = IO(new Bundle { 143 val frontend = Flipped(new FrontendToBackendIO) 144 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 145 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 146 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 147 val toIntBlock = new CtrlToIntBlockIO 148 val toFpBlock = new CtrlToFpBlockIO 149 val toLsBlock = new CtrlToLsBlockIO 150 val roqio = new Bundle { 151 // to int block 152 val toCSR = new RoqCSRIO 153 val exception = ValidIO(new MicroOp) 154 val isInterrupt = Output(Bool()) 155 // to mem block 156 val commits = new RoqCommitIO 157 val roqDeqPtr = Output(new RoqPtr) 158 } 159 }) 160 161 val ftq = Module(new Ftq) 162 val decode = Module(new DecodeStage) 163 val rename = Module(new Rename) 164 val dispatch = Module(new Dispatch) 165 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 166 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 167 val redirectGen = Module(new RedirectGenerator) 168 169 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 170 171 val roq = Module(new Roq(roqWbSize)) 172 173 val backendRedirect = redirectGen.io.stage2Redirect 174 val frontendRedirect = redirectGen.io.stage3Redirect 175 176 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 177 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 178 x.bits := y.bits 179 }) 180 redirectGen.io.loadRelay := io.fromLsBlock.replay 181 redirectGen.io.roqRedirect := roq.io.redirectOut 182 183 ftq.io.enq <> io.frontend.fetchInfo 184 for(i <- 0 until CommitWidth){ 185 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) 186 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 187 } 188 ftq.io.redirect <> backendRedirect 189 ftq.io.frontendRedirect <> frontendRedirect 190 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 191 192 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 193 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 194 195 io.frontend.redirect_cfiUpdate := frontendRedirect 196 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 197 198 decode.io.in <> io.frontend.cfVec 199 200 val jumpInst = dispatch.io.enqIQCtrl(0).bits 201 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 202 io.toIntBlock.jumpPc := GetPcByFtq(ftq.io.ftqRead(0).entry.ftqPC, jumpInst.cf.ftqOffset) 203 204 // pipeline between decode and dispatch 205 for (i <- 0 until RenameWidth) { 206 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 207 backendRedirect.valid || frontendRedirect.valid) 208 } 209 210 rename.io.redirect <> backendRedirect 211 rename.io.roqCommits <> roq.io.commits 212 rename.io.out <> dispatch.io.fromRename 213 rename.io.renameBypass <> dispatch.io.renameBypass 214 215 dispatch.io.redirect <> backendRedirect 216 dispatch.io.enqRoq <> roq.io.enq 217 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 218 dispatch.io.readIntRf <> io.toIntBlock.readRf 219 dispatch.io.readFpRf <> io.toFpBlock.readRf 220 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 221 intBusyTable.io.allocPregs(i).valid := preg.isInt 222 fpBusyTable.io.allocPregs(i).valid := preg.isFp 223 intBusyTable.io.allocPregs(i).bits := preg.preg 224 fpBusyTable.io.allocPregs(i).bits := preg.preg 225 } 226 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 227 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 228// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 229 230 231 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 232 fpBusyTable.io.flush := flush 233 intBusyTable.io.flush := flush 234 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 235 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 236 setPhyRegRdy.bits := wb.bits.uop.pdest 237 } 238 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 239 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 240 setPhyRegRdy.bits := wb.bits.uop.pdest 241 } 242 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 243 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 244 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 245 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 246 247 roq.io.redirect <> backendRedirect 248 roq.io.exeWbResults.zip( 249 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 250 ).foreach{ 251 case(x, y) => 252 x.bits := y.bits 253 x.valid := y.valid 254 } 255 256 // TODO: is 'backendRedirect' necesscary? 257 io.toIntBlock.redirect <> backendRedirect 258 io.toFpBlock.redirect <> backendRedirect 259 io.toLsBlock.redirect <> backendRedirect 260 261 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 262 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 263 264 // roq to int block 265 io.roqio.toCSR <> roq.io.csr 266 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 267 io.roqio.exception.bits := roq.io.exception 268 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 269 // roq to mem block 270 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 271 io.roqio.commits := roq.io.commits 272} 273