1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend.decode.{DecodeStage, ImmUnion} 24import xiangshan.backend.rename.{BusyTable, Rename} 25import xiangshan.backend.dispatch.Dispatch 26import xiangshan.backend.exu._ 27import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr, CfiInfoToCtrl} 28import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 29import xiangshan.mem.LsqEnqIO 30 31 32class CtrlToIntBlockIO(implicit p: Parameters) extends XSBundle { 33 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 34 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 35 val jumpPc = Output(UInt(VAddrBits.W)) 36 val jalr_target = Output(UInt(VAddrBits.W)) 37 // int block only uses port 0~7 38 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 39 val redirect = ValidIO(new Redirect) 40 val flush = Output(Bool()) 41 val debug_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 42} 43 44class CtrlToFpBlockIO(implicit p: Parameters) extends XSBundle { 45 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 46 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 47 // fp block uses port 0~11 48 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 49 val redirect = ValidIO(new Redirect) 50 val flush = Output(Bool()) 51 val debug_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 52} 53 54class CtrlToLsBlockIO(implicit p: Parameters) extends XSBundle { 55 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 56 val enqLsq = Flipped(new LsqEnqIO) 57 val memPredUpdate = Vec(StorePipelineWidth, Input(new MemPredUpdateReq)) 58 val redirect = ValidIO(new Redirect) 59 val flush = Output(Bool()) 60} 61 62class CtrlToFtqIO(implicit p: Parameters) extends XSBundle { 63 val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo)) 64 val stage2Redirect = Valid(new Redirect) 65 val roqFlush = Valid(new Bundle { 66 val ftqIdx = Output(new FtqPtr) 67 val ftqOffset = Output(UInt(log2Up(PredictWidth).W)) 68 }) 69 70 val exuWriteback = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Valid(new ExuOutput)) 71 val loadReplay = Valid(new Redirect) 72 val stage3Redirect = ValidIO(new Redirect) 73} 74 75class RedirectGenerator(implicit p: Parameters) extends XSModule 76 with HasCircularQueuePtrHelper { 77 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 78 val io = IO(new Bundle() { 79 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 80 val loadReplay = Flipped(ValidIO(new Redirect)) 81 val flush = Input(Bool()) 82 val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W))) 83 val stage1CfiRead = Vec(numRedirect+1, new FtqRead(new CfiInfoToCtrl)) 84 val stage2Redirect = ValidIO(new Redirect) 85 val stage3Redirect = ValidIO(new Redirect) 86 val memPredUpdate = Output(new MemPredUpdateReq) 87 val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2 88 }) 89 /* 90 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 91 | | | | | | | 92 |============= reg & compare =====| | ======== 93 | | 94 | | 95 | | Stage2 96 | | 97 redirect (flush backend) | 98 | | 99 === reg === | ======== 100 | | 101 |----- mux (exception first) -----| Stage3 102 | 103 redirect (send to frontend) 104 */ 105 private class Wrapper(val n: Int) extends Bundle { 106 val redirect = new Redirect 107 val valid = Bool() 108 val idx = UInt(log2Up(n).W) 109 } 110 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 111 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 112 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 113 (if (j < i) !xs(j).valid || compareVec(i)(j) 114 else if (j == i) xs(i).valid 115 else !xs(j).valid || !compareVec(j)(i)) 116 )).andR)) 117 resultOnehot 118 } 119 120 val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 121 val stage1FtqReadPcs = 122 (io.stage1PcRead zip redirects).map{ case (r: FtqRead[UInt], redirect: Redirect) => 123 r(redirect.ftqIdx, redirect.ftqOffset) 124 } 125 126 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 127 val redirect = Wire(Valid(new Redirect)) 128 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 129 redirect.bits := exuOut.bits.redirect 130 redirect 131 } 132 133 val jumpOut = io.exuMispredict.head 134 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 135 val oldestOneHot = selectOldestRedirect(allRedirect) 136 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 137 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 138 val oldestExuOutput = Mux1H((0 until 5).map(oldestOneHot), io.exuMispredict) 139 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 140 141 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 142 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 143 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 144 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 145 val s1_redirect_valid_reg = RegNext(oldestValid) 146 val s1_redirect_onehot = RegNext(oldestOneHot) 147 148 // stage1 -> stage2 149 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 150 io.stage2Redirect.bits := s1_redirect_bits_reg 151 io.stage2Redirect.bits.cfiUpdate := DontCare 152 153 val s1_isReplay = s1_redirect_onehot(5) 154 val s1_isJump = s1_redirect_onehot(0) 155 val cfiRead = Mux1H(s1_redirect_onehot, io.stage1CfiRead) 156 val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs) 157 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 158 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 159 val target = Mux(s1_isReplay, 160 real_pc, // repaly from itself 161 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 162 Mux(s1_isJump, s1_jumpTarget, brTarget), 163 snpc 164 ) 165 ) 166 167 // get pc from ftq 168 // valid only if redirect is caused by load violation 169 // store_pc is used to update store set 170 val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset) 171 172 // update load violation predictor if load violation redirect triggered 173 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 174 // update wait table 175 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 176 io.memPredUpdate.wdata := true.B 177 // update store set 178 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 179 // store pc is ready 1 cycle after s1_isReplay is judged 180 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 181 182 val s2_br_mask = RegEnable(cfiRead.data.br_mask, enable = s1_redirect_valid_reg) 183 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 184 if(i == 0) false.B else Cat(cfiRead.data.br_mask.take(i)).orR() 185 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 186 val s2_hist = RegEnable(cfiRead.data.hist, enable = s1_redirect_valid_reg) 187 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 188 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 189 val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg) 190 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 191 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 192 193 io.stage3Redirect.valid := s2_redirect_valid_reg 194 io.stage3Redirect.bits := s2_redirect_bits_reg 195 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 196 stage3CfiUpdate.pc := s2_pc 197 stage3CfiUpdate.pd := s2_pd 198 // stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 199 // stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 200 // stage3CfiUpdate.predHist := s2_ftqRead.predHist 201 // stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 202 stage3CfiUpdate.hist := s2_hist 203 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 204 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 205 stage3CfiUpdate.target := s2_target 206 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 207 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 208} 209 210class CtrlBlock(implicit p: Parameters) extends XSModule 211 with HasCircularQueuePtrHelper { 212 val io = IO(new Bundle { 213 val frontend = Flipped(new FrontendToCtrlIO) 214 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 215 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 216 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 217 val toIntBlock = new CtrlToIntBlockIO 218 val toFpBlock = new CtrlToFpBlockIO 219 val toLsBlock = new CtrlToLsBlockIO 220 val roqio = new Bundle { 221 // to int block 222 val toCSR = new RoqCSRIO 223 val exception = ValidIO(new ExceptionInfo) 224 // to mem block 225 val lsq = new RoqLsqIO 226 } 227 val csrCtrl = Input(new CustomCSRCtrlIO) 228 val perfInfo = Output(new Bundle{ 229 val ctrlInfo = new Bundle { 230 val roqFull = Input(Bool()) 231 val intdqFull = Input(Bool()) 232 val fpdqFull = Input(Bool()) 233 val lsdqFull = Input(Bool()) 234 } 235 }) 236 }) 237 238 val decode = Module(new DecodeStage) 239 val rename = Module(new Rename) 240 val dispatch = Module(new Dispatch) 241 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 242 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 243 val redirectGen = Module(new RedirectGenerator) 244 245 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 246 val roq = Module(new Roq(roqWbSize)) 247 248 val stage2Redirect = redirectGen.io.stage2Redirect 249 val stage3Redirect = redirectGen.io.stage3Redirect 250 val flush = roq.io.flushOut.valid 251 val flushReg = RegNext(flush) 252 253 val exuRedirect = io.fromIntBlock.exuRedirect.map(x => { 254 val valid = x.valid && x.bits.redirectValid 255 val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg) 256 val delayed = Wire(Valid(new ExuOutput)) 257 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 258 delayed.bits := RegEnable(x.bits, x.valid) 259 delayed 260 }) 261 val loadReplay = Wire(Valid(new Redirect)) 262 loadReplay.valid := RegNext(io.fromLsBlock.replay.valid && 263 !io.fromLsBlock.replay.bits.roqIdx.needFlush(stage2Redirect, flushReg), 264 init = false.B 265 ) 266 loadReplay.bits := RegEnable(io.fromLsBlock.replay.bits, io.fromLsBlock.replay.valid) 267 io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead 268 io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead 269 redirectGen.io.exuMispredict <> exuRedirect 270 redirectGen.io.loadReplay <> loadReplay 271 redirectGen.io.flush := flushReg 272 273 for(i <- 0 until CommitWidth){ 274 io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 275 io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i) 276 } 277 io.frontend.toFtq.stage2Redirect <> stage2Redirect 278 io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut) 279 io.frontend.toFtq.stage3Redirect <> stage3Redirect 280 io.frontend.toFtq.exuWriteback <> exuRedirect 281 io.frontend.toFtq.loadReplay <> loadReplay 282 283 val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead 284 val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset) 285 286 val flushRedirect = Wire(Valid(new Redirect)) 287 flushRedirect.valid := flushReg 288 flushRedirect.bits := DontCare 289 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 290 flushRedirect.bits.interrupt := true.B 291 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 292 io.roqio.toCSR.trapTarget, 293 flushPC + 4.U // flush pipe 294 ) 295 val flushRedirectReg = Wire(Valid(new Redirect)) 296 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 297 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 298 299 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect) 300 301 decode.io.in <> io.frontend.cfVec 302 // currently, we only update wait table when isReplay 303 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 304 decode.io.memPredUpdate(1) := DontCare 305 decode.io.memPredUpdate(1).valid := false.B 306 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 307 decode.io.csrCtrl := RegNext(io.csrCtrl) 308 309 310 val jumpInst = dispatch.io.enqIQCtrl(0).bits 311 val jumpPcRead = io.frontend.fromFtq.getJumpPcRead 312 io.toIntBlock.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 313 val jumpTargetRead = io.frontend.fromFtq.target_read 314 io.toIntBlock.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 315 316 // pipeline between decode and dispatch 317 for (i <- 0 until RenameWidth) { 318 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 319 flushReg || io.frontend.redirect_cfiUpdate.valid) 320 } 321 322 rename.io.redirect <> stage2Redirect 323 rename.io.flush := flushReg 324 rename.io.roqCommits <> roq.io.commits 325 rename.io.out <> dispatch.io.fromRename 326 rename.io.renameBypass <> dispatch.io.renameBypass 327 rename.io.dispatchInfo <> dispatch.io.preDpInfo 328 rename.io.csrCtrl <> RegNext(io.csrCtrl) 329 330 dispatch.io.redirect <> stage2Redirect 331 dispatch.io.flush := flushReg 332 dispatch.io.enqRoq <> roq.io.enq 333 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 334 dispatch.io.readIntRf <> io.toIntBlock.readRf 335 dispatch.io.readFpRf <> io.toFpBlock.readRf 336 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 337 intBusyTable.io.allocPregs(i).valid := preg.isInt 338 fpBusyTable.io.allocPregs(i).valid := preg.isFp 339 intBusyTable.io.allocPregs(i).bits := preg.preg 340 fpBusyTable.io.allocPregs(i).bits := preg.preg 341 } 342 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 343 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 344// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 345 dispatch.io.csrCtrl <> io.csrCtrl 346 dispatch.io.storeIssue <> io.fromLsBlock.stIn 347 348 349 fpBusyTable.io.flush := flushReg 350 intBusyTable.io.flush := flushReg 351 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 352 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 353 setPhyRegRdy.bits := wb.bits.uop.pdest 354 } 355 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 356 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 357 setPhyRegRdy.bits := wb.bits.uop.pdest 358 } 359 intBusyTable.io.read <> dispatch.io.readIntState 360 fpBusyTable.io.read <> dispatch.io.readFpState 361 362 roq.io.redirect <> stage2Redirect 363 val exeWbResults = VecInit(io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut) 364 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 365 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)) 366 roq_wb.bits := RegNext(wb.bits) 367 } 368 369 // TODO: is 'stage2Redirect' necesscary? 370 io.toIntBlock.redirect <> stage2Redirect 371 io.toIntBlock.flush <> flushReg 372 io.toIntBlock.debug_rat <> rename.io.debug_int_rat 373 io.toFpBlock.redirect <> stage2Redirect 374 io.toFpBlock.flush <> flushReg 375 io.toFpBlock.debug_rat <> rename.io.debug_fp_rat 376 io.toLsBlock.redirect <> stage2Redirect 377 io.toLsBlock.flush <> flushReg 378 379 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 380 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 381 382 // roq to int block 383 io.roqio.toCSR <> roq.io.csr 384 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 385 io.roqio.exception := roq.io.exception 386 io.roqio.exception.bits.uop.cf.pc := flushPC 387 // roq to mem block 388 io.roqio.lsq <> roq.io.lsq 389 390 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 391 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 392 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 393 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 394} 395