1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend.decode.{DecodeStage, ImmUnion} 24import xiangshan.backend.rename.{BusyTable, Rename} 25import xiangshan.backend.dispatch.Dispatch 26import xiangshan.backend.exu._ 27import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr, CfiInfoToCtrl} 28import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 29import xiangshan.mem.LsqEnqIO 30 31class CtrlToFtqIO(implicit p: Parameters) extends XSBundle { 32 val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo)) 33 val stage2Redirect = Valid(new Redirect) 34 val roqFlush = Valid(new Bundle { 35 val ftqIdx = Output(new FtqPtr) 36 val ftqOffset = Output(UInt(log2Up(PredictWidth).W)) 37 }) 38 39 val exuWriteback = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Valid(new ExuOutput)) 40 val loadReplay = Valid(new Redirect) 41 val stage3Redirect = ValidIO(new Redirect) 42} 43 44class RedirectGenerator(implicit p: Parameters) extends XSModule 45 with HasCircularQueuePtrHelper { 46 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 47 val io = IO(new Bundle() { 48 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 49 val loadReplay = Flipped(ValidIO(new Redirect)) 50 val flush = Input(Bool()) 51 val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W))) 52 val stage1CfiRead = Vec(numRedirect+1, new FtqRead(new CfiInfoToCtrl)) 53 val stage2Redirect = ValidIO(new Redirect) 54 val stage3Redirect = ValidIO(new Redirect) 55 val memPredUpdate = Output(new MemPredUpdateReq) 56 val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2 57 }) 58 /* 59 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 60 | | | | | | | 61 |============= reg & compare =====| | ======== 62 | | 63 | | 64 | | Stage2 65 | | 66 redirect (flush backend) | 67 | | 68 === reg === | ======== 69 | | 70 |----- mux (exception first) -----| Stage3 71 | 72 redirect (send to frontend) 73 */ 74 private class Wrapper(val n: Int) extends Bundle { 75 val redirect = new Redirect 76 val valid = Bool() 77 val idx = UInt(log2Up(n).W) 78 } 79 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 80 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 81 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 82 (if (j < i) !xs(j).valid || compareVec(i)(j) 83 else if (j == i) xs(i).valid 84 else !xs(j).valid || !compareVec(j)(i)) 85 )).andR)) 86 resultOnehot 87 } 88 89 val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 90 val stage1FtqReadPcs = 91 (io.stage1PcRead zip redirects).map{ case (r, redirect) => 92 r(redirect.ftqIdx, redirect.ftqOffset) 93 } 94 val stage1FtqReadCfis = 95 (io.stage1CfiRead zip redirects).map{ case (r, redirect) => 96 r(redirect.ftqIdx, redirect.ftqOffset) 97 } 98 val stage1FtqReadCfis = 99 (io.stage1CfiRead zip redirects).map{ case (r: FtqRead[CfiInfoToCtrl], redirect: Redirect) => 100 r(redirect.ftqIdx, redirect.ftqOffset) 101 } 102 103 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 104 val redirect = Wire(Valid(new Redirect)) 105 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 106 redirect.bits := exuOut.bits.redirect 107 redirect 108 } 109 110 val jumpOut = io.exuMispredict.head 111 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 112 val oldestOneHot = selectOldestRedirect(allRedirect) 113 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 114 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 115 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 116 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 117 118 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 119 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 120 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 121 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 122 val s1_redirect_valid_reg = RegNext(oldestValid) 123 val s1_redirect_onehot = RegNext(oldestOneHot) 124 125 // stage1 -> stage2 126 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 127 io.stage2Redirect.bits := s1_redirect_bits_reg 128 io.stage2Redirect.bits.cfiUpdate := DontCare 129 130 val s1_isReplay = s1_redirect_onehot.last 131 val s1_isJump = s1_redirect_onehot.head 132 val cfiRead = Mux1H(s1_redirect_onehot, stage1FtqReadCfis) 133 val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs) 134 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 135 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 136 val target = Mux(s1_isReplay, 137 real_pc, // repaly from itself 138 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 139 Mux(s1_isJump, s1_jumpTarget, brTarget), 140 snpc 141 ) 142 ) 143 144 // get pc from ftq 145 // valid only if redirect is caused by load violation 146 // store_pc is used to update store set 147 val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset) 148 149 // update load violation predictor if load violation redirect triggered 150 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 151 // update wait table 152 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 153 io.memPredUpdate.wdata := true.B 154 // update store set 155 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 156 // store pc is ready 1 cycle after s1_isReplay is judged 157 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 158 159 val s2_br_mask = RegEnable(cfiRead.br_mask, enable = s1_redirect_valid_reg) 160 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 161 if(i == 0) false.B else Cat(cfiRead.br_mask.take(i)).orR() 162 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 163 val s2_hist = RegEnable(cfiRead.hist, enable = s1_redirect_valid_reg) 164 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 165 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 166 val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg) 167 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 168 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 169 170 io.stage3Redirect.valid := s2_redirect_valid_reg 171 io.stage3Redirect.bits := s2_redirect_bits_reg 172 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 173 stage3CfiUpdate.pc := s2_pc 174 stage3CfiUpdate.pd := s2_pd 175 // stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 176 // stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 177 // stage3CfiUpdate.predHist := s2_ftqRead.predHist 178 // stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 179 stage3CfiUpdate.hist := s2_hist 180 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 181 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 182 stage3CfiUpdate.target := s2_target 183 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 184 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 185} 186 187class CtrlBlock(implicit p: Parameters) extends XSModule 188 with HasCircularQueuePtrHelper { 189 val io = IO(new Bundle { 190 val frontend = Flipped(new FrontendToCtrlIO) 191 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 192 // from int block 193 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 194 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 195 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 196 val memoryViolation = Flipped(ValidIO(new Redirect)) 197 val enqLsq = Flipped(new LsqEnqIO) 198 val jumpPc = Output(UInt(VAddrBits.W)) 199 val jalr_target = Output(UInt(VAddrBits.W)) 200 val roqio = new Bundle { 201 // to int block 202 val toCSR = new RoqCSRIO 203 val exception = ValidIO(new ExceptionInfo) 204 // to mem block 205 val lsq = new RoqLsqIO 206 } 207 val csrCtrl = Input(new CustomCSRCtrlIO) 208 val perfInfo = Output(new Bundle{ 209 val ctrlInfo = new Bundle { 210 val roqFull = Input(Bool()) 211 val intdqFull = Input(Bool()) 212 val fpdqFull = Input(Bool()) 213 val lsdqFull = Input(Bool()) 214 } 215 }) 216 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 217 // redirect out 218 val redirect = ValidIO(new Redirect) 219 val flush = Output(Bool()) 220 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 221 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 222 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 223 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 224 }) 225 226 val decode = Module(new DecodeStage) 227 val rename = Module(new Rename) 228 val dispatch = Module(new Dispatch) 229 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 230 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 231 val redirectGen = Module(new RedirectGenerator) 232 233 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 234 val roq = Module(new Roq(roqWbSize)) 235 236 val stage2Redirect = redirectGen.io.stage2Redirect 237 val stage3Redirect = redirectGen.io.stage3Redirect 238 val flush = roq.io.flushOut.valid 239 val flushReg = RegNext(flush) 240 241 val exuRedirect = io.exuRedirect.map(x => { 242 val valid = x.valid && x.bits.redirectValid 243 val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg) 244 val delayed = Wire(Valid(new ExuOutput)) 245 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 246 delayed.bits := RegEnable(x.bits, x.valid) 247 delayed 248 }) 249 val loadReplay = Wire(Valid(new Redirect)) 250 loadReplay.valid := RegNext(io.memoryViolation.valid && 251 !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg), 252 init = false.B 253 ) 254 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 255 io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead 256 io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead 257 io.frontend.fromFtq.cfi_reads <> redirectGen.io.stage1CfiRead 258 redirectGen.io.exuMispredict <> exuRedirect 259 redirectGen.io.loadReplay <> loadReplay 260 redirectGen.io.flush := flushReg 261 262 for(i <- 0 until CommitWidth){ 263 io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 264 io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i) 265 } 266 io.frontend.toFtq.stage2Redirect <> stage2Redirect 267 io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut) 268 io.frontend.toFtq.stage3Redirect <> stage3Redirect 269 io.frontend.toFtq.exuWriteback <> exuRedirect 270 io.frontend.toFtq.loadReplay <> loadReplay 271 272 val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead 273 val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset) 274 275 val flushRedirect = Wire(Valid(new Redirect)) 276 flushRedirect.valid := flushReg 277 flushRedirect.bits := DontCare 278 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 279 flushRedirect.bits.interrupt := true.B 280 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 281 io.roqio.toCSR.trapTarget, 282 flushPC + 4.U // flush pipe 283 ) 284 val flushRedirectReg = Wire(Valid(new Redirect)) 285 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 286 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 287 288 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect) 289 290 decode.io.in <> io.frontend.cfVec 291 // currently, we only update wait table when isReplay 292 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 293 decode.io.memPredUpdate(1) := DontCare 294 decode.io.memPredUpdate(1).valid := false.B 295 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 296 decode.io.csrCtrl := RegNext(io.csrCtrl) 297 298 299 val jumpInst = dispatch.io.enqIQCtrl(0).bits 300 val jumpPcRead = io.frontend.fromFtq.getJumpPcRead 301 io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 302 val jumpTargetRead = io.frontend.fromFtq.target_read 303 io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 304 305 // pipeline between decode and dispatch 306 for (i <- 0 until RenameWidth) { 307 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 308 flushReg || io.frontend.redirect_cfiUpdate.valid) 309 } 310 311 rename.io.redirect <> stage2Redirect 312 rename.io.flush := flushReg 313 rename.io.roqCommits <> roq.io.commits 314 rename.io.out <> dispatch.io.fromRename 315 rename.io.renameBypass <> dispatch.io.renameBypass 316 rename.io.dispatchInfo <> dispatch.io.preDpInfo 317 rename.io.csrCtrl <> RegNext(io.csrCtrl) 318 319 dispatch.io.redirect <> stage2Redirect 320 dispatch.io.flush := flushReg 321 dispatch.io.enqRoq <> roq.io.enq 322 dispatch.io.enqLsq <> io.enqLsq 323 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 324 intBusyTable.io.allocPregs(i).valid := preg.isInt 325 fpBusyTable.io.allocPregs(i).valid := preg.isFp 326 intBusyTable.io.allocPregs(i).bits := preg.preg 327 fpBusyTable.io.allocPregs(i).bits := preg.preg 328 } 329 dispatch.io.enqIQCtrl := DontCare 330 io.enqIQ <> dispatch.io.enqIQCtrl 331 dispatch.io.csrCtrl <> io.csrCtrl 332 dispatch.io.storeIssue <> io.stIn 333 dispatch.io.readIntRf <> io.readIntRf 334 dispatch.io.readFpRf <> io.readFpRf 335 336 fpBusyTable.io.flush := flushReg 337 intBusyTable.io.flush := flushReg 338 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 339 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 340 setPhyRegRdy.bits := wb.bits.uop.pdest 341 } 342 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 343 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 344 setPhyRegRdy.bits := wb.bits.uop.pdest 345 } 346 intBusyTable.io.read <> dispatch.io.readIntState 347 fpBusyTable.io.read <> dispatch.io.readFpState 348 349 roq.io.redirect <> stage2Redirect 350 val exeWbResults = VecInit(io.writeback ++ io.stOut) 351 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 352 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)) 353 roq_wb.bits := RegNext(wb.bits) 354 } 355 356 // TODO: is 'backendRedirect' necesscary? 357 io.redirect <> stage2Redirect 358 io.flush <> flushReg 359 io.debug_int_rat <> rename.io.debug_int_rat 360 io.debug_fp_rat <> rename.io.debug_fp_rat 361 362// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 363// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 364 365 // roq to int block 366 io.roqio.toCSR <> roq.io.csr 367 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 368 io.roqio.exception := roq.io.exception 369 io.roqio.exception.bits.uop.cf.pc := flushPC 370 // roq to mem block 371 io.roqio.lsq <> roq.io.lsq 372 373 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 374 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 375 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 376 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 377} 378