1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27} 28 29class CtrlToLsBlockIO extends XSBundle { 30 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 31 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 32 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 33} 34 35class CtrlBlock extends XSModule { 36 val io = IO(new Bundle { 37 val frontend = Flipped(new FrontendToBackendIO) 38 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 39 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 40 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 41 val toIntBlock = new CtrlToIntBlockIO 42 val toFpBlock = new CtrlToFpBlockIO 43 val toLsBlock = new CtrlToLsBlockIO 44 }) 45 46 val decode = Module(new DecodeStage) 47 val brq = Module(new Brq) 48 val decBuf = Module(new DecodeBuffer) 49 val rename = Module(new Rename) 50 val dispatch = Module(new Dispatch( 51 jmpExeUnit.config, aluExeUnits(0).config, mduExeUnits(0).config, 52 fmacExeUnits(0).config, fmiscExeUnits(0).config, 53 ldExeUnitCfg, stExeUnitCfg 54 )) 55 // TODO: move busyTable to dispatch1 56 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 57 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 58 val roq = Module(new Roq) 59 60 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 61 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 62 63 val redirect = Mux( 64 roq.io.redirect.valid, 65 roq.io.redirect, 66 Mux( 67 brq.io.redirect.valid, 68 brq.io.redirect, 69 io.fromLsBlock.replay 70 ) 71 ) 72 73 decode.io.in <> io.frontend.cfVec 74 decode.io.toBrq <> brq.io.enqReqs 75 decode.io.brTags <> brq.io.brTags 76 decode.io.out <> decBuf.io.in 77 78 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 79 decBuf.io.redirect <> redirect 80 decBuf.io.out <> rename.io.in 81 82 rename.io.redirect <> redirect 83 rename.io.roqCommits <> roq.io.commits 84 // they should be moved to busytables 85 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 86 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 87 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 88 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 89 rename.io.intPregRdy <> dispatch.io.intPregRdy 90 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 91 rename.io.replayPregReq <> dispatch.io.replayPregReq 92 rename.io.out <> dispatch.io.fromRename 93 94 dispatch.io.redirect <> redirect 95 dispatch.io.toRoq <> roq.io.dp1Req 96 dispatch.io.roqIdxs <> roq.io.roqIdxs 97 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 98 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 99 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 100 dispatch.io.dequeueRoqIndex.bits = Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 101 dispatch.io.readIntRf <> io.toIntBlock.rfReadPorts 102 dispatch.io.readFpRf <> io.toFpBlock.rfReadPorts 103 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 104 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIQCtrl ++ io.toFpBlock.enqIQCtrl ++ io.toLsBlock.enqIQCtrl 105 dispatch.io.enqIqData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 106 107 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 108 // fpBusyTable.flush := flush 109 // intBusyTable.flush := flush 110 // busytable io 111 // maybe update busytable in dispatch1? 112 113} 114