1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 21 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(NRIntReadPorts).W))) 22 val redirect = ValidIO(new Redirect) 23} 24 25class CtrlToFpBlockIO extends XSBundle { 26 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 27 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 28 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 29 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W))) 30 val redirect = ValidIO(new Redirect) 31} 32 33class CtrlToLsBlockIO extends XSBundle { 34 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 35 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 36 val enqLsq = Flipped(new LsqEnqIO) 37 val redirect = ValidIO(new Redirect) 38} 39 40class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 41 val io = IO(new Bundle { 42 val frontend = Flipped(new FrontendToBackendIO) 43 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 44 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 45 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 46 val toIntBlock = new CtrlToIntBlockIO 47 val toFpBlock = new CtrlToFpBlockIO 48 val toLsBlock = new CtrlToLsBlockIO 49 val roqio = new Bundle { 50 // to int block 51 val toCSR = new RoqCSRIO 52 val exception = ValidIO(new MicroOp) 53 val isInterrupt = Output(Bool()) 54 // to mem block 55 val commits = new RoqCommitIO 56 val roqDeqPtr = Output(new RoqPtr) 57 } 58 }) 59 60 val decode = Module(new DecodeStage) 61 val brq = Module(new Brq) 62 val rename = Module(new Rename) 63 val dispatch = Module(new Dispatch) 64 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 65 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 66 67 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 68 69 val roq = Module(new Roq(roqWbSize)) 70 71 // When replay and mis-prediction have the same roqIdx, 72 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 73 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 74 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 75 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 76 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 77 val redirectValid = roq.io.redirectOut.valid || brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 78 val redirect = Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits, redirectArb) 79 80 io.frontend.redirect.valid := RegNext(redirectValid) 81 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits.target, redirectArb.target)) 82 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 83 84 decode.io.in <> io.frontend.cfVec 85 decode.io.enqBrq <> brq.io.enq 86 87 brq.io.redirect.valid <> redirectValid 88 brq.io.redirect.bits <> redirect 89 brq.io.bcommit <> roq.io.bcommit 90 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 91 92 // pipeline between decode and dispatch 93 val lastCycleRedirect = RegNext(redirectValid) 94 for (i <- 0 until RenameWidth) { 95 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 96 } 97 98 rename.io.redirect.valid <> redirectValid 99 rename.io.redirect.bits <> redirect 100 rename.io.roqCommits <> roq.io.commits 101 rename.io.out <> dispatch.io.fromRename 102 rename.io.renameBypass <> dispatch.io.renameBypass 103 104 dispatch.io.redirect.valid <> redirectValid 105 dispatch.io.redirect.bits <> redirect 106 dispatch.io.enqRoq <> roq.io.enq 107 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 108 dispatch.io.readIntRf <> io.toIntBlock.readRf 109 dispatch.io.readFpRf <> io.toFpBlock.readRf 110 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 111 intBusyTable.io.allocPregs(i).valid := preg.isInt 112 fpBusyTable.io.allocPregs(i).valid := preg.isFp 113 intBusyTable.io.allocPregs(i).bits := preg.preg 114 fpBusyTable.io.allocPregs(i).bits := preg.preg 115 } 116 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 117 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 118 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 119 120 121 val flush = redirectValid && RedirectLevel.isUnconditional(redirect.level) 122 fpBusyTable.io.flush := flush 123 intBusyTable.io.flush := flush 124 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 125 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 126 setPhyRegRdy.bits := wb.bits.uop.pdest 127 } 128 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 129 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 130 setPhyRegRdy.bits := wb.bits.uop.pdest 131 } 132 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 133 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 134 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 135 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 136 137 roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 138 roq.io.redirect.bits <> redirectArb 139 roq.io.exeWbResults.take(roqWbSize-1).zip( 140 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 141 ).foreach{ 142 case(x, y) => 143 x.bits := y.bits 144 x.valid := y.valid && !y.bits.redirectValid 145 } 146 roq.io.exeWbResults.last := brq.io.out 147 148 io.toIntBlock.redirect.valid := redirectValid 149 io.toIntBlock.redirect.bits := redirect 150 io.toFpBlock.redirect.valid := redirectValid 151 io.toFpBlock.redirect.bits := redirect 152 io.toLsBlock.redirect.valid := redirectValid 153 io.toLsBlock.redirect.bits := redirect 154 155 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 156 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 157 158 // roq to int block 159 io.roqio.toCSR <> roq.io.csr 160 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 161 io.roqio.exception.bits := roq.io.exception 162 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 163 // roq to mem block 164 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 165 io.roqio.commits := roq.io.commits 166} 167