1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25 val flush = Output(Bool()) 26} 27 28class CtrlToFpBlockIO extends XSBundle { 29 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 30 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 31 // fp block uses port 0~11 32 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 33 val redirect = ValidIO(new Redirect) 34 val flush = Output(Bool()) 35} 36 37class CtrlToLsBlockIO extends XSBundle { 38 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 39 val enqLsq = Flipped(new LsqEnqIO) 40 val redirect = ValidIO(new Redirect) 41 val flush = Output(Bool()) 42} 43 44class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 45 val io = IO(new Bundle() { 46 val loadRelay = Flipped(ValidIO(new Redirect)) 47 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 48 val flush = Input(Bool()) 49 val stage2FtqRead = new FtqRead 50 val stage2Redirect = ValidIO(new Redirect) 51 val stage3Redirect = ValidIO(new Redirect) 52 }) 53 /* 54 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 55 | | | | | | | 56 |============= reg & compare =====| | ======== 57 | | 58 | | 59 | | Stage2 60 | | 61 redirect (flush backend) | 62 | | 63 === reg === | ======== 64 | | 65 |----- mux (exception first) -----| Stage3 66 | 67 redirect (send to frontend) 68 */ 69 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 70 Mux(x.valid, 71 Mux(y.valid, 72 Mux(isAfter(x.bits.roqIdx, y.bits.roqIdx), y, x), 73 x 74 ), 75 y 76 ) 77 } 78 def selectOlderExuOutWithFlag(x: Valid[ExuOutput], y: Valid[ExuOutput]): (Valid[ExuOutput], Bool) = { 79 val yIsOlder = Mux(x.valid, 80 Mux(y.valid, 81 Mux(isAfter(x.bits.redirect.roqIdx, y.bits.redirect.roqIdx), true.B, false.B), 82 false.B 83 ), 84 true.B 85 ) 86 val sel = Mux(yIsOlder, y, x) 87 (sel, yIsOlder) 88 } 89 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 90 selectOlderExuOutWithFlag(x, y)._1 91 } 92 val jumpOut = io.exuMispredict.head 93 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 94 val (oldestExuOut, jumpIsOlder) = selectOlderExuOutWithFlag(oldestAluOut, jumpOut) // select between jump and alu 95 96 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 97 val redirect = Wire(Valid(new Redirect)) 98 redirect.valid := oldestExuOut.valid 99 redirect.bits := oldestExuOut.bits.redirect 100 redirect 101 }) 102 103 XSDebug(oldestExuOut.valid, p"exuMispredict: ${Binary(Cat(io.exuMispredict.map(_.valid)))}\n") 104 105 val s1_isJump = RegNext(jumpIsOlder, init = false.B) 106 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 107 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 108 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 109 val s1_redirect_bits_reg = Reg(new Redirect) 110 val s1_redirect_valid_reg = RegInit(false.B) 111 112 // stage1 -> stage2 113 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect, io.flush)){ 114 s1_redirect_bits_reg := oldestMispredict.bits 115 s1_redirect_valid_reg := true.B 116 }.otherwise({ 117 s1_redirect_valid_reg := false.B 118 }) 119 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 120 io.stage2Redirect.bits := s1_redirect_bits_reg 121 io.stage2Redirect.bits.cfiUpdate := DontCare 122 // at stage2, we read ftq to get pc 123 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 124 125 // stage3, calculate redirect target 126 val s2_isJump = RegNext(s1_isJump) 127 val s2_jumpTarget = RegEnable(s1_jumpTarget, s1_redirect_valid_reg) 128 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 129 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 130 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 131 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 132 133 val ftqRead = io.stage2FtqRead.entry 134 val cfiUpdate_pc = 135 Cat(ftqRead.ftqPC.head(VAddrBits - s2_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 136 s2_redirect_bits_reg.ftqOffset, 137 0.U(instOffsetBits.W)) 138 val real_pc = 139 GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset, 140 ftqRead.lastPacketPC.valid, 141 ftqRead.lastPacketPC.bits) 142 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s2_imm12_reg), XLEN) 143 val snpc = real_pc + Mux(s2_pd.isRVC, 2.U, 4.U) 144 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 145 val target = Mux(isReplay, 146 real_pc, // repaly from itself 147 Mux(s2_redirect_bits_reg.cfiUpdate.taken, 148 Mux(s2_isJump, s2_jumpTarget, brTarget), 149 snpc 150 ) 151 ) 152 io.stage3Redirect.valid := s2_redirect_valid_reg 153 io.stage3Redirect.bits := s2_redirect_bits_reg 154 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 155 stage3CfiUpdate.pc := cfiUpdate_pc 156 stage3CfiUpdate.pd := s2_pd 157 stage3CfiUpdate.rasSp := ftqRead.rasSp 158 stage3CfiUpdate.rasEntry := ftqRead.rasTop 159 stage3CfiUpdate.hist := ftqRead.hist 160 stage3CfiUpdate.predHist := ftqRead.predHist 161 stage3CfiUpdate.specCnt := ftqRead.specCnt(s2_redirect_bits_reg.ftqOffset) 162 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 163 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 164 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 165 })(s2_redirect_bits_reg.ftqOffset) 166 stage3CfiUpdate.target := target 167 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 168 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 169} 170 171class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 172 val io = IO(new Bundle { 173 val frontend = Flipped(new FrontendToBackendIO) 174 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 175 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 176 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 177 val toIntBlock = new CtrlToIntBlockIO 178 val toFpBlock = new CtrlToFpBlockIO 179 val toLsBlock = new CtrlToLsBlockIO 180 val roqio = new Bundle { 181 // to int block 182 val toCSR = new RoqCSRIO 183 val exception = ValidIO(new ExceptionInfo) 184 // to mem block 185 val lsq = new RoqLsqIO 186 } 187 }) 188 189 val difftestIO = IO(new Bundle() { 190 val fromRoq = new Bundle() { 191 val commit = Output(UInt(32.W)) 192 val thisPC = Output(UInt(XLEN.W)) 193 val thisINST = Output(UInt(32.W)) 194 val skip = Output(UInt(32.W)) 195 val wen = Output(UInt(32.W)) 196 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 197 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 198 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 199 val isRVC = Output(UInt(32.W)) 200 val scFailed = Output(Bool()) 201 val lpaddr = Output(Vec(CommitWidth, UInt(64.W))) 202 val ltype = Output(Vec(CommitWidth, UInt(32.W))) 203 val lfu = Output(Vec(CommitWidth, UInt(4.W))) 204 } 205 }) 206 difftestIO <> DontCare 207 208 val ftq = Module(new Ftq) 209 val trapIO = IO(new TrapIO()) 210 trapIO <> DontCare 211 212 val decode = Module(new DecodeStage) 213 val rename = Module(new Rename) 214 val dispatch = Module(new Dispatch) 215 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 216 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 217 val redirectGen = Module(new RedirectGenerator) 218 219 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 220 221 val roq = Module(new Roq(roqWbSize)) 222 223 val backendRedirect = redirectGen.io.stage2Redirect 224 val frontendRedirect = redirectGen.io.stage3Redirect 225 val flush = roq.io.flushOut.valid 226 val flushReg = RegNext(flush) 227 228 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 229 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 230 x.bits := y.bits 231 }) 232 redirectGen.io.loadRelay := io.fromLsBlock.replay 233 redirectGen.io.flush := flushReg 234 235 ftq.io.enq <> io.frontend.fetchInfo 236 for(i <- 0 until CommitWidth){ 237 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 238 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 239 } 240 ftq.io.redirect <> backendRedirect 241 ftq.io.flush := flushReg 242 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 243 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 244 ftq.io.frontendRedirect <> frontendRedirect 245 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 246 247 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 248 ftq.io.ftqRead(2).ptr := roq.io.flushOut.bits.ftqIdx 249 val flushPC = GetPcByFtq( 250 ftq.io.ftqRead(2).entry.ftqPC, 251 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 252 ftq.io.ftqRead(2).entry.lastPacketPC.valid, 253 ftq.io.ftqRead(2).entry.lastPacketPC.bits 254 ) 255 256 val flushRedirect = Wire(Valid(new Redirect)) 257 flushRedirect.valid := flushReg 258 flushRedirect.bits := DontCare 259 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 260 flushRedirect.bits.interrupt := true.B 261 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 262 io.roqio.toCSR.trapTarget, 263 flushPC + 4.U // flush pipe 264 ) 265 266 io.frontend.redirect_cfiUpdate := Mux(flushRedirect.valid, flushRedirect, frontendRedirect) 267 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 268 io.frontend.ftqEnqPtr := ftq.io.enqPtr 269 io.frontend.ftqLeftOne := ftq.io.leftOne 270 271 decode.io.in <> io.frontend.cfVec 272 273 val jumpInst = dispatch.io.enqIQCtrl(0).bits 274 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 275 ftqOffsetReg := jumpInst.cf.ftqOffset 276 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 277 io.toIntBlock.jumpPc := GetPcByFtq( 278 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 279 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 280 ftq.io.ftqRead(0).entry.lastPacketPC.bits 281 ) 282 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 283 284 // pipeline between decode and dispatch 285 for (i <- 0 until RenameWidth) { 286 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 287 io.frontend.redirect_cfiUpdate.valid) 288 } 289 290 rename.io.redirect <> backendRedirect 291 rename.io.flush := flushReg 292 rename.io.roqCommits <> roq.io.commits 293 rename.io.out <> dispatch.io.fromRename 294 rename.io.renameBypass <> dispatch.io.renameBypass 295 296 dispatch.io.redirect <> backendRedirect 297 dispatch.io.flush := flushReg 298 dispatch.io.enqRoq <> roq.io.enq 299 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 300 dispatch.io.readIntRf <> io.toIntBlock.readRf 301 dispatch.io.readFpRf <> io.toFpBlock.readRf 302 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 303 intBusyTable.io.allocPregs(i).valid := preg.isInt 304 fpBusyTable.io.allocPregs(i).valid := preg.isFp 305 intBusyTable.io.allocPregs(i).bits := preg.preg 306 fpBusyTable.io.allocPregs(i).bits := preg.preg 307 } 308 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 309 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 310// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 311 312 313 fpBusyTable.io.flush := flushReg 314 intBusyTable.io.flush := flushReg 315 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 316 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 317 setPhyRegRdy.bits := wb.bits.uop.pdest 318 } 319 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 320 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 321 setPhyRegRdy.bits := wb.bits.uop.pdest 322 } 323 intBusyTable.io.read <> dispatch.io.readIntState 324 fpBusyTable.io.read <> dispatch.io.readFpState 325 326 roq.io.redirect <> backendRedirect 327 roq.io.exeWbResults.zip( 328 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 329 ).foreach{ 330 case(x, y) => 331 x.bits := y.bits 332 x.valid := y.valid 333 } 334 335 // TODO: is 'backendRedirect' necesscary? 336 io.toIntBlock.redirect <> backendRedirect 337 io.toIntBlock.flush <> flushReg 338 io.toFpBlock.redirect <> backendRedirect 339 io.toFpBlock.flush <> flushReg 340 io.toLsBlock.redirect <> backendRedirect 341 io.toLsBlock.flush <> flushReg 342 343 if (!env.FPGAPlatform) { 344 difftestIO.fromRoq <> roq.difftestIO 345 trapIO <> roq.trapIO 346 } 347 348 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 349 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 350 351 // roq to int block 352 io.roqio.toCSR <> roq.io.csr 353 io.roqio.exception := roq.io.exception 354 io.roqio.exception.bits.uop.cf.pc := flushPC 355 // roq to mem block 356 io.roqio.lsq <> roq.io.lsq 357} 358