1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.brq.{Brq, BrqPcRead} 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24} 25 26class CtrlToFpBlockIO extends XSBundle { 27 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 28 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 29 // fp block uses port 0~11 30 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 31 val redirect = ValidIO(new Redirect) 32} 33 34class CtrlToLsBlockIO extends XSBundle { 35 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 36 val enqLsq = Flipped(new LsqEnqIO) 37 val redirect = ValidIO(new Redirect) 38} 39 40class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 41 val io = IO(new Bundle { 42 val frontend = Flipped(new FrontendToBackendIO) 43 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 44 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 45 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 46 val toIntBlock = new CtrlToIntBlockIO 47 val toFpBlock = new CtrlToFpBlockIO 48 val toLsBlock = new CtrlToLsBlockIO 49 val roqio = new Bundle { 50 // to int block 51 val toCSR = new RoqCSRIO 52 val exception = ValidIO(new MicroOp) 53 val isInterrupt = Output(Bool()) 54 // to mem block 55 val lsq = new RoqLsqIO 56 } 57 }) 58 59 val difftestIO = IO(new Bundle() { 60 val fromRoq = new Bundle() { 61 val commit = Output(UInt(32.W)) 62 val thisPC = Output(UInt(XLEN.W)) 63 val thisINST = Output(UInt(32.W)) 64 val skip = Output(UInt(32.W)) 65 val wen = Output(UInt(32.W)) 66 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 67 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 68 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 69 val isRVC = Output(UInt(32.W)) 70 val scFailed = Output(Bool()) 71 val lpaddr = Output(Vec(CommitWidth, UInt(64.W))) 72 val ltype = Output(Vec(CommitWidth, UInt(32.W))) 73 val lfu = Output(Vec(CommitWidth, UInt(4.W))) 74 } 75 }) 76 difftestIO <> DontCare 77 78 val trapIO = IO(new TrapIO()) 79 trapIO <> DontCare 80 81 val decode = Module(new DecodeStage) 82 val brq = Module(new Brq) 83 val rename = Module(new Rename) 84 val dispatch = Module(new Dispatch) 85 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 86 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 87 88 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 89 90 val roq = Module(new Roq(roqWbSize)) 91 92 // When replay and mis-prediction have the same roqIdx, 93 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 94 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 95 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 96 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 97 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 98 val redirectValid = roq.io.redirectOut.valid || brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 99 val redirect = Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits, redirectArb) 100 101 io.frontend.redirect.valid := RegNext(redirectValid) 102 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits.target, redirectArb.target)) 103 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 104 105 decode.io.in <> io.frontend.cfVec 106 decode.io.enqBrq <> brq.io.enq 107 108 brq.io.redirect.valid <> redirectValid 109 brq.io.redirect.bits <> redirect 110 brq.io.bcommit <> roq.io.bcommit 111 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 112 brq.io.pcReadReq.brqIdx := dispatch.io.enqIQCtrl(0).bits.brTag // jump 113 io.toIntBlock.jumpPc := brq.io.pcReadReq.pc 114 115 // pipeline between decode and dispatch 116 val lastCycleRedirect = RegNext(redirectValid) 117 for (i <- 0 until RenameWidth) { 118 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 119 } 120 121 rename.io.redirect.valid <> redirectValid 122 rename.io.redirect.bits <> redirect 123 rename.io.roqCommits <> roq.io.commits 124 rename.io.out <> dispatch.io.fromRename 125 rename.io.renameBypass <> dispatch.io.renameBypass 126 127 dispatch.io.redirect.valid <> redirectValid 128 dispatch.io.redirect.bits <> redirect 129 dispatch.io.enqRoq <> roq.io.enq 130 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 131 dispatch.io.readIntRf <> io.toIntBlock.readRf 132 dispatch.io.readFpRf <> io.toFpBlock.readRf 133 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 134 intBusyTable.io.allocPregs(i).valid := preg.isInt 135 fpBusyTable.io.allocPregs(i).valid := preg.isFp 136 intBusyTable.io.allocPregs(i).bits := preg.preg 137 fpBusyTable.io.allocPregs(i).bits := preg.preg 138 } 139 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 140 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 141// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 142 143 144 val flush = redirectValid && RedirectLevel.isUnconditional(redirect.level) 145 fpBusyTable.io.flush := flush 146 intBusyTable.io.flush := flush 147 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 148 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 149 setPhyRegRdy.bits := wb.bits.uop.pdest 150 } 151 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 152 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 153 setPhyRegRdy.bits := wb.bits.uop.pdest 154 } 155 intBusyTable.io.read <> dispatch.io.readIntState 156 fpBusyTable.io.read <> dispatch.io.readFpState 157 158 roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 159 roq.io.redirect.bits <> redirectArb 160 roq.io.exeWbResults.take(roqWbSize-1).zip( 161 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 162 ).foreach{ 163 case(x, y) => 164 x.bits := y.bits 165 x.valid := y.valid && !y.bits.redirectValid 166 } 167 roq.io.exeWbResults.last := brq.io.out 168 169 if (env.DualCoreDifftest) { 170 difftestIO.fromRoq <> roq.difftestIO 171 trapIO <> roq.trapIO 172 } 173 174 io.toIntBlock.redirect.valid := redirectValid 175 io.toIntBlock.redirect.bits := redirect 176 io.toFpBlock.redirect.valid := redirectValid 177 io.toFpBlock.redirect.bits := redirect 178 io.toLsBlock.redirect.valid := redirectValid 179 io.toLsBlock.redirect.bits := redirect 180 181 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 182 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 183 184 // roq to int block 185 io.roqio.toCSR <> roq.io.csr 186 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 187 io.roqio.exception.bits := roq.io.exception 188 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 189 // roq to mem block 190 io.roqio.lsq <> roq.io.lsq 191} 192