xref: /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala (revision 8a597714f393747f61fbfe30222e7c70aeab82c1) 
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3*
4* XiangShan is licensed under Mulan PSL v2.
5* You can use this software according to the terms and conditions of the Mulan PSL v2.
6* You may obtain a copy of Mulan PSL v2 at:
7*          http://license.coscl.org.cn/MulanPSL2
8*
9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
12*
13* See the Mulan PSL v2 for more details.
14***************************************************************************************/
15
16package xiangshan.backend
17
18import chipsalliance.rocketchip.config.Parameters
19import chisel3._
20import chisel3.util._
21import utils._
22import xiangshan._
23import xiangshan.backend.decode.{DecodeStage, ImmUnion}
24import xiangshan.backend.rename.{BusyTable, Rename}
25import xiangshan.backend.dispatch.Dispatch
26import xiangshan.backend.exu._
27import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr, CfiInfoToCtrl}
28import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr}
29import xiangshan.mem.LsqEnqIO
30
31class CtrlToFtqIO(implicit p: Parameters) extends XSBundle {
32  val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo))
33  val stage2Redirect = Valid(new Redirect)
34  val roqFlush = Valid(new Bundle {
35    val ftqIdx = Output(new FtqPtr)
36    val ftqOffset = Output(UInt(log2Up(PredictWidth).W))
37  })
38
39  val loadReplay = Valid(new Redirect)
40  val stage3Redirect = ValidIO(new Redirect)
41}
42
43class RedirectGenerator(implicit p: Parameters) extends XSModule
44  with HasCircularQueuePtrHelper {
45  val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt
46  val io = IO(new Bundle() {
47    val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput)))
48    val loadReplay = Flipped(ValidIO(new Redirect))
49    val flush = Input(Bool())
50    val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W)))
51    val stage1CfiRead = Vec(numRedirect+1, new FtqRead(new CfiInfoToCtrl))
52    val stage2Redirect = ValidIO(new Redirect)
53    val stage3Redirect = ValidIO(new Redirect)
54    val memPredUpdate = Output(new MemPredUpdateReq)
55    val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2
56  })
57  /*
58        LoadQueue  Jump  ALU0  ALU1  ALU2  ALU3   exception    Stage1
59          |         |      |    |     |     |         |
60          |============= reg & compare =====|         |       ========
61                            |                         |
62                            |                         |
63                            |                         |        Stage2
64                            |                         |
65                    redirect (flush backend)          |
66                    |                                 |
67               === reg ===                            |       ========
68                    |                                 |
69                    |----- mux (exception first) -----|        Stage3
70                            |
71                redirect (send to frontend)
72   */
73  private class Wrapper(val n: Int) extends Bundle {
74    val redirect = new Redirect
75    val valid = Bool()
76    val idx = UInt(log2Up(n).W)
77  }
78  def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = {
79    val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx)))
80    val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j =>
81      (if (j < i) !xs(j).valid || compareVec(i)(j)
82      else if (j == i) xs(i).valid
83      else !xs(j).valid || !compareVec(j)(i))
84    )).andR))
85    resultOnehot
86  }
87
88  val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits
89  val stage1FtqReadPcs =
90    (io.stage1PcRead zip redirects).map{ case (r, redirect) =>
91      r(redirect.ftqIdx, redirect.ftqOffset)
92    }
93  val stage1FtqReadCfis =
94    (io.stage1CfiRead zip redirects).map{ case (r, redirect) =>
95      r(redirect.ftqIdx, redirect.ftqOffset)
96    }
97
98  def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = {
99    val redirect = Wire(Valid(new Redirect))
100    redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred
101    redirect.bits := exuOut.bits.redirect
102    redirect
103  }
104
105  val jumpOut = io.exuMispredict.head
106  val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay)
107  val oldestOneHot = selectOldestRedirect(allRedirect)
108  val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush)))
109  val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR
110  val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict)
111  val oldestRedirect = Mux1H(oldestOneHot, allRedirect)
112
113  val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid)
114  val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0))
115  val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd)
116  val s1_redirect_bits_reg = RegNext(oldestRedirect.bits)
117  val s1_redirect_valid_reg = RegNext(oldestValid)
118  val s1_redirect_onehot = RegNext(oldestOneHot)
119
120  // stage1 -> stage2
121  io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush
122  io.stage2Redirect.bits := s1_redirect_bits_reg
123  io.stage2Redirect.bits.cfiUpdate := DontCare
124
125  val s1_isReplay = s1_redirect_onehot.last
126  val s1_isJump = s1_redirect_onehot.head
127  val cfiRead = Mux1H(s1_redirect_onehot, stage1FtqReadCfis)
128  val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs)
129  val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN)
130  val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U)
131  val target = Mux(s1_isReplay,
132    real_pc, // repaly from itself
133    Mux(s1_redirect_bits_reg.cfiUpdate.taken,
134      Mux(s1_isJump, s1_jumpTarget, brTarget),
135      snpc
136    )
137  )
138
139  // get pc from ftq
140  // valid only if redirect is caused by load violation
141  // store_pc is used to update store set
142  val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset)
143
144  // update load violation predictor if load violation redirect triggered
145  io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B)
146  // update wait table
147  io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth))
148  io.memPredUpdate.wdata := true.B
149  // update store set
150  io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth))
151  // store pc is ready 1 cycle after s1_isReplay is judged
152  io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth)
153
154  val s2_br_mask = RegEnable(cfiRead.br_mask, enable = s1_redirect_valid_reg)
155  val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i =>
156      if(i == 0) false.B else Cat(cfiRead.br_mask.take(i)).orR()
157    })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg)
158  val s2_hist = RegEnable(cfiRead.hist, enable = s1_redirect_valid_reg)
159  val s2_target = RegEnable(target, enable = s1_redirect_valid_reg)
160  val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg)
161  val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg)
162  val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg)
163  val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B)
164
165  io.stage3Redirect.valid := s2_redirect_valid_reg
166  io.stage3Redirect.bits := s2_redirect_bits_reg
167  val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate
168  stage3CfiUpdate.pc := s2_pc
169  stage3CfiUpdate.pd := s2_pd
170  // stage3CfiUpdate.rasSp := s2_ftqRead.rasSp
171  // stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop
172  // stage3CfiUpdate.predHist := s2_ftqRead.predHist
173  // stage3CfiUpdate.specCnt := s2_ftqRead.specCnt
174  stage3CfiUpdate.hist := s2_hist
175  stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken
176  stage3CfiUpdate.br_hit := s2_sawNotTakenBranch
177  stage3CfiUpdate.target := s2_target
178  stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken
179  stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred
180}
181
182class CtrlBlock(implicit p: Parameters) extends XSModule
183  with HasCircularQueuePtrHelper {
184  val io = IO(new Bundle {
185    val frontend = Flipped(new FrontendToCtrlIO)
186    val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp))
187    // from int block
188    val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput)))
189    val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput)))
190    val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput)))
191    val memoryViolation = Flipped(ValidIO(new Redirect))
192    val enqLsq = Flipped(new LsqEnqIO)
193    val jumpPc = Output(UInt(VAddrBits.W))
194    val jalr_target = Output(UInt(VAddrBits.W))
195    val roqio = new Bundle {
196      // to int block
197      val toCSR = new RoqCSRIO
198      val exception = ValidIO(new ExceptionInfo)
199      // to mem block
200      val lsq = new RoqLsqIO
201    }
202    val csrCtrl = Input(new CustomCSRCtrlIO)
203    val perfInfo = Output(new Bundle{
204      val ctrlInfo = new Bundle {
205        val roqFull   = Input(Bool())
206        val intdqFull = Input(Bool())
207        val fpdqFull  = Input(Bool())
208        val lsdqFull  = Input(Bool())
209      }
210    })
211    val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput)))
212    // redirect out
213    val redirect = ValidIO(new Redirect)
214    val flush = Output(Bool())
215    val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W)))
216    val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W)))
217    val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W)))
218    val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W)))
219  })
220
221  val decode = Module(new DecodeStage)
222  val rename = Module(new Rename)
223  val dispatch = Module(new Dispatch)
224  val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts))
225  val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts))
226  val redirectGen = Module(new RedirectGenerator)
227
228  val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt
229  val roq = Module(new Roq(roqWbSize))
230
231  val stage2Redirect = redirectGen.io.stage2Redirect
232  val stage3Redirect = redirectGen.io.stage3Redirect
233  val flush = roq.io.flushOut.valid
234  val flushReg = RegNext(flush)
235
236  val exuRedirect = io.exuRedirect.map(x => {
237    val valid = x.valid && x.bits.redirectValid
238    val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)
239    val delayed = Wire(Valid(new ExuOutput))
240    delayed.valid := RegNext(valid && !killedByOlder, init = false.B)
241    delayed.bits := RegEnable(x.bits, x.valid)
242    delayed
243  })
244  val loadReplay = Wire(Valid(new Redirect))
245  loadReplay.valid := RegNext(io.memoryViolation.valid &&
246    !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg),
247    init = false.B
248  )
249  loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid)
250  io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead
251  io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead
252  io.frontend.fromFtq.cfi_reads <> redirectGen.io.stage1CfiRead
253  redirectGen.io.exuMispredict <> exuRedirect
254  redirectGen.io.loadReplay <> loadReplay
255  redirectGen.io.flush := flushReg
256
257  for(i <- 0 until CommitWidth){
258    io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk
259    io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i)
260  }
261  io.frontend.toFtq.stage2Redirect <> stage2Redirect
262  io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut)
263  io.frontend.toFtq.stage3Redirect <> stage3Redirect
264  io.frontend.toFtq.loadReplay <> loadReplay
265
266  val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead
267  val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset)
268
269  val flushRedirect = Wire(Valid(new Redirect))
270  flushRedirect.valid := flushReg
271  flushRedirect.bits := DontCare
272  flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush)
273  flushRedirect.bits.interrupt := true.B
274  flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid,
275    io.roqio.toCSR.trapTarget,
276    flushPC + 4.U // flush pipe
277  )
278  val flushRedirectReg = Wire(Valid(new Redirect))
279  flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B)
280  flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid)
281
282  io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect)
283
284  decode.io.in <> io.frontend.cfVec
285  // currently, we only update wait table when isReplay
286  decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate)
287  decode.io.memPredUpdate(1) := DontCare
288  decode.io.memPredUpdate(1).valid := false.B
289  // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate
290  decode.io.csrCtrl := RegNext(io.csrCtrl)
291
292
293  val jumpInst = dispatch.io.enqIQCtrl(0).bits
294  val jumpPcRead = io.frontend.fromFtq.getJumpPcRead
295  io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset)
296  val jumpTargetRead = io.frontend.fromFtq.target_read
297  io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset)
298
299  // pipeline between decode and dispatch
300  for (i <- 0 until RenameWidth) {
301    PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready,
302      flushReg || io.frontend.redirect_cfiUpdate.valid)
303  }
304
305  rename.io.redirect <> stage2Redirect
306  rename.io.flush := flushReg
307  rename.io.roqCommits <> roq.io.commits
308  rename.io.out <> dispatch.io.fromRename
309  rename.io.renameBypass <> dispatch.io.renameBypass
310  rename.io.dispatchInfo <> dispatch.io.preDpInfo
311  rename.io.csrCtrl <> RegNext(io.csrCtrl)
312
313  dispatch.io.redirect <> stage2Redirect
314  dispatch.io.flush := flushReg
315  dispatch.io.enqRoq <> roq.io.enq
316  dispatch.io.enqLsq <> io.enqLsq
317  dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) =>
318    intBusyTable.io.allocPregs(i).valid := preg.isInt
319    fpBusyTable.io.allocPregs(i).valid := preg.isFp
320    intBusyTable.io.allocPregs(i).bits := preg.preg
321    fpBusyTable.io.allocPregs(i).bits := preg.preg
322  }
323  dispatch.io.enqIQCtrl := DontCare
324  io.enqIQ <> dispatch.io.enqIQCtrl
325  dispatch.io.csrCtrl <> io.csrCtrl
326  dispatch.io.storeIssue <> io.stIn
327  dispatch.io.readIntRf <> io.readIntRf
328  dispatch.io.readFpRf <> io.readFpRf
329
330  fpBusyTable.io.flush := flushReg
331  intBusyTable.io.flush := flushReg
332  for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){
333    setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen
334    setPhyRegRdy.bits := wb.bits.uop.pdest
335  }
336  for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){
337    setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen
338    setPhyRegRdy.bits := wb.bits.uop.pdest
339  }
340  intBusyTable.io.read <> dispatch.io.readIntState
341  fpBusyTable.io.read <> dispatch.io.readFpState
342
343  roq.io.redirect <> stage2Redirect
344  val exeWbResults = VecInit(io.writeback ++ io.stOut)
345  for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) {
346    roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg))
347    roq_wb.bits := RegNext(wb.bits)
348  }
349
350  // TODO: is 'backendRedirect' necesscary?
351  io.redirect <> stage2Redirect
352  io.flush <> flushReg
353  io.debug_int_rat <> rename.io.debug_int_rat
354  io.debug_fp_rat <> rename.io.debug_fp_rat
355
356//  dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex
357//  dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex
358
359  // roq to int block
360  io.roqio.toCSR <> roq.io.csr
361  io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr)
362  io.roqio.exception := roq.io.exception
363  io.roqio.exception.bits.uop.cf.pc := flushPC
364  // roq to mem block
365  io.roqio.lsq <> roq.io.lsq
366
367  io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull)
368  io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull)
369  io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull)
370  io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull)
371}
372