1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17 18class FpBlockToCtrlIO extends XSBundle { 19 // TODO: should not be FpExuCnt 20 val wbIntRegs = Vec(exuParameters.FpExuCnt, Flipped(ValidIO(new ExuOutput))) 21 val wbFpRegs = Vec(exuParameters.FpExuCnt, Flipped(ValidIO(new ExuOutput))) 22 val numExist = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil(IssQueSize).W))) 23} 24 25class CtrlToIntBlockIO extends XSBundle { 26 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 27 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 28 val readIntRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 29} 30 31class CtrlToFpBlockIO extends XSBundle { 32 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 33 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 34 val readFpRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 35} 36 37class CtrlToLsBlockIO extends XSBundle { 38 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 39 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 40 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 41} 42 43class CtrlBlock extends XSModule { 44 val io = IO(new Bundle { 45 val frontend = Flipped(new FrontendToBackendIO) 46 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 47 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 48 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 49 val toIntBlock = new CtrlToIntBlockIO 50 val toFpBlock = new CtrlToFpBlockIO 51 val toLsBlock = new CtrlToLsBlockIO 52 }) 53 54 val decode = Module(new DecodeStage) 55 val brq = Module(new Brq) 56 val decBuf = Module(new DecodeBuffer) 57 val rename = Module(new Rename) 58 val dispatch = Module(new Dispatch( 59 jmpExeUnit.config, aluExeUnits(0).config, mduExeUnits(0).config, 60 fmacExeUnits(0).config, fmiscExeUnits(0).config, 61 ldExeUnitCfg, stExeUnitCfg 62 )) 63 // TODO: move busyTable to dispatch1 64 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 65 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 66 val roq = Module(new Roq) 67 68 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 69 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 70 71 val redirect = Mux( 72 roq.io.redirect.valid, 73 roq.io.redirect, 74 Mux( 75 brq.io.redirect.valid, 76 brq.io.redirect, 77 io.fromLsBlock.replay 78 ) 79 ) 80 81 decode.io.in <> io.frontend.cfVec 82 decode.io.toBrq <> brq.io.enqReqs 83 decode.io.brTags <> brq.io.brTags 84 decode.io.out <> decBuf.io.in 85 86 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 87 decBuf.io.redirect <> redirect 88 decBuf.io.out <> rename.io.in 89 90 rename.io.redirect <> redirect 91 rename.io.roqCommits <> roq.io.commits 92 // they should be moved to busytables 93 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 94 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 95 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 96 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 97 rename.io.intPregRdy <> dispatch.io.intPregRdy 98 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 99 rename.io.replayPregReq <> dispatch.io.replayPregReq 100 rename.io.out <> dispatch.io.fromRename 101 102 dispatch.io.redirect <> redirect 103 dispatch.io.toRoq <> roq.io.dp1Req 104 dispatch.io.roqIdxs <> roq.io.roqIdxs 105 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 106 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 107 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 108 dispatch.io.dequeueRoqIndex.bits = Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 109 dispatch.io.readIntRf <> io.toIntBlock.rfReadPorts 110 dispatch.io.readFpRf <> io.toFpBlock.rfReadPorts 111 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 112 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIQCtrl ++ io.toFpBlock.enqIQCtrl ++ io.toLsBlock.enqIQCtrl 113 dispatch.io.enqIqData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 114 115 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 116 // fpBusyTable.flush := flush 117 // intBusyTable.flush := flush 118 // busytable io 119 // maybe update busytable in dispatch1? 120 121} 122