1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.brq.{Brq, BrqPcRead} 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 14import xiangshan.backend.regfile.RfReadPort 15import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 16import xiangshan.mem.LsqEnqIO 17 18class CtrlToIntBlockIO extends XSBundle { 19 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 21 val jumpPc = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25} 26 27class CtrlToFpBlockIO extends XSBundle { 28 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 29 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 30 // fp block uses port 0~11 31 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 32 val redirect = ValidIO(new Redirect) 33} 34 35class CtrlToLsBlockIO extends XSBundle { 36 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 37 val enqLsq = Flipped(new LsqEnqIO) 38 val redirect = ValidIO(new Redirect) 39} 40 41class RedirectGenerator extends XSModule with NeedImpl { 42 val io = IO(new Bundle() { 43 val loadRelay = Flipped(ValidIO(new Redirect)) 44 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 45 val roqRedirect = Flipped(ValidIO(new Redirect)) 46 val exuFtqRead = new FtqRead 47 val stage2Redirect = ValidIO(new Redirect) 48 val stage3CfiUpdate = Output(ValidIO(new CfiUpdateInfo)) 49 }) 50 /* 51 loadReplay and roqRedirect already read cfi update info from ftq 52 exus haven't read, they need to read at stage 2 53 54 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 55 | | | | | | | 56 | |==== reg & compare ====| | ======== 57 | | | 58 | ftq read | 59 |------- mux ------| | Stage2 60 | | 61 redirect (flush backend) | 62 | | 63 === reg === | ======== 64 | | 65 |----- mux (exception first) -----| Stage3 66 | 67 redirect (send to frontend) 68 */ 69} 70 71class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 72 val io = IO(new Bundle { 73 val frontend = Flipped(new FrontendToBackendIO) 74 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 75 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 76 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 77 val toIntBlock = new CtrlToIntBlockIO 78 val toFpBlock = new CtrlToFpBlockIO 79 val toLsBlock = new CtrlToLsBlockIO 80 val roqio = new Bundle { 81 // to int block 82 val toCSR = new RoqCSRIO 83 val exception = ValidIO(new MicroOp) 84 val isInterrupt = Output(Bool()) 85 // to mem block 86 val commits = new RoqCommitIO 87 val roqDeqPtr = Output(new RoqPtr) 88 } 89 }) 90 91 val ftq = Module(new Ftq) 92 val decode = Module(new DecodeStage) 93 val rename = Module(new Rename) 94 val dispatch = Module(new Dispatch) 95 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 96 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 97 val redirectGen = Module(new RedirectGenerator) 98 99 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 100 101 val roq = Module(new Roq(roqWbSize)) 102 103 val backendRedirect = redirectGen.io.stage2Redirect 104 val frontendRedirect = redirectGen.io.stage3CfiUpdate 105 106 ftq.io.enq <> io.frontend.fetchInfo 107 for(i <- 0 until CommitWidth){ 108 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) 109 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 110 } 111 ftq.io.redirect <> backendRedirect 112 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 113 114 ftq.io.ftqRead(1) <> redirectGen.io.exuFtqRead 115 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc / load replay pc form here 116 117 io.frontend.redirect_cfiUpdate := frontendRedirect 118 io.frontend.commit_cfiUpdate := ftq.io.commit_cfiUpdate 119 120 decode.io.in <> io.frontend.cfVec 121 122 val jumpInst = dispatch.io.enqIQCtrl(0).bits 123 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 124 io.toIntBlock.jumpPc := GetPcByFtq(ftq.io.ftqRead(0).entry.ftqPC, jumpInst.cf.ftqOffset) 125 126 // pipeline between decode and dispatch 127 for (i <- 0 until RenameWidth) { 128 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 129 backendRedirect.valid || frontendRedirect.valid) 130 } 131 132 rename.io.redirect <> backendRedirect 133 rename.io.roqCommits <> roq.io.commits 134 rename.io.out <> dispatch.io.fromRename 135 rename.io.renameBypass <> dispatch.io.renameBypass 136 137 dispatch.io.redirect <> backendRedirect 138 dispatch.io.enqRoq <> roq.io.enq 139 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 140 dispatch.io.readIntRf <> io.toIntBlock.readRf 141 dispatch.io.readFpRf <> io.toFpBlock.readRf 142 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 143 intBusyTable.io.allocPregs(i).valid := preg.isInt 144 fpBusyTable.io.allocPregs(i).valid := preg.isFp 145 intBusyTable.io.allocPregs(i).bits := preg.preg 146 fpBusyTable.io.allocPregs(i).bits := preg.preg 147 } 148 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 149 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 150// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 151 152 153 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 154 fpBusyTable.io.flush := flush 155 intBusyTable.io.flush := flush 156 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 157 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 158 setPhyRegRdy.bits := wb.bits.uop.pdest 159 } 160 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 161 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 162 setPhyRegRdy.bits := wb.bits.uop.pdest 163 } 164 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 165 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 166 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 167 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 168 169 roq.io.redirect <> backendRedirect 170 roq.io.exeWbResults.take(roqWbSize-1).zip( 171 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 172 ).foreach{ 173 case(x, y) => 174 x.bits := y.bits 175 x.valid := y.valid 176 } 177 178 // TODO: is 'backendRedirect' necesscary? 179 io.toIntBlock.redirect <> backendRedirect 180 io.toFpBlock.redirect <> backendRedirect 181 io.toLsBlock.redirect <> backendRedirect 182 183 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 184 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 185 186 // roq to int block 187 io.roqio.toCSR <> roq.io.csr 188 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 189 io.roqio.exception.bits := roq.io.exception 190 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 191 // roq to mem block 192 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 193 io.roqio.commits := roq.io.commits 194} 195