1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{Rename, BusyTable} 9import xiangshan.backend.brq.Brq 10import xiangshan.backend.dispatch.Dispatch 11import xiangshan.backend.exu._ 12import xiangshan.backend.exu.Exu.exuConfigs 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqPtr, RoqCSRIO} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 20 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(NRIntReadPorts).W))) 21 val redirect = ValidIO(new Redirect) 22} 23 24class CtrlToFpBlockIO extends XSBundle { 25 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 27 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil(NRFpReadPorts - exuParameters.StuCnt).W))) 28 val redirect = ValidIO(new Redirect) 29} 30 31class CtrlToLsBlockIO extends XSBundle { 32 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 33 val enqLsq = Flipped(new LsqEnqIO) 34 val redirect = ValidIO(new Redirect) 35} 36 37class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 38 val io = IO(new Bundle { 39 val frontend = Flipped(new FrontendToBackendIO) 40 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 41 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 42 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 43 val toIntBlock = new CtrlToIntBlockIO 44 val toFpBlock = new CtrlToFpBlockIO 45 val toLsBlock = new CtrlToLsBlockIO 46 val roqio = new Bundle { 47 // to int block 48 val toCSR = new RoqCSRIO 49 val exception = ValidIO(new MicroOp) 50 val isInterrupt = Output(Bool()) 51 // to mem block 52 val commits = new RoqCommitIO 53 val roqDeqPtr = Output(new RoqPtr) 54 } 55 }) 56 57 val decode = Module(new DecodeStage) 58 val brq = Module(new Brq) 59 val rename = Module(new Rename) 60 val dispatch = Module(new Dispatch) 61 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 62 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 63 64 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt + 1 65 66 val roq = Module(new Roq(roqWbSize)) 67 68 // When replay and mis-prediction have the same roqIdx, 69 // mis-prediction should have higher priority, since mis-prediction flushes the load instruction. 70 // Thus, only when mis-prediction roqIdx is after replay roqIdx, replay should be valid. 71 val brqIsAfterLsq = isAfter(brq.io.redirectOut.bits.roqIdx, io.fromLsBlock.replay.bits.roqIdx) 72 val redirectArb = Mux(io.fromLsBlock.replay.valid && (!brq.io.redirectOut.valid || brqIsAfterLsq), 73 io.fromLsBlock.replay.bits, brq.io.redirectOut.bits) 74 val redirectValid = roq.io.redirectOut.valid || brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 75 val redirect = Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits, redirectArb) 76 77 io.frontend.redirect.valid := RegNext(redirectValid) 78 io.frontend.redirect.bits := RegNext(Mux(roq.io.redirectOut.valid, roq.io.redirectOut.bits.target, redirectArb.target)) 79 io.frontend.cfiUpdateInfo <> brq.io.cfiInfo 80 81 decode.io.in <> io.frontend.cfVec 82 decode.io.enqBrq <> brq.io.enq 83 84 brq.io.redirect.valid <> redirectValid 85 brq.io.redirect.bits <> redirect 86 brq.io.bcommit <> roq.io.bcommit 87 brq.io.exuRedirectWb <> io.fromIntBlock.exuRedirect 88 89 // pipeline between decode and dispatch 90 val lastCycleRedirect = RegNext(redirectValid) 91 for (i <- 0 until RenameWidth) { 92 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, redirectValid || lastCycleRedirect) 93 } 94 95 rename.io.redirect.valid <> redirectValid 96 rename.io.redirect.bits <> redirect 97 rename.io.roqCommits <> roq.io.commits 98 rename.io.out <> dispatch.io.fromRename 99 rename.io.renameBypass <> dispatch.io.renameBypass 100 101 dispatch.io.redirect.valid <> redirectValid 102 dispatch.io.redirect.bits <> redirect 103 dispatch.io.enqRoq <> roq.io.enq 104 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 105 dispatch.io.readIntRf <> io.toIntBlock.readRf 106 dispatch.io.readFpRf <> io.toFpBlock.readRf 107 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 108 intBusyTable.io.allocPregs(i).valid := preg.isInt 109 fpBusyTable.io.allocPregs(i).valid := preg.isFp 110 intBusyTable.io.allocPregs(i).bits := preg.preg 111 fpBusyTable.io.allocPregs(i).bits := preg.preg 112 } 113 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 114 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 115// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 116 117 118 val flush = redirectValid && RedirectLevel.isUnconditional(redirect.level) 119 fpBusyTable.io.flush := flush 120 intBusyTable.io.flush := flush 121 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 122 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen && (wb.bits.uop.ctrl.ldest =/= 0.U) 123 setPhyRegRdy.bits := wb.bits.uop.pdest 124 } 125 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 126 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 127 setPhyRegRdy.bits := wb.bits.uop.pdest 128 } 129 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 130 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 131 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 132 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 133 134 roq.io.redirect.valid := brq.io.redirectOut.valid || io.fromLsBlock.replay.valid 135 roq.io.redirect.bits <> redirectArb 136 roq.io.exeWbResults.take(roqWbSize-1).zip( 137 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 138 ).foreach{ 139 case(x, y) => 140 x.bits := y.bits 141 x.valid := y.valid && !y.bits.redirectValid 142 } 143 roq.io.exeWbResults.last := brq.io.out 144 145 io.toIntBlock.redirect.valid := redirectValid 146 io.toIntBlock.redirect.bits := redirect 147 io.toFpBlock.redirect.valid := redirectValid 148 io.toFpBlock.redirect.bits := redirect 149 io.toLsBlock.redirect.valid := redirectValid 150 io.toLsBlock.redirect.bits := redirect 151 152 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 153 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 154 155 // roq to int block 156 io.roqio.toCSR <> roq.io.csr 157 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 158 io.roqio.exception.bits := roq.io.exception 159 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 160 // roq to mem block 161 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 162 io.roqio.commits := roq.io.commits 163} 164