1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.{DecodeStage, ImmUnion} 25import xiangshan.backend.rename.{BusyTable, Rename} 26import xiangshan.backend.dispatch.Dispatch 27import xiangshan.backend.exu._ 28import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr} 29import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 30import xiangshan.mem.LsqEnqIO 31 32class CtrlToFtqIO(implicit p: Parameters) extends XSBundle { 33 val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo)) 34 val stage2Redirect = Valid(new Redirect) 35 val stage3Redirect = ValidIO(new Redirect) 36 val roqFlush = Valid(new Bundle { 37 val ftqIdx = Output(new FtqPtr) 38 val ftqOffset = Output(UInt(log2Up(PredictWidth).W)) 39 val replayInst = Output(Bool()) // not used for now 40 }) 41} 42 43class RedirectGenerator(implicit p: Parameters) extends XSModule 44 with HasCircularQueuePtrHelper { 45 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 46 val io = IO(new Bundle() { 47 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 48 val loadReplay = Flipped(ValidIO(new Redirect)) 49 val flush = Input(Bool()) 50 val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W))) 51 val stage2Redirect = ValidIO(new Redirect) 52 val stage3Redirect = ValidIO(new Redirect) 53 val memPredUpdate = Output(new MemPredUpdateReq) 54 val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2 55 }) 56 /* 57 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 58 | | | | | | | 59 |============= reg & compare =====| | ======== 60 | | 61 | | 62 | | Stage2 63 | | 64 redirect (flush backend) | 65 | | 66 === reg === | ======== 67 | | 68 |----- mux (exception first) -----| Stage3 69 | 70 redirect (send to frontend) 71 */ 72 private class Wrapper(val n: Int) extends Bundle { 73 val redirect = new Redirect 74 val valid = Bool() 75 val idx = UInt(log2Up(n).W) 76 } 77 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 78 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 79 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 80 (if (j < i) !xs(j).valid || compareVec(i)(j) 81 else if (j == i) xs(i).valid 82 else !xs(j).valid || !compareVec(j)(i)) 83 )).andR)) 84 resultOnehot 85 } 86 87 val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 88 val stage1FtqReadPcs = 89 (io.stage1PcRead zip redirects).map{ case (r, redirect) => 90 r(redirect.ftqIdx, redirect.ftqOffset) 91 } 92 93 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 94 val redirect = Wire(Valid(new Redirect)) 95 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 96 redirect.bits := exuOut.bits.redirect 97 redirect 98 } 99 100 val jumpOut = io.exuMispredict.head 101 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 102 val oldestOneHot = selectOldestRedirect(allRedirect) 103 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 104 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 105 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 106 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 107 108 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 109 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 110 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 111 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 112 val s1_redirect_valid_reg = RegNext(oldestValid) 113 val s1_redirect_onehot = RegNext(oldestOneHot) 114 115 // stage1 -> stage2 116 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 117 io.stage2Redirect.bits := s1_redirect_bits_reg 118 io.stage2Redirect.bits.cfiUpdate := DontCare 119 120 val s1_isReplay = s1_redirect_onehot.last 121 val s1_isJump = s1_redirect_onehot.head 122 val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs) 123 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 124 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 125 val target = Mux(s1_isReplay, 126 real_pc, // replay from itself 127 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 128 Mux(s1_isJump, s1_jumpTarget, brTarget), 129 snpc 130 ) 131 ) 132 133 // get pc from ftq 134 // valid only if redirect is caused by load violation 135 // store_pc is used to update store set 136 val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset) 137 138 // update load violation predictor if load violation redirect triggered 139 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 140 // update wait table 141 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 142 io.memPredUpdate.wdata := true.B 143 // update store set 144 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 145 // store pc is ready 1 cycle after s1_isReplay is judged 146 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 147 148 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 149 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 150 val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg) 151 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 152 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 153 154 io.stage3Redirect.valid := s2_redirect_valid_reg 155 io.stage3Redirect.bits := s2_redirect_bits_reg 156 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 157 stage3CfiUpdate.pc := s2_pc 158 stage3CfiUpdate.pd := s2_pd 159 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 160 stage3CfiUpdate.target := s2_target 161 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 162 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 163} 164 165class CtrlBlock(implicit p: Parameters) extends XSModule 166 with HasCircularQueuePtrHelper { 167 val io = IO(new Bundle { 168 val frontend = Flipped(new FrontendToCtrlIO) 169 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 170 // from int block 171 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 172 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 173 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 174 val memoryViolation = Flipped(ValidIO(new Redirect)) 175 val enqLsq = Flipped(new LsqEnqIO) 176 val jumpPc = Output(UInt(VAddrBits.W)) 177 val jalr_target = Output(UInt(VAddrBits.W)) 178 val roqio = new Bundle { 179 // to int block 180 val toCSR = new RoqCSRIO 181 val exception = ValidIO(new ExceptionInfo) 182 // to mem block 183 val lsq = new RoqLsqIO 184 } 185 val csrCtrl = Input(new CustomCSRCtrlIO) 186 val perfInfo = Output(new Bundle{ 187 val ctrlInfo = new Bundle { 188 val roqFull = Input(Bool()) 189 val intdqFull = Input(Bool()) 190 val fpdqFull = Input(Bool()) 191 val lsdqFull = Input(Bool()) 192 } 193 }) 194 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 195 // redirect out 196 val redirect = ValidIO(new Redirect) 197 val flush = Output(Bool()) 198 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 199 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 200 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 201 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 202 }) 203 204 val decode = Module(new DecodeStage) 205 val rename = Module(new Rename) 206 val dispatch = Module(new Dispatch) 207 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 208 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 209 val redirectGen = Module(new RedirectGenerator) 210 211 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 212 val roq = Module(new Roq(roqWbSize)) 213 214 val stage2Redirect = redirectGen.io.stage2Redirect 215 val stage3Redirect = redirectGen.io.stage3Redirect 216 val flush = roq.io.flushOut.valid 217 val flushReg = RegNext(flush) 218 219 val exuRedirect = io.exuRedirect.map(x => { 220 val valid = x.valid && x.bits.redirectValid 221 val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg) 222 val delayed = Wire(Valid(new ExuOutput)) 223 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 224 delayed.bits := RegEnable(x.bits, x.valid) 225 delayed 226 }) 227 val loadReplay = Wire(Valid(new Redirect)) 228 loadReplay.valid := RegNext(io.memoryViolation.valid && 229 !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg), 230 init = false.B 231 ) 232 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 233 io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead 234 io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead 235 redirectGen.io.exuMispredict <> exuRedirect 236 redirectGen.io.loadReplay <> loadReplay 237 redirectGen.io.flush := flushReg 238 239 for(i <- 0 until CommitWidth){ 240 io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 241 io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i) 242 } 243 io.frontend.toFtq.stage2Redirect <> stage2Redirect 244 io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut) 245 246 val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead 247 val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset) 248 249 val flushRedirect = Wire(Valid(new Redirect)) 250 flushRedirect.valid := flushReg 251 flushRedirect.bits := DontCare 252 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 253 flushRedirect.bits.interrupt := true.B 254 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 255 io.roqio.toCSR.trapTarget, 256 Mux(RegEnable(roq.io.flushOut.bits.replayInst, flush), 257 flushPC, // replay inst 258 flushPC + 4.U // flush pipe 259 ) 260 ) 261 when (flushRedirect.valid && RegEnable(roq.io.flushOut.bits.replayInst, flush)) { 262 XSDebug("replay inst (%x) from rob\n", flushPC); 263 } 264 val flushRedirectReg = Wire(Valid(new Redirect)) 265 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 266 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 267 268 io.frontend.toFtq.stage3Redirect := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect) 269 270 decode.io.in <> io.frontend.cfVec 271 // currently, we only update wait table when isReplay 272 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 273 decode.io.memPredUpdate(1) := DontCare 274 decode.io.memPredUpdate(1).valid := false.B 275 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 276 decode.io.csrCtrl := RegNext(io.csrCtrl) 277 278 279 val jumpInst = dispatch.io.enqIQCtrl(0).bits 280 val jumpPcRead = io.frontend.fromFtq.getJumpPcRead 281 io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 282 val jumpTargetRead = io.frontend.fromFtq.target_read 283 io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 284 285 // pipeline between decode and dispatch 286 for (i <- 0 until RenameWidth) { 287 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 288 flushReg || io.frontend.toFtq.stage3Redirect.valid) 289 } 290 291 rename.io.redirect <> stage2Redirect 292 rename.io.flush := flushReg 293 rename.io.roqCommits <> roq.io.commits 294 rename.io.out <> dispatch.io.fromRename 295 rename.io.renameBypass <> dispatch.io.renameBypass 296 rename.io.dispatchInfo <> dispatch.io.preDpInfo 297 298 dispatch.io.redirect <> stage2Redirect 299 dispatch.io.flush := flushReg 300 dispatch.io.enqRoq <> roq.io.enq 301 dispatch.io.enqLsq <> io.enqLsq 302 dispatch.io.singleStep := false.B 303 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 304 intBusyTable.io.allocPregs(i).valid := preg.isInt 305 fpBusyTable.io.allocPregs(i).valid := preg.isFp 306 intBusyTable.io.allocPregs(i).bits := preg.preg 307 fpBusyTable.io.allocPregs(i).bits := preg.preg 308 } 309 dispatch.io.enqIQCtrl := DontCare 310 io.enqIQ <> dispatch.io.enqIQCtrl 311 dispatch.io.csrCtrl <> io.csrCtrl 312 dispatch.io.storeIssue <> io.stIn 313 dispatch.io.readIntRf <> io.readIntRf 314 dispatch.io.readFpRf <> io.readFpRf 315 316 fpBusyTable.io.flush := flushReg 317 intBusyTable.io.flush := flushReg 318 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 319 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 320 setPhyRegRdy.bits := wb.bits.uop.pdest 321 } 322 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 323 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 324 setPhyRegRdy.bits := wb.bits.uop.pdest 325 } 326 intBusyTable.io.read <> dispatch.io.readIntState 327 fpBusyTable.io.read <> dispatch.io.readFpState 328 329 roq.io.redirect <> stage2Redirect 330 val exeWbResults = VecInit(io.writeback ++ io.stOut) 331 val timer = GTimer() 332 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 333 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)) 334 roq_wb.bits := RegNext(wb.bits) 335 roq_wb.bits.uop.debugInfo.writebackTime := timer 336 } 337 338 // TODO: is 'backendRedirect' necesscary? 339 io.redirect <> stage2Redirect 340 io.flush <> flushReg 341 io.debug_int_rat <> rename.io.debug_int_rat 342 io.debug_fp_rat <> rename.io.debug_fp_rat 343 344// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 345// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 346 347 // roq to int block 348 io.roqio.toCSR <> roq.io.csr 349 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 350 io.roqio.exception := roq.io.exception 351 io.roqio.exception.bits.uop.cf.pc := flushPC 352 // roq to mem block 353 io.roqio.lsq <> roq.io.lsq 354 355 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 356 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 357 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 358 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 359} 360