xref: /XiangShan/src/main/scala/xiangshan/backend/CtrlBlock.scala (revision 6ab6918f8d678bdfe6b2bd2a326acf56cb4325b6)
1/***************************************************************************************
2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3* Copyright (c) 2020-2021 Peng Cheng Laboratory
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package xiangshan.backend
18
19import chipsalliance.rocketchip.config.Parameters
20import chisel3._
21import chisel3.util._
22import difftest._
23import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp}
24import utils._
25import xiangshan._
26import xiangshan.backend.decode.{DecodeStage, ImmUnion}
27import xiangshan.backend.dispatch.{Dispatch, DispatchQueue}
28import xiangshan.backend.fu.PFEvent
29import xiangshan.backend.rename.{Rename, RenameTableWrapper}
30import xiangshan.backend.rob.{Rob, RobCSRIO, RobLsqIO}
31import xiangshan.frontend.FtqRead
32import xiangshan.mem.mdp.{LFST, SSIT, WaitTable}
33
34class CtrlToFtqIO(implicit p: Parameters) extends XSBundle {
35  val rob_commits = Vec(CommitWidth, Valid(new RobCommitInfo))
36  val stage2Redirect = Valid(new Redirect)
37  val stage3Redirect = ValidIO(new Redirect)
38  val robFlush = ValidIO(new Redirect)
39}
40
41class RedirectGenerator(implicit p: Parameters) extends XSModule
42  with HasCircularQueuePtrHelper {
43  val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt
44  val io = IO(new Bundle() {
45    val hartId = Input(UInt(8.W))
46    val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput)))
47    val loadReplay = Flipped(ValidIO(new Redirect))
48    val flush = Input(Bool())
49    val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W)))
50    val stage2Redirect = ValidIO(new Redirect)
51    val stage3Redirect = ValidIO(new Redirect)
52    val memPredUpdate = Output(new MemPredUpdateReq)
53    val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2
54  })
55  /*
56        LoadQueue  Jump  ALU0  ALU1  ALU2  ALU3   exception    Stage1
57          |         |      |    |     |     |         |
58          |============= reg & compare =====|         |       ========
59                            |                         |
60                            |                         |
61                            |                         |        Stage2
62                            |                         |
63                    redirect (flush backend)          |
64                    |                                 |
65               === reg ===                            |       ========
66                    |                                 |
67                    |----- mux (exception first) -----|        Stage3
68                            |
69                redirect (send to frontend)
70   */
71  private class Wrapper(val n: Int) extends Bundle {
72    val redirect = new Redirect
73    val valid = Bool()
74    val idx = UInt(log2Up(n).W)
75  }
76  def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = {
77    val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.robIdx, xs(i).bits.robIdx)))
78    val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j =>
79      (if (j < i) !xs(j).valid || compareVec(i)(j)
80      else if (j == i) xs(i).valid
81      else !xs(j).valid || !compareVec(j)(i))
82    )).andR))
83    resultOnehot
84  }
85
86  val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits
87  val stage1FtqReadPcs =
88    (io.stage1PcRead zip redirects).map{ case (r, redirect) =>
89      r(redirect.ftqIdx, redirect.ftqOffset)
90    }
91
92  def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = {
93    val redirect = Wire(Valid(new Redirect))
94    redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred
95    redirect.bits := exuOut.bits.redirect
96    redirect
97  }
98
99  val jumpOut = io.exuMispredict.head
100  val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay)
101  val oldestOneHot = selectOldestRedirect(allRedirect)
102  val needFlushVec = VecInit(allRedirect.map(_.bits.robIdx.needFlush(io.stage2Redirect) || io.flush))
103  val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR
104  val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict)
105  val oldestRedirect = Mux1H(oldestOneHot, allRedirect)
106
107  val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid)
108  val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0))
109  val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd)
110  val s1_redirect_bits_reg = RegNext(oldestRedirect.bits)
111  val s1_redirect_valid_reg = RegNext(oldestValid)
112  val s1_redirect_onehot = RegNext(oldestOneHot)
113
114  // stage1 -> stage2
115  io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush
116  io.stage2Redirect.bits := s1_redirect_bits_reg
117  io.stage2Redirect.bits.cfiUpdate := DontCare
118
119  val s1_isReplay = s1_redirect_onehot.last
120  val s1_isJump = s1_redirect_onehot.head
121  val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs)
122  val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN)
123  val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U)
124  val target = Mux(s1_isReplay,
125    real_pc, // replay from itself
126    Mux(s1_redirect_bits_reg.cfiUpdate.taken,
127      Mux(s1_isJump, s1_jumpTarget, brTarget),
128      snpc
129    )
130  )
131
132  // get pc from ftq
133  // valid only if redirect is caused by load violation
134  // store_pc is used to update store set
135  val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset)
136
137  // update load violation predictor if load violation redirect triggered
138  io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B)
139  // update wait table
140  io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth))
141  io.memPredUpdate.wdata := true.B
142  // update store set
143  io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth))
144  // store pc is ready 1 cycle after s1_isReplay is judged
145  io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth)
146
147  val s2_target = RegEnable(target, enable = s1_redirect_valid_reg)
148  val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg)
149  val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg)
150  val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg)
151  val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B)
152
153  io.stage3Redirect.valid := s2_redirect_valid_reg
154  io.stage3Redirect.bits := s2_redirect_bits_reg
155  val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate
156  stage3CfiUpdate.pc := s2_pc
157  stage3CfiUpdate.pd := s2_pd
158  stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken
159  stage3CfiUpdate.target := s2_target
160  stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken
161  stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred
162
163  // recover runahead checkpoint if redirect
164  if (!env.FPGAPlatform) {
165    val runahead_redirect = Module(new DifftestRunaheadRedirectEvent)
166    runahead_redirect.io.clock := clock
167    runahead_redirect.io.coreid := io.hartId
168    runahead_redirect.io.valid := io.stage3Redirect.valid
169    runahead_redirect.io.pc :=  s2_pc // for debug only
170    runahead_redirect.io.target_pc := s2_target // for debug only
171    runahead_redirect.io.checkpoint_id := io.stage3Redirect.bits.debug_runahead_checkpoint_id // make sure it is right
172  }
173}
174
175class CtrlBlock(implicit p: Parameters) extends LazyModule with HasWritebackSink with HasWritebackSource {
176  val rob = LazyModule(new Rob)
177
178  override def addWritebackSink(source: Seq[HasWritebackSource], index: Option[Seq[Int]]): HasWritebackSink = {
179    rob.addWritebackSink(Seq(this), Some(Seq(writebackSinks.length)))
180    super.addWritebackSink(source, index)
181  }
182
183  lazy val module = new CtrlBlockImp(this)
184
185  override lazy val writebackSourceParams: Seq[WritebackSourceParams] = {
186    writebackSinksParams
187  }
188  override lazy val writebackSourceImp: HasWritebackSourceImp = module
189
190  override def generateWritebackIO(
191    thisMod: Option[HasWritebackSource] = None,
192    thisModImp: Option[HasWritebackSourceImp] = None
193  ): Unit = {
194    module.io.writeback.zip(writebackSinksImp(thisMod, thisModImp)).foreach(x => x._1 := x._2)
195  }
196}
197
198class CtrlBlockImp(outer: CtrlBlock)(implicit p: Parameters) extends LazyModuleImp(outer)
199  with HasXSParameter with HasCircularQueuePtrHelper with HasWritebackSourceImp {
200  val writebackLengths = outer.writebackSinksParams.map(_.length)
201
202  val io = IO(new Bundle {
203    val hartId = Input(UInt(8.W))
204    val frontend = Flipped(new FrontendToCtrlIO)
205    val allocPregs = Vec(RenameWidth, Output(new ResetPregStateReq))
206    val dispatch = Vec(3*dpParams.IntDqDeqWidth, DecoupledIO(new MicroOp))
207    // from int block
208    val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput)))
209    val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput)))
210    val memoryViolation = Flipped(ValidIO(new Redirect))
211    val jumpPc = Output(UInt(VAddrBits.W))
212    val jalr_target = Output(UInt(VAddrBits.W))
213    val robio = new Bundle {
214      // to int block
215      val toCSR = new RobCSRIO
216      val exception = ValidIO(new ExceptionInfo)
217      // to mem block
218      val lsq = new RobLsqIO
219    }
220    val csrCtrl = Input(new CustomCSRCtrlIO)
221    val perfInfo = Output(new Bundle{
222      val ctrlInfo = new Bundle {
223        val robFull   = Input(Bool())
224        val intdqFull = Input(Bool())
225        val fpdqFull  = Input(Bool())
226        val lsdqFull  = Input(Bool())
227      }
228    })
229    val writeback = MixedVec(writebackLengths.map(num => Vec(num, Flipped(ValidIO(new ExuOutput)))))
230    // redirect out
231    val redirect = ValidIO(new Redirect)
232    val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W)))
233    val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W)))
234  })
235
236  override def writebackSource: Option[Seq[Seq[Valid[ExuOutput]]]] = {
237    Some(io.writeback.map(writeback => {
238      val exuOutput = WireInit(writeback)
239      val timer = GTimer()
240      for ((wb_next, wb) <- exuOutput.zip(writeback)) {
241        wb_next.valid := RegNext(wb.valid && !wb.bits.uop.robIdx.needFlush(stage2Redirect))
242        wb_next.bits := RegNext(wb.bits)
243        wb_next.bits.uop.debugInfo.writebackTime := timer
244      }
245      exuOutput
246    }))
247  }
248
249  val decode = Module(new DecodeStage)
250  val rat = Module(new RenameTableWrapper)
251  val ssit = Module(new SSIT)
252  val waittable = Module(new WaitTable)
253  val rename = Module(new Rename)
254  val dispatch = Module(new Dispatch)
255  val intDq = Module(new DispatchQueue(dpParams.IntDqSize, RenameWidth, dpParams.IntDqDeqWidth, "int"))
256  val fpDq = Module(new DispatchQueue(dpParams.FpDqSize, RenameWidth, dpParams.FpDqDeqWidth, "fp"))
257  val lsDq = Module(new DispatchQueue(dpParams.LsDqSize, RenameWidth, dpParams.LsDqDeqWidth, "ls"))
258  val redirectGen = Module(new RedirectGenerator)
259
260  val rob = outer.rob.module
261
262  val robPcRead = io.frontend.fromFtq.getRobFlushPcRead
263  val flushPC = robPcRead(rob.io.flushOut.bits.ftqIdx, rob.io.flushOut.bits.ftqOffset)
264
265  val flushRedirect = Wire(Valid(new Redirect))
266  flushRedirect.valid := RegNext(rob.io.flushOut.valid)
267  flushRedirect.bits := RegEnable(rob.io.flushOut.bits, rob.io.flushOut.valid)
268  flushRedirect.bits.cfiUpdate.target := Mux(io.robio.toCSR.isXRet || rob.io.exception.valid,
269    io.robio.toCSR.trapTarget,
270    Mux(flushRedirect.bits.flushItself(),
271      flushPC, // replay inst
272      flushPC + 4.U // flush pipe
273    )
274  )
275
276  val flushRedirectReg = Wire(Valid(new Redirect))
277  flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B)
278  flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid)
279
280  val stage2Redirect = Mux(flushRedirect.valid, flushRedirect, redirectGen.io.stage2Redirect)
281  val stage3Redirect = Mux(flushRedirectReg.valid, flushRedirectReg, redirectGen.io.stage3Redirect)
282
283  val exuRedirect = io.exuRedirect.map(x => {
284    val valid = x.valid && x.bits.redirectValid
285    val killedByOlder = x.bits.uop.robIdx.needFlush(stage2Redirect)
286    val delayed = Wire(Valid(new ExuOutput))
287    delayed.valid := RegNext(valid && !killedByOlder, init = false.B)
288    delayed.bits := RegEnable(x.bits, x.valid)
289    delayed
290  })
291  val loadReplay = Wire(Valid(new Redirect))
292  loadReplay.valid := RegNext(io.memoryViolation.valid &&
293    !io.memoryViolation.bits.robIdx.needFlush(stage2Redirect),
294    init = false.B
295  )
296  loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid)
297  io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead
298  io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead
299  redirectGen.io.hartId := io.hartId
300  redirectGen.io.exuMispredict <> exuRedirect
301  redirectGen.io.loadReplay <> loadReplay
302  redirectGen.io.flush := RegNext(rob.io.flushOut.valid)
303
304  for(i <- 0 until CommitWidth){
305    io.frontend.toFtq.rob_commits(i).valid := rob.io.commits.valid(i) && !rob.io.commits.isWalk
306    io.frontend.toFtq.rob_commits(i).bits := rob.io.commits.info(i)
307  }
308  io.frontend.toFtq.stage2Redirect <> stage2Redirect
309  io.frontend.toFtq.robFlush <> RegNext(rob.io.flushOut)
310  io.frontend.toFtq.stage3Redirect := stage3Redirect
311
312  decode.io.in <> io.frontend.cfVec
313  decode.io.csrCtrl := io.csrCtrl
314
315  // memory dependency predict
316  // when decode, send fold pc to mdp
317  for (i <- 0 until DecodeWidth) {
318    val mdp_foldpc = Mux(
319      decode.io.out(i).fire(),
320      decode.io.in(i).bits.foldpc,
321      rename.io.in(i).bits.cf.foldpc
322    )
323    ssit.io.raddr(i) := mdp_foldpc
324    waittable.io.raddr(i) := mdp_foldpc
325  }
326  // currently, we only update mdp info when isReplay
327  ssit.io.update <> RegNext(redirectGen.io.memPredUpdate)
328  ssit.io.csrCtrl := RegNext(io.csrCtrl)
329  waittable.io.update <> RegNext(redirectGen.io.memPredUpdate)
330  waittable.io.csrCtrl := RegNext(io.csrCtrl)
331
332  // LFST lookup and update
333  val lfst = Module(new LFST)
334  lfst.io.redirect <> RegNext(io.redirect)
335  lfst.io.storeIssue <> RegNext(io.stIn)
336  lfst.io.csrCtrl <> RegNext(io.csrCtrl)
337  lfst.io.dispatch <> dispatch.io.lfst
338
339  rat.io.robCommits := rob.io.commits
340  for ((r, i) <- rat.io.intReadPorts.zipWithIndex) {
341    val raddr = decode.io.out(i).bits.ctrl.lsrc.take(2) :+ decode.io.out(i).bits.ctrl.ldest
342    r.map(_.addr).zip(raddr).foreach(x => x._1 := x._2)
343    rename.io.intReadPorts(i) := r.map(_.data)
344    r.foreach(_.hold := !rename.io.in(i).ready)
345  }
346  rat.io.intRenamePorts := rename.io.intRenamePorts
347  for ((r, i) <- rat.io.fpReadPorts.zipWithIndex) {
348    val raddr = decode.io.out(i).bits.ctrl.lsrc.take(3) :+ decode.io.out(i).bits.ctrl.ldest
349    r.map(_.addr).zip(raddr).foreach(x => x._1 := x._2)
350    rename.io.fpReadPorts(i) := r.map(_.data)
351    r.foreach(_.hold := !rename.io.in(i).ready)
352  }
353  rat.io.fpRenamePorts := rename.io.fpRenamePorts
354  rat.io.debug_int_rat <> io.debug_int_rat
355  rat.io.debug_fp_rat <> io.debug_fp_rat
356
357  // pipeline between decode and rename
358  for (i <- 0 until RenameWidth) {
359    PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready,
360      stage2Redirect.valid || stage3Redirect.valid)
361  }
362
363  rename.io.redirect <> stage2Redirect
364  rename.io.robCommits <> rob.io.commits
365  rename.io.ssit <> ssit.io.rdata
366  rename.io.waittable <> RegNext(waittable.io.rdata)
367
368  // pipeline between rename and dispatch
369  for (i <- 0 until RenameWidth) {
370    PipelineConnect(rename.io.out(i), dispatch.io.fromRename(i), dispatch.io.recv(i), stage2Redirect.valid)
371  }
372
373  dispatch.io.hartId := io.hartId
374  dispatch.io.redirect <> stage2Redirect
375  dispatch.io.enqRob <> rob.io.enq
376  dispatch.io.toIntDq <> intDq.io.enq
377  dispatch.io.toFpDq <> fpDq.io.enq
378  dispatch.io.toLsDq <> lsDq.io.enq
379  dispatch.io.allocPregs <> io.allocPregs
380  dispatch.io.singleStep := false.B
381
382  intDq.io.redirect <> stage2Redirect
383  fpDq.io.redirect <> stage2Redirect
384  lsDq.io.redirect <> stage2Redirect
385
386  io.dispatch <> intDq.io.deq ++ lsDq.io.deq ++ fpDq.io.deq
387
388  val pingpong = RegInit(false.B)
389  pingpong := !pingpong
390  val jumpInst = Mux(pingpong && (exuParameters.AluCnt > 2).B, io.dispatch(2).bits, io.dispatch(0).bits)
391  val jumpPcRead = io.frontend.fromFtq.getJumpPcRead
392  io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset)
393  val jumpTargetRead = io.frontend.fromFtq.target_read
394  io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset)
395
396  rob.io.hartId := io.hartId
397  rob.io.redirect <> stage2Redirect
398  outer.rob.generateWritebackIO(Some(outer), Some(this))
399
400  io.redirect <> stage2Redirect
401
402  // rob to int block
403  io.robio.toCSR <> rob.io.csr
404  io.robio.toCSR.perfinfo.retiredInstr <> RegNext(rob.io.csr.perfinfo.retiredInstr)
405  io.robio.exception := rob.io.exception
406  io.robio.exception.bits.uop.cf.pc := flushPC
407
408  // rob to mem block
409  io.robio.lsq <> rob.io.lsq
410
411  io.perfInfo.ctrlInfo.robFull := RegNext(rob.io.robFull)
412  io.perfInfo.ctrlInfo.intdqFull := RegNext(intDq.io.dqFull)
413  io.perfInfo.ctrlInfo.fpdqFull := RegNext(fpDq.io.dqFull)
414  io.perfInfo.ctrlInfo.lsdqFull := RegNext(lsDq.io.dqFull)
415
416  val pfevent = Module(new PFEvent)
417  val csrevents = pfevent.io.hpmevent.slice(8,16)
418  val perfinfo = IO(new Bundle(){
419    val perfEvents        = Output(new PerfEventsBundle(csrevents.length))
420    val perfEventsRs      = Input(new PerfEventsBundle(NumRs))
421    val perfEventsEu0     = Input(new PerfEventsBundle(10))
422    val perfEventsEu1     = Input(new PerfEventsBundle(10))
423  })
424
425  if(print_perfcounter){
426    val decode_perf     = decode.perfEvents.map(_._1).zip(decode.perfinfo.perfEvents.perf_events)
427    val rename_perf     = rename.perfEvents.map(_._1).zip(rename.perfinfo.perfEvents.perf_events)
428    val dispat_perf     = dispatch.perfEvents.map(_._1).zip(dispatch.perfinfo.perfEvents.perf_events)
429    val intdq_perf      = intDq.perfEvents.map(_._1).zip(intDq.perfinfo.perfEvents.perf_events)
430    val fpdq_perf       = fpDq.perfEvents.map(_._1).zip(fpDq.perfinfo.perfEvents.perf_events)
431    val lsdq_perf       = lsDq.perfEvents.map(_._1).zip(lsDq.perfinfo.perfEvents.perf_events)
432    val rob_perf        = rob.perfEvents.map(_._1).zip(rob.perfinfo.perfEvents.perf_events)
433    val perfEvents =  decode_perf ++ rename_perf ++ dispat_perf ++ intdq_perf ++ fpdq_perf ++ lsdq_perf ++ rob_perf
434
435    for (((perf_name,perf),i) <- perfEvents.zipWithIndex) {
436      println(s"ctrl perf $i: $perf_name")
437    }
438  }
439
440  val hpmEvents = decode.perfinfo.perfEvents.perf_events ++ rename.perfinfo.perfEvents.perf_events ++
441                  dispatch.perfinfo.perfEvents.perf_events ++
442                  intDq.perfinfo.perfEvents.perf_events ++ fpDq.perfinfo.perfEvents.perf_events ++
443                  lsDq.perfinfo.perfEvents.perf_events ++ rob.perfinfo.perfEvents.perf_events ++
444                  perfinfo.perfEventsEu0.perf_events ++ perfinfo.perfEventsEu1.perf_events ++
445                  perfinfo.perfEventsRs.perf_events
446
447  val perf_length = hpmEvents.length
448  val hpm_ctrl = Module(new HPerfmonitor(perf_length,csrevents.length))
449  hpm_ctrl.io.hpm_event := csrevents
450  hpm_ctrl.io.events_sets.perf_events := hpmEvents
451  perfinfo.perfEvents := RegNext(hpm_ctrl.io.events_selected)
452  pfevent.io.distribute_csr := RegNext(io.csrCtrl.distribute_csr)
453
454}
455