1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25} 26 27class CtrlToFpBlockIO extends XSBundle { 28 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 29 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 30 // fp block uses port 0~11 31 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 32 val redirect = ValidIO(new Redirect) 33} 34 35class CtrlToLsBlockIO extends XSBundle { 36 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 37 val enqLsq = Flipped(new LsqEnqIO) 38 val redirect = ValidIO(new Redirect) 39} 40 41class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 42 val io = IO(new Bundle() { 43 val loadRelay = Flipped(ValidIO(new Redirect)) 44 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 45 val roqRedirect = Flipped(ValidIO(new Redirect)) 46 val stage2FtqRead = new FtqRead 47 val stage2Redirect = ValidIO(new Redirect) 48 val stage3Redirect = ValidIO(new Redirect) 49 }) 50 /* 51 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 52 | | | | | | | 53 |============= reg & compare =====| | ======== 54 | | 55 | | 56 | | Stage2 57 | | 58 redirect (flush backend) | 59 | | 60 === reg === | ======== 61 | | 62 |----- mux (exception first) -----| Stage3 63 | 64 redirect (send to frontend) 65 */ 66 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 67 Mux(x.valid, 68 Mux(y.valid, 69 Mux(isAfter(x.bits.roqIdx, y.bits.roqIdx), y, x), 70 x 71 ), 72 y 73 ) 74 } 75 def selectOlderExuOutWithFlag(x: Valid[ExuOutput], y: Valid[ExuOutput]): (Valid[ExuOutput], Bool) = { 76 val yIsOlder = Mux(x.valid, 77 Mux(y.valid, 78 Mux(isAfter(x.bits.redirect.roqIdx, y.bits.redirect.roqIdx), true.B, false.B), 79 false.B 80 ), 81 true.B 82 ) 83 val sel = Mux(yIsOlder, y, x) 84 (sel, yIsOlder) 85 } 86 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 87 selectOlderExuOutWithFlag(x, y)._1 88 } 89 val jumpOut = io.exuMispredict.head 90 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 91 val (oldestExuOut, jumpIsOlder) = selectOlderExuOutWithFlag(oldestAluOut, jumpOut) // select between jump and alu 92 93 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 94 val redirect = Wire(Valid(new Redirect)) 95 redirect.valid := oldestExuOut.valid 96 redirect.bits := oldestExuOut.bits.redirect 97 redirect 98 }) 99 100 XSDebug(oldestExuOut.valid, p"exuMispredict: ${Binary(Cat(io.exuMispredict.map(_.valid)))}\n") 101 102 val s1_isJump = RegNext(jumpIsOlder, init = false.B) 103 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 104 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 105 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 106 val s1_redirect_bits_reg = Reg(new Redirect) 107 val s1_redirect_valid_reg = RegInit(false.B) 108 109 // stage1 -> stage2 110 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect)){ 111 s1_redirect_bits_reg := oldestMispredict.bits 112 s1_redirect_valid_reg := true.B 113 }.otherwise({ 114 s1_redirect_valid_reg := false.B 115 }) 116 io.stage2Redirect.valid := s1_redirect_valid_reg 117 io.stage2Redirect.bits := s1_redirect_bits_reg 118 io.stage2Redirect.bits.cfiUpdate := DontCare 119 // at stage2, we read ftq to get pc 120 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 121 122 // stage3, calculate redirect target 123 val s2_isJump = RegNext(s1_isJump) 124 val s2_jumpTarget = RegEnable(s1_jumpTarget, s1_redirect_valid_reg) 125 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 126 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 127 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 128 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg, init = false.B) 129 130 val ftqRead = io.stage2FtqRead.entry 131 val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset, ftqRead.hasLastPrev) 132 val brTarget = pc + SignExt(ImmUnion.B.toImm32(s2_imm12_reg), XLEN) 133 val snpc = pc + Mux(s2_pd.isRVC, 2.U, 4.U) 134 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 135 val target = Mux(isReplay, 136 pc, // repaly from itself 137 Mux(s2_redirect_bits_reg.cfiUpdate.taken, 138 Mux(s2_isJump, s2_jumpTarget, brTarget), 139 snpc 140 ) 141 ) 142 io.stage3Redirect.valid := s2_redirect_valid_reg 143 io.stage3Redirect.bits := s2_redirect_bits_reg 144 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 145 stage3CfiUpdate.pc := pc 146 stage3CfiUpdate.pd := s2_pd 147 stage3CfiUpdate.rasSp := ftqRead.rasSp 148 stage3CfiUpdate.rasEntry := ftqRead.rasTop 149 stage3CfiUpdate.hist := ftqRead.hist 150 stage3CfiUpdate.predHist := ftqRead.predHist 151 stage3CfiUpdate.specCnt := ftqRead.specCnt(s2_redirect_bits_reg.ftqOffset) 152 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 153 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 154 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 155 })(s2_redirect_bits_reg.ftqOffset) 156 stage3CfiUpdate.target := target 157 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 158 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 159} 160 161class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 162 val io = IO(new Bundle { 163 val frontend = Flipped(new FrontendToBackendIO) 164 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 165 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 166 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 167 val toIntBlock = new CtrlToIntBlockIO 168 val toFpBlock = new CtrlToFpBlockIO 169 val toLsBlock = new CtrlToLsBlockIO 170 val roqio = new Bundle { 171 // to int block 172 val toCSR = new RoqCSRIO 173 val exception = ValidIO(new MicroOp) 174 val isInterrupt = Output(Bool()) 175 // to mem block 176 val commits = new RoqCommitIO 177 val roqDeqPtr = Output(new RoqPtr) 178 } 179 }) 180 181 val difftestIO = IO(new Bundle() { 182 val fromRoq = new Bundle() { 183 val commit = Output(UInt(32.W)) 184 val thisPC = Output(UInt(XLEN.W)) 185 val thisINST = Output(UInt(32.W)) 186 val skip = Output(UInt(32.W)) 187 val wen = Output(UInt(32.W)) 188 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 189 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 190 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 191 val isRVC = Output(UInt(32.W)) 192 val scFailed = Output(Bool()) 193 } 194 }) 195 difftestIO <> DontCare 196 197 val ftq = Module(new Ftq) 198 val decode = Module(new DecodeStage) 199 val rename = Module(new Rename) 200 val dispatch = Module(new Dispatch) 201 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 202 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 203 val redirectGen = Module(new RedirectGenerator) 204 205 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 206 207 val roq = Module(new Roq(roqWbSize)) 208 209 val backendRedirect = redirectGen.io.stage2Redirect 210 val frontendRedirect = redirectGen.io.stage3Redirect 211 212 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 213 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 214 x.bits := y.bits 215 }) 216 redirectGen.io.loadRelay := io.fromLsBlock.replay 217 redirectGen.io.roqRedirect := roq.io.redirectOut 218 219 ftq.io.enq <> io.frontend.fetchInfo 220 for(i <- 0 until CommitWidth){ 221 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 222 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 223 } 224 ftq.io.redirect <> backendRedirect 225 ftq.io.frontendRedirect <> frontendRedirect 226 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 227 228 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 229 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 230 231 io.frontend.redirect_cfiUpdate := frontendRedirect 232 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 233 io.frontend.ftqEnqPtr := ftq.io.enqPtr 234 io.frontend.ftqLeftOne := ftq.io.leftOne 235 236 decode.io.in <> io.frontend.cfVec 237 238 val jumpInst = dispatch.io.enqIQCtrl(0).bits 239 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 240 ftqOffsetReg := jumpInst.cf.ftqOffset 241 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 242 io.toIntBlock.jumpPc := GetPcByFtq( 243 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, ftq.io.ftqRead(0).entry.hasLastPrev 244 ) 245 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 246 247 // pipeline between decode and dispatch 248 for (i <- 0 until RenameWidth) { 249 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 250 backendRedirect.valid || frontendRedirect.valid) 251 } 252 253 rename.io.redirect <> backendRedirect 254 rename.io.roqCommits <> roq.io.commits 255 rename.io.out <> dispatch.io.fromRename 256 rename.io.renameBypass <> dispatch.io.renameBypass 257 258 dispatch.io.redirect <> backendRedirect 259 dispatch.io.enqRoq <> roq.io.enq 260 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 261 dispatch.io.readIntRf <> io.toIntBlock.readRf 262 dispatch.io.readFpRf <> io.toFpBlock.readRf 263 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 264 intBusyTable.io.allocPregs(i).valid := preg.isInt 265 fpBusyTable.io.allocPregs(i).valid := preg.isFp 266 intBusyTable.io.allocPregs(i).bits := preg.preg 267 fpBusyTable.io.allocPregs(i).bits := preg.preg 268 } 269 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 270 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 271// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 272 273 274 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 275 fpBusyTable.io.flush := flush 276 intBusyTable.io.flush := flush 277 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 278 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 279 setPhyRegRdy.bits := wb.bits.uop.pdest 280 } 281 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 282 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 283 setPhyRegRdy.bits := wb.bits.uop.pdest 284 } 285 intBusyTable.io.read <> dispatch.io.readIntState 286 fpBusyTable.io.read <> dispatch.io.readFpState 287 288 roq.io.redirect <> backendRedirect 289 roq.io.exeWbResults.zip( 290 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 291 ).foreach{ 292 case(x, y) => 293 x.bits := y.bits 294 x.valid := y.valid 295 } 296 297 // TODO: is 'backendRedirect' necesscary? 298 io.toIntBlock.redirect <> backendRedirect 299 io.toFpBlock.redirect <> backendRedirect 300 io.toLsBlock.redirect <> backendRedirect 301 302 if (env.DualCoreDifftest) { 303 difftestIO.fromRoq <> roq.difftestIO 304 } 305 306 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 307 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 308 309 // roq to int block 310 io.roqio.toCSR <> roq.io.csr 311 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 312 io.roqio.exception.bits := roq.io.exception 313 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 314 // roq to mem block 315 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 316 io.roqio.commits := roq.io.commits 317} 318