1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr, RoqExceptionInfo} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25 val flush = Output(Bool()) 26} 27 28class CtrlToFpBlockIO extends XSBundle { 29 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 30 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 31 // fp block uses port 0~11 32 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 33 val redirect = ValidIO(new Redirect) 34 val flush = Output(Bool()) 35} 36 37class CtrlToLsBlockIO extends XSBundle { 38 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 39 val enqLsq = Flipped(new LsqEnqIO) 40 val redirect = ValidIO(new Redirect) 41 val flush = Output(Bool()) 42} 43 44class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper { 45 val io = IO(new Bundle() { 46 val loadRelay = Flipped(ValidIO(new Redirect)) 47 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 48 val stage2FtqRead = new FtqRead 49 val stage2Redirect = ValidIO(new Redirect) 50 val stage3Redirect = ValidIO(new Redirect) 51 }) 52 /* 53 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 54 | | | | | | | 55 |============= reg & compare =====| | ======== 56 | | 57 | | 58 | | Stage2 59 | | 60 redirect (flush backend) | 61 | | 62 === reg === | ======== 63 | | 64 |----- mux (exception first) -----| Stage3 65 | 66 redirect (send to frontend) 67 */ 68 def selectOlderRedirect(x: Valid[Redirect], y: Valid[Redirect]): Valid[Redirect] = { 69 Mux(x.valid, 70 Mux(y.valid, 71 Mux(isAfter(x.bits.roqIdx, y.bits.roqIdx), y, x), 72 x 73 ), 74 y 75 ) 76 } 77 def selectOlderExuOutWithFlag(x: Valid[ExuOutput], y: Valid[ExuOutput]): (Valid[ExuOutput], Bool) = { 78 val yIsOlder = Mux(x.valid, 79 Mux(y.valid, 80 Mux(isAfter(x.bits.redirect.roqIdx, y.bits.redirect.roqIdx), true.B, false.B), 81 false.B 82 ), 83 true.B 84 ) 85 val sel = Mux(yIsOlder, y, x) 86 (sel, yIsOlder) 87 } 88 def selectOlderExuOut(x: Valid[ExuOutput], y: Valid[ExuOutput]): Valid[ExuOutput] = { 89 selectOlderExuOutWithFlag(x, y)._1 90 } 91 val jumpOut = io.exuMispredict.head 92 val oldestAluOut = ParallelOperation(io.exuMispredict.tail, selectOlderExuOut) 93 val (oldestExuOut, jumpIsOlder) = selectOlderExuOutWithFlag(oldestAluOut, jumpOut) // select between jump and alu 94 95 val oldestMispredict = selectOlderRedirect(io.loadRelay, { 96 val redirect = Wire(Valid(new Redirect)) 97 redirect.valid := oldestExuOut.valid 98 redirect.bits := oldestExuOut.bits.redirect 99 redirect 100 }) 101 102 XSDebug(oldestExuOut.valid, p"exuMispredict: ${Binary(Cat(io.exuMispredict.map(_.valid)))}\n") 103 104 val s1_isJump = RegNext(jumpIsOlder, init = false.B) 105 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 106 val s1_imm12_reg = RegEnable(oldestExuOut.bits.uop.ctrl.imm(11, 0), oldestExuOut.valid) 107 val s1_pd = RegEnable(oldestExuOut.bits.uop.cf.pd, oldestExuOut.valid) 108 val s1_redirect_bits_reg = Reg(new Redirect) 109 val s1_redirect_valid_reg = RegInit(false.B) 110 111 // stage1 -> stage2 112 when(oldestMispredict.valid && !oldestMispredict.bits.roqIdx.needFlush(io.stage2Redirect, false.B)){ 113 s1_redirect_bits_reg := oldestMispredict.bits 114 s1_redirect_valid_reg := true.B 115 }.otherwise({ 116 s1_redirect_valid_reg := false.B 117 }) 118 io.stage2Redirect.valid := s1_redirect_valid_reg 119 io.stage2Redirect.bits := s1_redirect_bits_reg 120 io.stage2Redirect.bits.cfiUpdate := DontCare 121 // at stage2, we read ftq to get pc 122 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 123 124 // stage3, calculate redirect target 125 val s2_isJump = RegNext(s1_isJump) 126 val s2_jumpTarget = RegEnable(s1_jumpTarget, s1_redirect_valid_reg) 127 val s2_imm12_reg = RegEnable(s1_imm12_reg, s1_redirect_valid_reg) 128 val s2_pd = RegEnable(s1_pd, s1_redirect_valid_reg) 129 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 130 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg, init = false.B) 131 132 val ftqRead = io.stage2FtqRead.entry 133 val pc = GetPcByFtq(ftqRead.ftqPC, s2_redirect_bits_reg.ftqOffset, ftqRead.hasLastPrev) 134 val brTarget = pc + SignExt(ImmUnion.B.toImm32(s2_imm12_reg), XLEN) 135 val snpc = pc + Mux(s2_pd.isRVC, 2.U, 4.U) 136 val isReplay = RedirectLevel.flushItself(s2_redirect_bits_reg.level) 137 val target = Mux(isReplay, 138 pc, // repaly from itself 139 Mux(s2_redirect_bits_reg.cfiUpdate.taken, 140 Mux(s2_isJump, s2_jumpTarget, brTarget), 141 snpc 142 ) 143 ) 144 io.stage3Redirect.valid := s2_redirect_valid_reg 145 io.stage3Redirect.bits := s2_redirect_bits_reg 146 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 147 stage3CfiUpdate.pc := pc 148 stage3CfiUpdate.pd := s2_pd 149 stage3CfiUpdate.rasSp := ftqRead.rasSp 150 stage3CfiUpdate.rasEntry := ftqRead.rasTop 151 stage3CfiUpdate.hist := ftqRead.hist 152 stage3CfiUpdate.predHist := ftqRead.predHist 153 stage3CfiUpdate.specCnt := ftqRead.specCnt(s2_redirect_bits_reg.ftqOffset) 154 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 155 stage3CfiUpdate.sawNotTakenBranch := VecInit((0 until PredictWidth).map{ i => 156 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 157 })(s2_redirect_bits_reg.ftqOffset) 158 stage3CfiUpdate.target := target 159 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 160 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 161} 162 163class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 164 val io = IO(new Bundle { 165 val frontend = Flipped(new FrontendToBackendIO) 166 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 167 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 168 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 169 val toIntBlock = new CtrlToIntBlockIO 170 val toFpBlock = new CtrlToFpBlockIO 171 val toLsBlock = new CtrlToLsBlockIO 172 val roqio = new Bundle { 173 // to int block 174 val toCSR = new RoqCSRIO 175 val exception = ValidIO(new RoqExceptionInfo) 176 // to mem block 177 val lsq = new RoqLsqIO 178 } 179 }) 180 181 val difftestIO = IO(new Bundle() { 182 val fromRoq = new Bundle() { 183 val commit = Output(UInt(32.W)) 184 val thisPC = Output(UInt(XLEN.W)) 185 val thisINST = Output(UInt(32.W)) 186 val skip = Output(UInt(32.W)) 187 val wen = Output(UInt(32.W)) 188 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 189 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 190 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 191 val isRVC = Output(UInt(32.W)) 192 val scFailed = Output(Bool()) 193 } 194 }) 195 difftestIO <> DontCare 196 197 val ftq = Module(new Ftq) 198 val decode = Module(new DecodeStage) 199 val rename = Module(new Rename) 200 val dispatch = Module(new Dispatch) 201 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 202 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 203 val redirectGen = Module(new RedirectGenerator) 204 205 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 206 207 val roq = Module(new Roq(roqWbSize)) 208 209 val backendRedirect = redirectGen.io.stage2Redirect 210 val frontendRedirect = redirectGen.io.stage3Redirect 211 val flush = roq.io.flushOut.valid 212 213 redirectGen.io.exuMispredict.zip(io.fromIntBlock.exuRedirect).map({case (x, y) => 214 x.valid := y.valid && y.bits.redirect.cfiUpdate.isMisPred 215 x.bits := y.bits 216 }) 217 redirectGen.io.loadRelay := io.fromLsBlock.replay 218 219 ftq.io.enq <> io.frontend.fetchInfo 220 for(i <- 0 until CommitWidth){ 221 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 222 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 223 } 224 ftq.io.redirect <> backendRedirect 225 ftq.io.flush := flush 226 ftq.io.frontendRedirect <> frontendRedirect 227 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 228 229 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 230 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 231 232 io.frontend.redirect_cfiUpdate := frontendRedirect 233 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 234 io.frontend.ftqEnqPtr := ftq.io.enqPtr 235 io.frontend.ftqLeftOne := ftq.io.leftOne 236 237 decode.io.in <> io.frontend.cfVec 238 239 val jumpInst = dispatch.io.enqIQCtrl(0).bits 240 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 241 ftqOffsetReg := jumpInst.cf.ftqOffset 242 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 243 io.toIntBlock.jumpPc := GetPcByFtq( 244 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, ftq.io.ftqRead(0).entry.hasLastPrev 245 ) 246 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 247 248 // pipeline between decode and dispatch 249 for (i <- 0 until RenameWidth) { 250 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 251 backendRedirect.valid || frontendRedirect.valid) 252 } 253 254 rename.io.redirect <> backendRedirect 255 rename.io.flush := flush 256 rename.io.roqCommits <> roq.io.commits 257 rename.io.out <> dispatch.io.fromRename 258 rename.io.renameBypass <> dispatch.io.renameBypass 259 260 dispatch.io.redirect <> backendRedirect 261 dispatch.io.flush := flush 262 dispatch.io.enqRoq <> roq.io.enq 263 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 264 dispatch.io.readIntRf <> io.toIntBlock.readRf 265 dispatch.io.readFpRf <> io.toFpBlock.readRf 266 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 267 intBusyTable.io.allocPregs(i).valid := preg.isInt 268 fpBusyTable.io.allocPregs(i).valid := preg.isFp 269 intBusyTable.io.allocPregs(i).bits := preg.preg 270 fpBusyTable.io.allocPregs(i).bits := preg.preg 271 } 272 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 273 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 274// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 275 276 277 fpBusyTable.io.flush := flush 278 intBusyTable.io.flush := flush 279 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 280 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 281 setPhyRegRdy.bits := wb.bits.uop.pdest 282 } 283 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 284 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 285 setPhyRegRdy.bits := wb.bits.uop.pdest 286 } 287 intBusyTable.io.read <> dispatch.io.readIntState 288 fpBusyTable.io.read <> dispatch.io.readFpState 289 290 roq.io.redirect <> backendRedirect 291 roq.io.exeWbResults.zip( 292 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 293 ).foreach{ 294 case(x, y) => 295 x.bits := y.bits 296 x.valid := y.valid 297 } 298 299 // TODO: is 'backendRedirect' necesscary? 300 io.toIntBlock.redirect <> backendRedirect 301 io.toIntBlock.flush <> flush 302 io.toFpBlock.redirect <> backendRedirect 303 io.toFpBlock.flush <> flush 304 io.toLsBlock.redirect <> backendRedirect 305 io.toLsBlock.flush <> flush 306 307 if (env.DualCoreDifftest) { 308 difftestIO.fromRoq <> roq.difftestIO 309 } 310 311 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 312 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 313 314 // roq to int block 315 io.roqio.toCSR <> roq.io.csr 316 io.roqio.exception := roq.io.exception 317 // roq to mem block 318 io.roqio.lsq <> roq.io.lsq 319} 320