1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.DecodeStage 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort(XLEN))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 // int block only uses port 0~7 22 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 23 val redirect = ValidIO(new Redirect) 24} 25 26class CtrlToFpBlockIO extends XSBundle { 27 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 28 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort(XLEN + 1))) 29 // fp block uses port 0~11 30 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 31 val redirect = ValidIO(new Redirect) 32} 33 34class CtrlToLsBlockIO extends XSBundle { 35 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 36 val enqLsq = Flipped(new LsqEnqIO) 37 val redirect = ValidIO(new Redirect) 38} 39 40class RedirectGenerator extends XSModule with NeedImpl { 41 val io = IO(new Bundle() { 42 val loadRelay = Flipped(ValidIO(new Redirect)) 43 val exuMispredict = Vec(exuParameters.JmpCnt + exuParameters.AluCnt, Flipped(ValidIO(new ExuOutput))) 44 val roqRedirect = Flipped(ValidIO(new Redirect)) 45 val stage2FtqRead = new FtqRead 46 val stage2Redirect = ValidIO(new Redirect) 47 val stage3CfiUpdate = Output(ValidIO(new CfiUpdateInfo)) 48 }) 49 /* 50 loadReplay and roqRedirect already read cfi update info from ftq 51 exus haven't read, they need to read at stage 2 52 53 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 54 | | | | | | | 55 |============= reg & compare ====| | ======== 56 | | 57 | | 58 | | Stage2 59 | | 60 redirect (flush backend) | 61 | | 62 === reg === | ======== 63 | | 64 |----- mux (exception first) -----| Stage3 65 | 66 redirect (send to frontend) 67 */ 68} 69 70class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 71 val io = IO(new Bundle { 72 val frontend = Flipped(new FrontendToBackendIO) 73 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 74 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 75 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 76 val toIntBlock = new CtrlToIntBlockIO 77 val toFpBlock = new CtrlToFpBlockIO 78 val toLsBlock = new CtrlToLsBlockIO 79 val roqio = new Bundle { 80 // to int block 81 val toCSR = new RoqCSRIO 82 val exception = ValidIO(new MicroOp) 83 val isInterrupt = Output(Bool()) 84 // to mem block 85 val commits = new RoqCommitIO 86 val roqDeqPtr = Output(new RoqPtr) 87 } 88 }) 89 90 val ftq = Module(new Ftq) 91 val decode = Module(new DecodeStage) 92 val rename = Module(new Rename) 93 val dispatch = Module(new Dispatch) 94 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 95 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 96 val redirectGen = Module(new RedirectGenerator) 97 98 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 99 100 val roq = Module(new Roq(roqWbSize)) 101 102 val backendRedirect = redirectGen.io.stage2Redirect 103 val frontendRedirect = redirectGen.io.stage3CfiUpdate 104 105 ftq.io.enq <> io.frontend.fetchInfo 106 for(i <- 0 until CommitWidth){ 107 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) 108 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 109 } 110 ftq.io.redirect <> backendRedirect 111 ftq.io.exuWriteback <> io.fromIntBlock.exuRedirect 112 113 ftq.io.ftqRead(1) <> redirectGen.io.stage2FtqRead 114 ftq.io.ftqRead(2) <> DontCare // TODO: read exception pc form here 115 116 io.frontend.redirect_cfiUpdate := frontendRedirect 117 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 118 119 decode.io.in <> io.frontend.cfVec 120 121 val jumpInst = dispatch.io.enqIQCtrl(0).bits 122 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 123 io.toIntBlock.jumpPc := GetPcByFtq(ftq.io.ftqRead(0).entry.ftqPC, jumpInst.cf.ftqOffset) 124 125 // pipeline between decode and dispatch 126 for (i <- 0 until RenameWidth) { 127 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 128 backendRedirect.valid || frontendRedirect.valid) 129 } 130 131 rename.io.redirect <> backendRedirect 132 rename.io.roqCommits <> roq.io.commits 133 rename.io.out <> dispatch.io.fromRename 134 rename.io.renameBypass <> dispatch.io.renameBypass 135 136 dispatch.io.redirect <> backendRedirect 137 dispatch.io.enqRoq <> roq.io.enq 138 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 139 dispatch.io.readIntRf <> io.toIntBlock.readRf 140 dispatch.io.readFpRf <> io.toFpBlock.readRf 141 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 142 intBusyTable.io.allocPregs(i).valid := preg.isInt 143 fpBusyTable.io.allocPregs(i).valid := preg.isFp 144 intBusyTable.io.allocPregs(i).bits := preg.preg 145 fpBusyTable.io.allocPregs(i).bits := preg.preg 146 } 147 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 148 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 149// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 150 151 152 val flush = backendRedirect.valid && RedirectLevel.isUnconditional(backendRedirect.bits.level) 153 fpBusyTable.io.flush := flush 154 intBusyTable.io.flush := flush 155 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 156 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 157 setPhyRegRdy.bits := wb.bits.uop.pdest 158 } 159 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 160 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 161 setPhyRegRdy.bits := wb.bits.uop.pdest 162 } 163 intBusyTable.io.rfReadAddr <> dispatch.io.readIntRf.map(_.addr) 164 intBusyTable.io.pregRdy <> dispatch.io.intPregRdy 165 fpBusyTable.io.rfReadAddr <> dispatch.io.readFpRf.map(_.addr) 166 fpBusyTable.io.pregRdy <> dispatch.io.fpPregRdy 167 168 roq.io.redirect <> backendRedirect 169 roq.io.exeWbResults.zip( 170 io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut 171 ).foreach{ 172 case(x, y) => 173 x.bits := y.bits 174 x.valid := y.valid 175 } 176 177 // TODO: is 'backendRedirect' necesscary? 178 io.toIntBlock.redirect <> backendRedirect 179 io.toFpBlock.redirect <> backendRedirect 180 io.toLsBlock.redirect <> backendRedirect 181 182 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 183 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 184 185 // roq to int block 186 io.roqio.toCSR <> roq.io.csr 187 io.roqio.exception.valid := roq.io.redirectOut.valid && roq.io.redirectOut.bits.isException() 188 io.roqio.exception.bits := roq.io.exception 189 io.roqio.isInterrupt := roq.io.redirectOut.bits.interrupt 190 // roq to mem block 191 io.roqio.roqDeqPtr := roq.io.roqDeqPtr 192 io.roqio.commits := roq.io.commits 193} 194