1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import xiangshan._ 6import xiangshan.backend.decode.{DecodeBuffer, DecodeStage} 7import xiangshan.backend.rename.Rename 8import xiangshan.backend.brq.Brq 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.issue.ReservationStationNew 12import xiangshan.backend.regfile.RfReadPort 13import xiangshan.backend.roq.{Roq, RoqPtr} 14import xiangshan.mem._ 15import xiangshan.backend.fu.FunctionUnit._ 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val enqIqData = Vec(exuParameters.IntExuCnt, Output(new ExuInput)) 20 val readRf = Vec(NRIntReadPorts, Flipped(new RfReadPort)) 21} 22 23class CtrlToFpBlockIO extends XSBundle { 24 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 25 val enqIqData = Vec(exuParameters.FpExuCnt, Output(new ExuInput)) 26 val readRf = Vec(NRFpReadPorts, Flipped(new RfReadPort)) 27} 28 29class CtrlToLsBlockIO extends XSBundle { 30 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 31 val enqIqData = Vec(exuParameters.LsExuCnt, Output(new ExuInput)) 32 val lsqIdxReq = Vec(RenameWidth, DecoupledIO(new MicroOp)) 33} 34 35class CtrlBlock 36( 37 jmpCfg: ExuConfig, 38 aluCfg: ExuConfig, 39 mduCfg: ExuConfig, 40 fmacCfg: ExuConfig, 41 fmiscCfg: ExuConfig, 42 ldCfg: ExuConfig, 43 stCfg: ExuConfig 44) extends XSModule { 45 val io = IO(new Bundle { 46 val frontend = Flipped(new FrontendToBackendIO) 47 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 48 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 49 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 50 val toIntBlock = new CtrlToIntBlockIO 51 val toFpBlock = new CtrlToFpBlockIO 52 val toLsBlock = new CtrlToLsBlockIO 53 }) 54 55 val decode = Module(new DecodeStage) 56 val brq = Module(new Brq) 57 val decBuf = Module(new DecodeBuffer) 58 val rename = Module(new Rename) 59 val dispatch = Module(new Dispatch( 60 jmpCfg, aluCfg, mduCfg, 61 fmacCfg, fmiscCfg, 62 ldCfg, stCfg 63 )) 64 // TODO: move busyTable to dispatch1 65 // val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 66 // val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 67 val roq = Module(new Roq) 68 69 val fromExeBlock = (io.fromIntBlock, io.fromFpBlock, io.fromLsBlock) 70 val toExeBlock = (io.toIntBlock, io.toFpBlock, io.toLsBlock) 71 72 val redirect = Mux( 73 roq.io.redirect.valid, 74 roq.io.redirect, 75 Mux( 76 brq.io.redirect.valid, 77 brq.io.redirect, 78 io.fromLsBlock.replay 79 ) 80 ) 81 82 decode.io.in <> io.frontend.cfVec 83 decode.io.toBrq <> brq.io.enqReqs 84 decode.io.brTags <> brq.io.brTags 85 decode.io.out <> decBuf.io.in 86 87 decBuf.io.isWalking := roq.io.commits(0).valid && roq.io.commits(0).bits.isWalk 88 decBuf.io.redirect <> redirect 89 decBuf.io.out <> rename.io.in 90 91 rename.io.redirect <> redirect 92 rename.io.roqCommits <> roq.io.commits 93 // they should be moved to busytables 94 rename.io.wbIntResults <> io.fromIntBlock.wbIntRegs ++ io.fromFpBlock.wbIntRegs ++ io.fromLsBlock.wbIntRegs 95 rename.io.wbFpResults <> io.fromIntBlock.wbFpRegs ++ io.fromFpBlock.wbFpRegs ++ io.fromLsBlock.wbFpRegs 96 rename.io.intRfReadAddr <> dispatch.io.readIntRf.map(_.addr) 97 rename.io.fpRfReadAddr <> dispatch.io.readFpRf.map(_.addr) 98 rename.io.intPregRdy <> dispatch.io.intPregRdy 99 rename.io.fpPregRdy <> dispatch.io.fpPregRdy 100 rename.io.replayPregReq <> dispatch.io.replayPregReq 101 rename.io.out <> dispatch.io.fromRename 102 103 dispatch.io.redirect <> redirect 104 dispatch.io.toRoq <> roq.io.dp1Req 105 dispatch.io.roqIdxs <> roq.io.roqIdxs 106 dispatch.io.toLsroq <> io.toLsBlock.lsqIdxReq 107 dispatch.io.lsIdxs <> io.fromLsBlock.lsqIdxResp 108 dispatch.io.dequeueRoqIndex.valid := roq.io.commitRoqIndex.valid || io.fromLsBlock.oldestStore.valid 109 dispatch.io.dequeueRoqIndex.bits := Mux(io.fromLsBlock.oldestStore.valid, io.fromLsBlock.oldestStore.bits, roq.io.commitRoqIndex.bits) 110 dispatch.io.readIntRf <> io.toIntBlock.readRf 111 dispatch.io.readFpRf <> io.toFpBlock.readRf 112 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 113 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 114 dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 115 116 // val flush = redirect.valid && (redirect.bits.isException || redirect.bits.isFlushPipe) 117 // fpBusyTable.flush := flush 118 // intBusyTable.flush := flush 119 // busytable io 120 // maybe update busytable in dispatch1? 121 122} 123