1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* Copyright (c) 2020-2021 Peng Cheng Laboratory 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package xiangshan.backend 18 19import chipsalliance.rocketchip.config.Parameters 20import chisel3._ 21import chisel3.util._ 22import utils._ 23import xiangshan._ 24import xiangshan.backend.decode.{DecodeStage, ImmUnion} 25import xiangshan.backend.rename.{BusyTable, Rename} 26import xiangshan.backend.dispatch.Dispatch 27import xiangshan.backend.exu._ 28import xiangshan.frontend.{FtqRead, FtqToCtrlIO, FtqPtr} 29import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 30import xiangshan.mem.LsqEnqIO 31 32class CtrlToFtqIO(implicit p: Parameters) extends XSBundle { 33 val roq_commits = Vec(CommitWidth, Valid(new RoqCommitInfo)) 34 val stage2Redirect = Valid(new Redirect) 35 val stage3Redirect = ValidIO(new Redirect) 36 val roqFlush = Valid(new Bundle { 37 val ftqIdx = Output(new FtqPtr) 38 val ftqOffset = Output(UInt(log2Up(PredictWidth).W)) 39 }) 40} 41 42class RedirectGenerator(implicit p: Parameters) extends XSModule 43 with HasCircularQueuePtrHelper { 44 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 45 val io = IO(new Bundle() { 46 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 47 val loadReplay = Flipped(ValidIO(new Redirect)) 48 val flush = Input(Bool()) 49 val stage1PcRead = Vec(numRedirect+1, new FtqRead(UInt(VAddrBits.W))) 50 val stage2Redirect = ValidIO(new Redirect) 51 val stage3Redirect = ValidIO(new Redirect) 52 val memPredUpdate = Output(new MemPredUpdateReq) 53 val memPredPcRead = new FtqRead(UInt(VAddrBits.W)) // read req send form stage 2 54 }) 55 /* 56 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 57 | | | | | | | 58 |============= reg & compare =====| | ======== 59 | | 60 | | 61 | | Stage2 62 | | 63 redirect (flush backend) | 64 | | 65 === reg === | ======== 66 | | 67 |----- mux (exception first) -----| Stage3 68 | 69 redirect (send to frontend) 70 */ 71 private class Wrapper(val n: Int) extends Bundle { 72 val redirect = new Redirect 73 val valid = Bool() 74 val idx = UInt(log2Up(n).W) 75 } 76 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 77 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 78 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 79 (if (j < i) !xs(j).valid || compareVec(i)(j) 80 else if (j == i) xs(i).valid 81 else !xs(j).valid || !compareVec(j)(i)) 82 )).andR)) 83 resultOnehot 84 } 85 86 val redirects = io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 87 val stage1FtqReadPcs = 88 (io.stage1PcRead zip redirects).map{ case (r, redirect) => 89 r(redirect.ftqIdx, redirect.ftqOffset) 90 } 91 92 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 93 val redirect = Wire(Valid(new Redirect)) 94 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 95 redirect.bits := exuOut.bits.redirect 96 redirect 97 } 98 99 val jumpOut = io.exuMispredict.head 100 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 101 val oldestOneHot = selectOldestRedirect(allRedirect) 102 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 103 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 104 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 105 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 106 107 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 108 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 109 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 110 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 111 val s1_redirect_valid_reg = RegNext(oldestValid) 112 val s1_redirect_onehot = RegNext(oldestOneHot) 113 114 // stage1 -> stage2 115 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 116 io.stage2Redirect.bits := s1_redirect_bits_reg 117 io.stage2Redirect.bits.cfiUpdate := DontCare 118 119 val s1_isReplay = s1_redirect_onehot.last 120 val s1_isJump = s1_redirect_onehot.head 121 val real_pc = Mux1H(s1_redirect_onehot, stage1FtqReadPcs) 122 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 123 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 124 val target = Mux(s1_isReplay, 125 real_pc, // repaly from itself 126 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 127 Mux(s1_isJump, s1_jumpTarget, brTarget), 128 snpc 129 ) 130 ) 131 132 // get pc from ftq 133 // valid only if redirect is caused by load violation 134 // store_pc is used to update store set 135 val store_pc = io.memPredPcRead(s1_redirect_bits_reg.stFtqIdx, s1_redirect_bits_reg.stFtqOffset) 136 137 // update load violation predictor if load violation redirect triggered 138 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 139 // update wait table 140 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 141 io.memPredUpdate.wdata := true.B 142 // update store set 143 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 144 // store pc is ready 1 cycle after s1_isReplay is judged 145 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 146 147 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 148 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 149 val s2_pc = RegEnable(real_pc, enable = s1_redirect_valid_reg) 150 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 151 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 152 153 io.stage3Redirect.valid := s2_redirect_valid_reg 154 io.stage3Redirect.bits := s2_redirect_bits_reg 155 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 156 stage3CfiUpdate.pc := s2_pc 157 stage3CfiUpdate.pd := s2_pd 158 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 159 stage3CfiUpdate.target := s2_target 160 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 161 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 162} 163 164class CtrlBlock(implicit p: Parameters) extends XSModule 165 with HasCircularQueuePtrHelper { 166 val io = IO(new Bundle { 167 val frontend = Flipped(new FrontendToCtrlIO) 168 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 169 // from int block 170 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 171 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 172 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 173 val memoryViolation = Flipped(ValidIO(new Redirect)) 174 val enqLsq = Flipped(new LsqEnqIO) 175 val jumpPc = Output(UInt(VAddrBits.W)) 176 val jalr_target = Output(UInt(VAddrBits.W)) 177 val roqio = new Bundle { 178 // to int block 179 val toCSR = new RoqCSRIO 180 val exception = ValidIO(new ExceptionInfo) 181 // to mem block 182 val lsq = new RoqLsqIO 183 } 184 val csrCtrl = Input(new CustomCSRCtrlIO) 185 val perfInfo = Output(new Bundle{ 186 val ctrlInfo = new Bundle { 187 val roqFull = Input(Bool()) 188 val intdqFull = Input(Bool()) 189 val fpdqFull = Input(Bool()) 190 val lsdqFull = Input(Bool()) 191 } 192 }) 193 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 194 // redirect out 195 val redirect = ValidIO(new Redirect) 196 val flush = Output(Bool()) 197 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 198 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 199 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 200 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 201 }) 202 203 val decode = Module(new DecodeStage) 204 val rename = Module(new Rename) 205 val dispatch = Module(new Dispatch) 206 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 207 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 208 val redirectGen = Module(new RedirectGenerator) 209 210 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 211 val roq = Module(new Roq(roqWbSize)) 212 213 val stage2Redirect = redirectGen.io.stage2Redirect 214 val stage3Redirect = redirectGen.io.stage3Redirect 215 val flush = roq.io.flushOut.valid 216 val flushReg = RegNext(flush) 217 218 val exuRedirect = io.exuRedirect.map(x => { 219 val valid = x.valid && x.bits.redirectValid 220 val killedByOlder = x.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg) 221 val delayed = Wire(Valid(new ExuOutput)) 222 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 223 delayed.bits := RegEnable(x.bits, x.valid) 224 delayed 225 }) 226 val loadReplay = Wire(Valid(new Redirect)) 227 loadReplay.valid := RegNext(io.memoryViolation.valid && 228 !io.memoryViolation.bits.roqIdx.needFlush(stage2Redirect, flushReg), 229 init = false.B 230 ) 231 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 232 io.frontend.fromFtq.getRedirectPcRead <> redirectGen.io.stage1PcRead 233 io.frontend.fromFtq.getMemPredPcRead <> redirectGen.io.memPredPcRead 234 redirectGen.io.exuMispredict <> exuRedirect 235 redirectGen.io.loadReplay <> loadReplay 236 redirectGen.io.flush := flushReg 237 238 for(i <- 0 until CommitWidth){ 239 io.frontend.toFtq.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 240 io.frontend.toFtq.roq_commits(i).bits := roq.io.commits.info(i) 241 } 242 io.frontend.toFtq.stage2Redirect <> stage2Redirect 243 io.frontend.toFtq.roqFlush <> RegNext(roq.io.flushOut) 244 245 val roqPcRead = io.frontend.fromFtq.getRoqFlushPcRead 246 val flushPC = roqPcRead(roq.io.flushOut.bits.ftqIdx, roq.io.flushOut.bits.ftqOffset) 247 248 val flushRedirect = Wire(Valid(new Redirect)) 249 flushRedirect.valid := flushReg 250 flushRedirect.bits := DontCare 251 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 252 flushRedirect.bits.interrupt := true.B 253 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 254 io.roqio.toCSR.trapTarget, 255 flushPC + 4.U // flush pipe 256 ) 257 val flushRedirectReg = Wire(Valid(new Redirect)) 258 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 259 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 260 261 io.frontend.toFtq.stage3Redirect := Mux(flushRedirectReg.valid, flushRedirectReg, stage3Redirect) 262 263 decode.io.in <> io.frontend.cfVec 264 // currently, we only update wait table when isReplay 265 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 266 decode.io.memPredUpdate(1) := DontCare 267 decode.io.memPredUpdate(1).valid := false.B 268 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 269 decode.io.csrCtrl := RegNext(io.csrCtrl) 270 271 272 val jumpInst = dispatch.io.enqIQCtrl(0).bits 273 val jumpPcRead = io.frontend.fromFtq.getJumpPcRead 274 io.jumpPc := jumpPcRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 275 val jumpTargetRead = io.frontend.fromFtq.target_read 276 io.jalr_target := jumpTargetRead(jumpInst.cf.ftqPtr, jumpInst.cf.ftqOffset) 277 278 // pipeline between decode and dispatch 279 for (i <- 0 until RenameWidth) { 280 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 281 flushReg || io.frontend.toFtq.stage3Redirect.valid) 282 } 283 284 rename.io.redirect <> stage2Redirect 285 rename.io.flush := flushReg 286 rename.io.roqCommits <> roq.io.commits 287 rename.io.out <> dispatch.io.fromRename 288 rename.io.renameBypass <> dispatch.io.renameBypass 289 rename.io.dispatchInfo <> dispatch.io.preDpInfo 290 291 dispatch.io.redirect <> stage2Redirect 292 dispatch.io.flush := flushReg 293 dispatch.io.enqRoq <> roq.io.enq 294 dispatch.io.enqLsq <> io.enqLsq 295 dispatch.io.singleStep := false.B 296 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 297 intBusyTable.io.allocPregs(i).valid := preg.isInt 298 fpBusyTable.io.allocPregs(i).valid := preg.isFp 299 intBusyTable.io.allocPregs(i).bits := preg.preg 300 fpBusyTable.io.allocPregs(i).bits := preg.preg 301 } 302 dispatch.io.enqIQCtrl := DontCare 303 io.enqIQ <> dispatch.io.enqIQCtrl 304 dispatch.io.csrCtrl <> io.csrCtrl 305 dispatch.io.storeIssue <> io.stIn 306 dispatch.io.readIntRf <> io.readIntRf 307 dispatch.io.readFpRf <> io.readFpRf 308 309 fpBusyTable.io.flush := flushReg 310 intBusyTable.io.flush := flushReg 311 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 312 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 313 setPhyRegRdy.bits := wb.bits.uop.pdest 314 } 315 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 316 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 317 setPhyRegRdy.bits := wb.bits.uop.pdest 318 } 319 intBusyTable.io.read <> dispatch.io.readIntState 320 fpBusyTable.io.read <> dispatch.io.readFpState 321 322 roq.io.redirect <> stage2Redirect 323 val exeWbResults = VecInit(io.writeback ++ io.stOut) 324 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 325 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(stage2Redirect, flushReg)) 326 roq_wb.bits := RegNext(wb.bits) 327 } 328 329 // TODO: is 'backendRedirect' necesscary? 330 io.redirect <> stage2Redirect 331 io.flush <> flushReg 332 io.debug_int_rat <> rename.io.debug_int_rat 333 io.debug_fp_rat <> rename.io.debug_fp_rat 334 335// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 336// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 337 338 // roq to int block 339 io.roqio.toCSR <> roq.io.csr 340 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 341 io.roqio.exception := roq.io.exception 342 io.roqio.exception.bits.uop.cf.pc := flushPC 343 // roq to mem block 344 io.roqio.lsq <> roq.io.lsq 345 346 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 347 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 348 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 349 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 350} 351