1package xiangshan.backend 2 3import chisel3._ 4import chisel3.util._ 5import utils._ 6import xiangshan._ 7import xiangshan.backend.decode.{DecodeStage, ImmUnion, WaitTableParameters} 8import xiangshan.backend.rename.{BusyTable, Rename} 9import xiangshan.backend.dispatch.Dispatch 10import xiangshan.backend.exu._ 11import xiangshan.backend.exu.Exu.exuConfigs 12import xiangshan.backend.ftq.{Ftq, FtqRead, GetPcByFtq} 13import xiangshan.backend.regfile.RfReadPort 14import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 15import xiangshan.mem.LsqEnqIO 16 17class CtrlToIntBlockIO extends XSBundle { 18 val enqIqCtrl = Vec(exuParameters.IntExuCnt, DecoupledIO(new MicroOp)) 19 val readRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 20 val jumpPc = Output(UInt(VAddrBits.W)) 21 val jalr_target = Output(UInt(VAddrBits.W)) 22 // int block only uses port 0~7 23 val readPortIndex = Vec(exuParameters.IntExuCnt, Output(UInt(log2Ceil(8 / 2).W))) // TODO parameterize 8 here 24 val redirect = ValidIO(new Redirect) 25 val flush = Output(Bool()) 26} 27 28class CtrlToFpBlockIO extends XSBundle { 29 val enqIqCtrl = Vec(exuParameters.FpExuCnt, DecoupledIO(new MicroOp)) 30 val readRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 31 // fp block uses port 0~11 32 val readPortIndex = Vec(exuParameters.FpExuCnt, Output(UInt(log2Ceil((NRFpReadPorts - exuParameters.StuCnt) / 3).W))) 33 val redirect = ValidIO(new Redirect) 34 val flush = Output(Bool()) 35} 36 37class CtrlToLsBlockIO extends XSBundle { 38 val enqIqCtrl = Vec(exuParameters.LsExuCnt, DecoupledIO(new MicroOp)) 39 val enqLsq = Flipped(new LsqEnqIO) 40 val waitTableUpdate = Vec(StorePipelineWidth, Input(new WaitTableUpdateReq)) 41 val redirect = ValidIO(new Redirect) 42 val flush = Output(Bool()) 43} 44 45class RedirectGenerator extends XSModule with HasCircularQueuePtrHelper with WaitTableParameters { 46 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 47 val io = IO(new Bundle() { 48 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 49 val loadReplay = Flipped(ValidIO(new Redirect)) 50 val flush = Input(Bool()) 51 val stage1FtqRead = Vec(numRedirect + 1, new FtqRead) 52 val stage2FtqRead = new FtqRead 53 val stage2Redirect = ValidIO(new Redirect) 54 val stage3Redirect = ValidIO(new Redirect) 55 val waitTableUpdate = Output(new WaitTableUpdateReq) 56 }) 57 /* 58 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 59 | | | | | | | 60 |============= reg & compare =====| | ======== 61 | | 62 | | 63 | | Stage2 64 | | 65 redirect (flush backend) | 66 | | 67 === reg === | ======== 68 | | 69 |----- mux (exception first) -----| Stage3 70 | 71 redirect (send to frontend) 72 */ 73 private class Wrapper(val n: Int) extends Bundle { 74 val redirect = new Redirect 75 val valid = Bool() 76 val idx = UInt(log2Up(n).W) 77 } 78 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): (Valid[Redirect], UInt) = { 79 val wrappers = for((r, i) <- xs.zipWithIndex) yield { 80 val wrap = Wire(new Wrapper(xs.size)) 81 wrap.redirect := r.bits 82 wrap.valid := r.valid 83 wrap.idx := i.U 84 wrap 85 } 86 val oldest = ParallelOperation[Wrapper](wrappers, (x, y) => { 87 Mux(x.valid, 88 Mux(y.valid, Mux(isAfter(x.redirect.roqIdx, y.redirect.roqIdx), y, x), x), y 89 ) 90 }) 91 val result = Wire(Valid(new Redirect)) 92 result.valid := oldest.valid 93 result.bits := oldest.redirect 94 (result, oldest.idx) 95 } 96 97 for((ptr, redirect) <- io.stage1FtqRead.map(_.ptr).zip( 98 io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 99 )){ ptr := redirect.ftqIdx } 100 101 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 102 val redirect = Wire(Valid(new Redirect)) 103 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 104 redirect.bits := exuOut.bits.redirect 105 redirect 106 } 107 108 val jumpOut = io.exuMispredict.head 109 val aluOut = VecInit(io.exuMispredict.tail) 110 val (oldestAluRedirect, oldestAluIdx) = selectOldestRedirect(aluOut.map(getRedirect)) 111 val (oldestExuRedirect, jumpIsOlder) = selectOldestRedirect(Seq( 112 oldestAluRedirect, getRedirect(jumpOut) 113 )) 114 val oldestExuOutput = Mux(jumpIsOlder.asBool(), jumpOut, aluOut(oldestAluIdx)) 115 val (oldestRedirect, _) = selectOldestRedirect(Seq(io.loadReplay, oldestExuRedirect)) 116 117 val s1_isJump = RegNext(jumpIsOlder.asBool(), init = false.B) 118 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 119 val s1_imm12_reg = RegEnable(oldestExuOutput.bits.uop.ctrl.imm(11, 0), oldestExuOutput.valid) 120 val s1_pd = RegEnable(oldestExuOutput.bits.uop.cf.pd, oldestExuOutput.valid) 121 val s1_redirect_bits_reg = Reg(new Redirect) 122 val s1_redirect_valid_reg = RegInit(false.B) 123 val s1_aluIdx = RegEnable(oldestAluIdx, oldestAluRedirect.valid) 124 125 // stage1 -> stage2 126 when(oldestRedirect.valid && !oldestRedirect.bits.roqIdx.needFlush(io.stage2Redirect, io.flush)){ 127 s1_redirect_bits_reg := oldestRedirect.bits 128 s1_redirect_valid_reg := true.B 129 }.otherwise({ 130 s1_redirect_valid_reg := false.B 131 }) 132 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 133 io.stage2Redirect.bits := s1_redirect_bits_reg 134 io.stage2Redirect.bits.cfiUpdate := DontCare 135 // at stage2, we read ftq to get pc 136 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 137 138 val isReplay = RedirectLevel.flushItself(s1_redirect_bits_reg.level) 139 val ftqRead = Mux(isReplay, 140 io.stage1FtqRead.last.entry, 141 Mux( 142 s1_isJump, 143 io.stage1FtqRead.head.entry, 144 VecInit(io.stage1FtqRead.tail.take(exuParameters.AluCnt).map(_.entry))(s1_aluIdx) 145 ) 146 ) 147 val cfiUpdate_pc = Cat( 148 ftqRead.ftqPC.head(VAddrBits - s1_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 149 s1_redirect_bits_reg.ftqOffset, 150 0.U(instOffsetBits.W) 151 ) 152 val real_pc = GetPcByFtq(ftqRead.ftqPC, s1_redirect_bits_reg.ftqOffset, 153 ftqRead.lastPacketPC.valid, 154 ftqRead.lastPacketPC.bits 155 ) 156 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 157 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 158 val target = Mux(isReplay, 159 real_pc, // repaly from itself 160 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 161 Mux(s1_isJump, s1_jumpTarget, brTarget), 162 snpc 163 ) 164 ) 165 166 // update waittable if load violation redirect triggered 167 io.waitTableUpdate.valid := RegNext(isReplay && s1_redirect_valid_reg, init = false.B) 168 io.waitTableUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), WaitTableAddrWidth)) 169 io.waitTableUpdate.wdata := true.B 170 171 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 172 173 val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) 174 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 175 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 176 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 177 val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) 178 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 179 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 180 val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) 181 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 182 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 183 val s2_ftqRead = io.stage2FtqRead.entry 184 185 io.stage3Redirect.valid := s2_redirect_valid_reg 186 io.stage3Redirect.bits := s2_redirect_bits_reg 187 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 188 stage3CfiUpdate.pc := s2_cfiUpdata_pc 189 stage3CfiUpdate.pd := s2_pd 190 stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 191 stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 192 stage3CfiUpdate.predHist := s2_ftqRead.predHist 193 stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 194 stage3CfiUpdate.hist := s2_hist 195 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 196 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 197 stage3CfiUpdate.target := s2_target 198 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 199 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 200} 201 202class CtrlBlock extends XSModule with HasCircularQueuePtrHelper { 203 val io = IO(new Bundle { 204 val frontend = Flipped(new FrontendToBackendIO) 205 val fromIntBlock = Flipped(new IntBlockToCtrlIO) 206 val fromFpBlock = Flipped(new FpBlockToCtrlIO) 207 val fromLsBlock = Flipped(new LsBlockToCtrlIO) 208 val toIntBlock = new CtrlToIntBlockIO 209 val toFpBlock = new CtrlToFpBlockIO 210 val toLsBlock = new CtrlToLsBlockIO 211 val roqio = new Bundle { 212 // to int block 213 val toCSR = new RoqCSRIO 214 val exception = ValidIO(new ExceptionInfo) 215 // to mem block 216 val lsq = new RoqLsqIO 217 } 218 val csrCtrl = Input(new CustomCSRCtrlIO) 219 }) 220 221 val difftestIO = IO(new Bundle() { 222 val fromRoq = new Bundle() { 223 val commit = Output(UInt(32.W)) 224 val thisPC = Output(UInt(XLEN.W)) 225 val thisINST = Output(UInt(32.W)) 226 val skip = Output(UInt(32.W)) 227 val wen = Output(UInt(32.W)) 228 val wdata = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 229 val wdst = Output(Vec(CommitWidth, UInt(32.W))) // set difftest width to 6 230 val wpc = Output(Vec(CommitWidth, UInt(XLEN.W))) // set difftest width to 6 231 val isRVC = Output(UInt(32.W)) 232 val scFailed = Output(Bool()) 233 val lpaddr = Output(Vec(CommitWidth, UInt(64.W))) 234 val ltype = Output(Vec(CommitWidth, UInt(32.W))) 235 val lfu = Output(Vec(CommitWidth, UInt(4.W))) 236 } 237 }) 238 difftestIO <> DontCare 239 240 val ftq = Module(new Ftq) 241 val trapIO = IO(new TrapIO()) 242 trapIO <> DontCare 243 244 val decode = Module(new DecodeStage) 245 val rename = Module(new Rename) 246 val dispatch = Module(new Dispatch) 247 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 248 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 249 val redirectGen = Module(new RedirectGenerator) 250 251 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 252 val roq = Module(new Roq(roqWbSize)) 253 254 val backendRedirect = redirectGen.io.stage2Redirect 255 val frontendRedirect = redirectGen.io.stage3Redirect 256 val flush = roq.io.flushOut.valid 257 val flushReg = RegNext(flush) 258 259 val exuRedirect = io.fromIntBlock.exuRedirect.map(x => { 260 val valid = x.valid && x.bits.redirectValid 261 val killedByOlder = x.bits.uop.roqIdx.needFlush(backendRedirect, flushReg) 262 val delayed = Wire(Valid(new ExuOutput)) 263 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 264 delayed.bits := RegEnable(x.bits, x.valid) 265 delayed 266 }) 267 val loadReplay = Wire(Valid(new Redirect)) 268 loadReplay.valid := RegNext(io.fromLsBlock.replay.valid && 269 !io.fromLsBlock.replay.bits.roqIdx.needFlush(backendRedirect, flushReg), 270 init = false.B 271 ) 272 loadReplay.bits := RegEnable(io.fromLsBlock.replay.bits, io.fromLsBlock.replay.valid) 273 VecInit(ftq.io.ftqRead.tail.dropRight(1)) <> redirectGen.io.stage1FtqRead 274 ftq.io.cfiRead <> redirectGen.io.stage2FtqRead 275 redirectGen.io.exuMispredict <> exuRedirect 276 redirectGen.io.loadReplay <> loadReplay 277 redirectGen.io.flush := flushReg 278 279 ftq.io.enq <> io.frontend.fetchInfo 280 for(i <- 0 until CommitWidth){ 281 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 282 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 283 } 284 ftq.io.redirect <> backendRedirect 285 ftq.io.flush := flushReg 286 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 287 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 288 ftq.io.frontendRedirect <> frontendRedirect 289 ftq.io.exuWriteback <> exuRedirect 290 291 ftq.io.ftqRead.last.ptr := roq.io.flushOut.bits.ftqIdx 292 val flushPC = GetPcByFtq( 293 ftq.io.ftqRead.last.entry.ftqPC, 294 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 295 ftq.io.ftqRead.last.entry.lastPacketPC.valid, 296 ftq.io.ftqRead.last.entry.lastPacketPC.bits 297 ) 298 299 val flushRedirect = Wire(Valid(new Redirect)) 300 flushRedirect.valid := flushReg 301 flushRedirect.bits := DontCare 302 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 303 flushRedirect.bits.interrupt := true.B 304 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 305 io.roqio.toCSR.trapTarget, 306 flushPC + 4.U // flush pipe 307 ) 308 val flushRedirectReg = Wire(Valid(new Redirect)) 309 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 310 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 311 312 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, frontendRedirect) 313 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 314 io.frontend.ftqEnqPtr := ftq.io.enqPtr 315 io.frontend.ftqLeftOne := ftq.io.leftOne 316 317 decode.io.in <> io.frontend.cfVec 318 // currently, we only update wait table when isReplay 319 decode.io.waitTableUpdate(0) <> RegNext(redirectGen.io.waitTableUpdate) 320 decode.io.waitTableUpdate(1) := DontCare 321 decode.io.waitTableUpdate(1).valid := false.B 322 // decode.io.waitTableUpdate <> io.toLsBlock.waitTableUpdate 323 decode.io.csrCtrl := RegNext(io.csrCtrl) 324 325 326 val jumpInst = dispatch.io.enqIQCtrl(0).bits 327 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 328 ftqOffsetReg := jumpInst.cf.ftqOffset 329 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 330 io.toIntBlock.jumpPc := GetPcByFtq( 331 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 332 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 333 ftq.io.ftqRead(0).entry.lastPacketPC.bits 334 ) 335 io.toIntBlock.jalr_target := ftq.io.ftqRead(0).entry.target 336 337 // pipeline between decode and dispatch 338 for (i <- 0 until RenameWidth) { 339 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 340 flushReg || io.frontend.redirect_cfiUpdate.valid) 341 } 342 343 rename.io.redirect <> backendRedirect 344 rename.io.flush := flushReg 345 rename.io.roqCommits <> roq.io.commits 346 rename.io.out <> dispatch.io.fromRename 347 rename.io.renameBypass <> dispatch.io.renameBypass 348 rename.io.dispatchInfo <> dispatch.io.preDpInfo 349 350 dispatch.io.redirect <> backendRedirect 351 dispatch.io.flush := flushReg 352 dispatch.io.enqRoq <> roq.io.enq 353 dispatch.io.enqLsq <> io.toLsBlock.enqLsq 354 dispatch.io.readIntRf <> io.toIntBlock.readRf 355 dispatch.io.readFpRf <> io.toFpBlock.readRf 356 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 357 intBusyTable.io.allocPregs(i).valid := preg.isInt 358 fpBusyTable.io.allocPregs(i).valid := preg.isFp 359 intBusyTable.io.allocPregs(i).bits := preg.preg 360 fpBusyTable.io.allocPregs(i).bits := preg.preg 361 } 362 dispatch.io.numExist <> io.fromIntBlock.numExist ++ io.fromFpBlock.numExist ++ io.fromLsBlock.numExist 363 dispatch.io.enqIQCtrl <> io.toIntBlock.enqIqCtrl ++ io.toFpBlock.enqIqCtrl ++ io.toLsBlock.enqIqCtrl 364// dispatch.io.enqIQData <> io.toIntBlock.enqIqData ++ io.toFpBlock.enqIqData ++ io.toLsBlock.enqIqData 365 366 367 fpBusyTable.io.flush := flushReg 368 intBusyTable.io.flush := flushReg 369 for((wb, setPhyRegRdy) <- io.fromIntBlock.wbRegs.zip(intBusyTable.io.wbPregs)){ 370 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 371 setPhyRegRdy.bits := wb.bits.uop.pdest 372 } 373 for((wb, setPhyRegRdy) <- io.fromFpBlock.wbRegs.zip(fpBusyTable.io.wbPregs)){ 374 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 375 setPhyRegRdy.bits := wb.bits.uop.pdest 376 } 377 intBusyTable.io.read <> dispatch.io.readIntState 378 fpBusyTable.io.read <> dispatch.io.readFpState 379 380 roq.io.redirect <> backendRedirect 381 val exeWbResults = VecInit(io.fromIntBlock.wbRegs ++ io.fromFpBlock.wbRegs ++ io.fromLsBlock.stOut) 382 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 383 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(backendRedirect, flushReg)) 384 roq_wb.bits := RegNext(wb.bits) 385 } 386 387 // TODO: is 'backendRedirect' necesscary? 388 io.toIntBlock.redirect <> backendRedirect 389 io.toIntBlock.flush <> flushReg 390 io.toFpBlock.redirect <> backendRedirect 391 io.toFpBlock.flush <> flushReg 392 io.toLsBlock.redirect <> backendRedirect 393 io.toLsBlock.flush <> flushReg 394 395 if (!env.FPGAPlatform) { 396 difftestIO.fromRoq <> roq.difftestIO 397 trapIO <> roq.trapIO 398 } 399 400 dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 401 dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 402 403 // roq to int block 404 io.roqio.toCSR <> roq.io.csr 405 io.roqio.exception := roq.io.exception 406 io.roqio.exception.bits.uop.cf.pc := flushPC 407 // roq to mem block 408 io.roqio.lsq <> roq.io.lsq 409} 410