1/*************************************************************************************** 2* Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences 3* 4* XiangShan is licensed under Mulan PSL v2. 5* You can use this software according to the terms and conditions of the Mulan PSL v2. 6* You may obtain a copy of Mulan PSL v2 at: 7* http://license.coscl.org.cn/MulanPSL2 8* 9* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 10* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 11* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 12* 13* See the Mulan PSL v2 for more details. 14***************************************************************************************/ 15 16package xiangshan.backend 17 18import chipsalliance.rocketchip.config.Parameters 19import chisel3._ 20import chisel3.util._ 21import utils._ 22import xiangshan._ 23import xiangshan.backend.decode.{DecodeStage, ImmUnion} 24import xiangshan.backend.rename.{BusyTable, Rename} 25import xiangshan.backend.dispatch.Dispatch 26import xiangshan.backend.exu._ 27import xiangshan.backend.ftq.{Ftq, FtqRead, HasFtqHelper} 28import xiangshan.backend.roq.{Roq, RoqCSRIO, RoqLsqIO, RoqPtr} 29import xiangshan.mem.LsqEnqIO 30 31class RedirectGenerator(implicit p: Parameters) extends XSModule 32 with HasCircularQueuePtrHelper with HasFtqHelper { 33 val numRedirect = exuParameters.JmpCnt + exuParameters.AluCnt 34 val io = IO(new Bundle() { 35 val exuMispredict = Vec(numRedirect, Flipped(ValidIO(new ExuOutput))) 36 val loadReplay = Flipped(ValidIO(new Redirect)) 37 val flush = Input(Bool()) 38 val stage1FtqRead = Vec(numRedirect + 1, new FtqRead) 39 val stage2FtqRead = new FtqRead 40 val stage2Redirect = ValidIO(new Redirect) 41 val stage3Redirect = ValidIO(new Redirect) 42 val memPredUpdate = Output(new MemPredUpdateReq) 43 val memPredFtqRead = new FtqRead // read req send form stage 2 44 }) 45 /* 46 LoadQueue Jump ALU0 ALU1 ALU2 ALU3 exception Stage1 47 | | | | | | | 48 |============= reg & compare =====| | ======== 49 | | 50 | | 51 | | Stage2 52 | | 53 redirect (flush backend) | 54 | | 55 === reg === | ======== 56 | | 57 |----- mux (exception first) -----| Stage3 58 | 59 redirect (send to frontend) 60 */ 61 private class Wrapper(val n: Int) extends Bundle { 62 val redirect = new Redirect 63 val valid = Bool() 64 val idx = UInt(log2Up(n).W) 65 } 66 def selectOldestRedirect(xs: Seq[Valid[Redirect]]): Vec[Bool] = { 67 val compareVec = (0 until xs.length).map(i => (0 until i).map(j => isAfter(xs(j).bits.roqIdx, xs(i).bits.roqIdx))) 68 val resultOnehot = VecInit((0 until xs.length).map(i => Cat((0 until xs.length).map(j => 69 (if (j < i) !xs(j).valid || compareVec(i)(j) 70 else if (j == i) xs(i).valid 71 else !xs(j).valid || !compareVec(j)(i)) 72 )).andR)) 73 resultOnehot 74 } 75 76 for((ptr, redirect) <- io.stage1FtqRead.map(_.ptr).zip( 77 io.exuMispredict.map(_.bits.redirect) :+ io.loadReplay.bits 78 )){ ptr := redirect.ftqIdx } 79 80 def getRedirect(exuOut: Valid[ExuOutput]): ValidIO[Redirect] = { 81 val redirect = Wire(Valid(new Redirect)) 82 redirect.valid := exuOut.valid && exuOut.bits.redirect.cfiUpdate.isMisPred 83 redirect.bits := exuOut.bits.redirect 84 redirect 85 } 86 87 val jumpOut = io.exuMispredict.head 88 val allRedirect = VecInit(io.exuMispredict.map(x => getRedirect(x)) :+ io.loadReplay) 89 val oldestOneHot = selectOldestRedirect(allRedirect) 90 val needFlushVec = VecInit(allRedirect.map(_.bits.roqIdx.needFlush(io.stage2Redirect, io.flush))) 91 val oldestValid = VecInit(oldestOneHot.zip(needFlushVec).map{ case (v, f) => v && !f }).asUInt.orR 92 val oldestExuOutput = Mux1H(io.exuMispredict.indices.map(oldestOneHot), io.exuMispredict) 93 val oldestRedirect = Mux1H(oldestOneHot, allRedirect) 94 95 val s1_jumpTarget = RegEnable(jumpOut.bits.redirect.cfiUpdate.target, jumpOut.valid) 96 val s1_imm12_reg = RegNext(oldestExuOutput.bits.uop.ctrl.imm(11, 0)) 97 val s1_pd = RegNext(oldestExuOutput.bits.uop.cf.pd) 98 val s1_redirect_bits_reg = RegNext(oldestRedirect.bits) 99 val s1_redirect_valid_reg = RegNext(oldestValid) 100 val s1_redirect_onehot = RegNext(oldestOneHot) 101 102 // stage1 -> stage2 103 io.stage2Redirect.valid := s1_redirect_valid_reg && !io.flush 104 io.stage2Redirect.bits := s1_redirect_bits_reg 105 io.stage2Redirect.bits.cfiUpdate := DontCare 106 // at stage2, we read ftq to get pc 107 io.stage2FtqRead.ptr := s1_redirect_bits_reg.ftqIdx 108 109 val s1_isReplay = s1_redirect_onehot.last 110 val s1_isJump = s1_redirect_onehot.head 111 val ftqRead = Mux1H(s1_redirect_onehot, io.stage1FtqRead).entry 112 val cfiUpdate_pc = Cat( 113 ftqRead.ftqPC.head(VAddrBits - s1_redirect_bits_reg.ftqOffset.getWidth - instOffsetBits), 114 s1_redirect_bits_reg.ftqOffset, 115 0.U(instOffsetBits.W) 116 ) 117 val real_pc = GetPcByFtq( 118 ftqRead.ftqPC, s1_redirect_bits_reg.ftqOffset, 119 ftqRead.lastPacketPC.valid, 120 ftqRead.lastPacketPC.bits 121 ) 122 val brTarget = real_pc + SignExt(ImmUnion.B.toImm32(s1_imm12_reg), XLEN) 123 val snpc = real_pc + Mux(s1_pd.isRVC, 2.U, 4.U) 124 val target = Mux(s1_isReplay, 125 real_pc, // repaly from itself 126 Mux(s1_redirect_bits_reg.cfiUpdate.taken, 127 Mux(s1_isJump, s1_jumpTarget, brTarget), 128 snpc 129 ) 130 ) 131 132 // get pc from ftq 133 io.memPredFtqRead.ptr := s1_redirect_bits_reg.stFtqIdx 134 // valid only if redirect is caused by load violation 135 // store_pc is used to update store set 136 val memPredFtqRead = io.memPredFtqRead.entry 137 val store_pc = GetPcByFtq(memPredFtqRead.ftqPC, RegNext(s1_redirect_bits_reg).stFtqOffset, 138 memPredFtqRead.lastPacketPC.valid, 139 memPredFtqRead.lastPacketPC.bits 140 ) 141 142 // update load violation predictor if load violation redirect triggered 143 io.memPredUpdate.valid := RegNext(s1_isReplay && s1_redirect_valid_reg, init = false.B) 144 // update wait table 145 io.memPredUpdate.waddr := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 146 io.memPredUpdate.wdata := true.B 147 // update store set 148 io.memPredUpdate.ldpc := RegNext(XORFold(real_pc(VAddrBits-1, 1), MemPredPCWidth)) 149 // store pc is ready 1 cycle after s1_isReplay is judged 150 io.memPredUpdate.stpc := XORFold(store_pc(VAddrBits-1, 1), MemPredPCWidth) 151 152 153 val s2_br_mask = RegEnable(ftqRead.br_mask, enable = s1_redirect_valid_reg) 154 val s2_sawNotTakenBranch = RegEnable(VecInit((0 until PredictWidth).map{ i => 155 if(i == 0) false.B else Cat(ftqRead.br_mask.take(i)).orR() 156 })(s1_redirect_bits_reg.ftqOffset), enable = s1_redirect_valid_reg) 157 val s2_hist = RegEnable(ftqRead.hist, enable = s1_redirect_valid_reg) 158 val s2_target = RegEnable(target, enable = s1_redirect_valid_reg) 159 val s2_pd = RegEnable(s1_pd, enable = s1_redirect_valid_reg) 160 val s2_cfiUpdata_pc = RegEnable(cfiUpdate_pc, enable = s1_redirect_valid_reg) 161 val s2_redirect_bits_reg = RegEnable(s1_redirect_bits_reg, enable = s1_redirect_valid_reg) 162 val s2_redirect_valid_reg = RegNext(s1_redirect_valid_reg && !io.flush, init = false.B) 163 val s2_ftqRead = io.stage2FtqRead.entry 164 165 io.stage3Redirect.valid := s2_redirect_valid_reg 166 io.stage3Redirect.bits := s2_redirect_bits_reg 167 val stage3CfiUpdate = io.stage3Redirect.bits.cfiUpdate 168 stage3CfiUpdate.pc := s2_cfiUpdata_pc 169 stage3CfiUpdate.pd := s2_pd 170 stage3CfiUpdate.rasSp := s2_ftqRead.rasSp 171 stage3CfiUpdate.rasEntry := s2_ftqRead.rasTop 172 stage3CfiUpdate.predHist := s2_ftqRead.predHist 173 stage3CfiUpdate.specCnt := s2_ftqRead.specCnt 174 stage3CfiUpdate.hist := s2_hist 175 stage3CfiUpdate.predTaken := s2_redirect_bits_reg.cfiUpdate.predTaken 176 stage3CfiUpdate.sawNotTakenBranch := s2_sawNotTakenBranch 177 stage3CfiUpdate.target := s2_target 178 stage3CfiUpdate.taken := s2_redirect_bits_reg.cfiUpdate.taken 179 stage3CfiUpdate.isMisPred := s2_redirect_bits_reg.cfiUpdate.isMisPred 180} 181 182class CtrlBlock(implicit p: Parameters) extends XSModule 183 with HasCircularQueuePtrHelper with HasFtqHelper { 184 val io = IO(new Bundle { 185 val frontend = Flipped(new FrontendToBackendIO) 186 val enqIQ = Vec(exuParameters.CriticalExuCnt, DecoupledIO(new MicroOp)) 187 // from int block 188 val exuRedirect = Vec(exuParameters.AluCnt + exuParameters.JmpCnt, Flipped(ValidIO(new ExuOutput))) 189 val stIn = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuInput))) 190 val stOut = Vec(exuParameters.StuCnt, Flipped(ValidIO(new ExuOutput))) 191 val memoryViolation = Flipped(ValidIO(new Redirect)) 192 val enqLsq = Flipped(new LsqEnqIO) 193 val jumpPc = Output(UInt(VAddrBits.W)) 194 val jalr_target = Output(UInt(VAddrBits.W)) 195 val roqio = new Bundle { 196 // to int block 197 val toCSR = new RoqCSRIO 198 val exception = ValidIO(new ExceptionInfo) 199 // to mem block 200 val lsq = new RoqLsqIO 201 } 202 val csrCtrl = Input(new CustomCSRCtrlIO) 203 val perfInfo = Output(new Bundle{ 204 val ctrlInfo = new Bundle { 205 val roqFull = Input(Bool()) 206 val intdqFull = Input(Bool()) 207 val fpdqFull = Input(Bool()) 208 val lsdqFull = Input(Bool()) 209 } 210 val bpuInfo = new Bundle { 211 val bpRight = Output(UInt(XLEN.W)) 212 val bpWrong = Output(UInt(XLEN.W)) 213 } 214 }) 215 val writeback = Vec(NRIntWritePorts + NRFpWritePorts, Flipped(ValidIO(new ExuOutput))) 216 // redirect out 217 val redirect = ValidIO(new Redirect) 218 val flush = Output(Bool()) 219 val readIntRf = Vec(NRIntReadPorts, Output(UInt(PhyRegIdxWidth.W))) 220 val readFpRf = Vec(NRFpReadPorts, Output(UInt(PhyRegIdxWidth.W))) 221 val debug_int_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 222 val debug_fp_rat = Vec(32, Output(UInt(PhyRegIdxWidth.W))) 223 }) 224 225 val ftq = Module(new Ftq) 226 227 val decode = Module(new DecodeStage) 228 val rename = Module(new Rename) 229 val dispatch = Module(new Dispatch) 230 val intBusyTable = Module(new BusyTable(NRIntReadPorts, NRIntWritePorts)) 231 val fpBusyTable = Module(new BusyTable(NRFpReadPorts, NRFpWritePorts)) 232 val redirectGen = Module(new RedirectGenerator) 233 234 val roqWbSize = NRIntWritePorts + NRFpWritePorts + exuParameters.StuCnt 235 val roq = Module(new Roq(roqWbSize)) 236 237 val backendRedirect = redirectGen.io.stage2Redirect 238 val frontendRedirect = redirectGen.io.stage3Redirect 239 val flush = roq.io.flushOut.valid 240 val flushReg = RegNext(flush) 241 242 val exuRedirect = io.exuRedirect.map(x => { 243 val valid = x.valid && x.bits.redirectValid 244 val killedByOlder = x.bits.uop.roqIdx.needFlush(backendRedirect, flushReg) 245 val delayed = Wire(Valid(new ExuOutput)) 246 delayed.valid := RegNext(valid && !killedByOlder, init = false.B) 247 delayed.bits := RegEnable(x.bits, x.valid) 248 delayed 249 }) 250 val loadReplay = Wire(Valid(new Redirect)) 251 loadReplay.valid := RegNext(io.memoryViolation.valid && 252 !io.memoryViolation.bits.roqIdx.needFlush(backendRedirect, flushReg), 253 init = false.B 254 ) 255 loadReplay.bits := RegEnable(io.memoryViolation.bits, io.memoryViolation.valid) 256 VecInit(ftq.io.ftqRead.tail.dropRight(2)) <> redirectGen.io.stage1FtqRead 257 ftq.io.ftqRead.dropRight(1).last <> redirectGen.io.memPredFtqRead 258 ftq.io.cfiRead <> redirectGen.io.stage2FtqRead 259 redirectGen.io.exuMispredict <> exuRedirect 260 redirectGen.io.loadReplay <> loadReplay 261 redirectGen.io.flush := flushReg 262 263 ftq.io.enq <> io.frontend.fetchInfo 264 for(i <- 0 until CommitWidth){ 265 ftq.io.roq_commits(i).valid := roq.io.commits.valid(i) && !roq.io.commits.isWalk 266 ftq.io.roq_commits(i).bits := roq.io.commits.info(i) 267 } 268 ftq.io.redirect <> backendRedirect 269 ftq.io.flush := flushReg 270 ftq.io.flushIdx := RegNext(roq.io.flushOut.bits.ftqIdx) 271 ftq.io.flushOffset := RegNext(roq.io.flushOut.bits.ftqOffset) 272 ftq.io.frontendRedirect <> frontendRedirect 273 ftq.io.exuWriteback <> exuRedirect 274 275 ftq.io.ftqRead.last.ptr := roq.io.flushOut.bits.ftqIdx 276 val flushPC = GetPcByFtq( 277 ftq.io.ftqRead.last.entry.ftqPC, 278 RegEnable(roq.io.flushOut.bits.ftqOffset, roq.io.flushOut.valid), 279 ftq.io.ftqRead.last.entry.lastPacketPC.valid, 280 ftq.io.ftqRead.last.entry.lastPacketPC.bits 281 ) 282 283 val flushRedirect = Wire(Valid(new Redirect)) 284 flushRedirect.valid := flushReg 285 flushRedirect.bits := DontCare 286 flushRedirect.bits.ftqIdx := RegEnable(roq.io.flushOut.bits.ftqIdx, flush) 287 flushRedirect.bits.interrupt := true.B 288 flushRedirect.bits.cfiUpdate.target := Mux(io.roqio.toCSR.isXRet || roq.io.exception.valid, 289 io.roqio.toCSR.trapTarget, 290 flushPC + 4.U // flush pipe 291 ) 292 val flushRedirectReg = Wire(Valid(new Redirect)) 293 flushRedirectReg.valid := RegNext(flushRedirect.valid, init = false.B) 294 flushRedirectReg.bits := RegEnable(flushRedirect.bits, enable = flushRedirect.valid) 295 296 io.frontend.redirect_cfiUpdate := Mux(flushRedirectReg.valid, flushRedirectReg, frontendRedirect) 297 io.frontend.commit_cfiUpdate := ftq.io.commit_ftqEntry 298 io.frontend.ftqEnqPtr := ftq.io.enqPtr 299 io.frontend.ftqLeftOne := ftq.io.leftOne 300 301 decode.io.in <> io.frontend.cfVec 302 // currently, we only update wait table when isReplay 303 decode.io.memPredUpdate(0) <> RegNext(redirectGen.io.memPredUpdate) 304 decode.io.memPredUpdate(1) := DontCare 305 decode.io.memPredUpdate(1).valid := false.B 306 // decode.io.memPredUpdate <> io.toLsBlock.memPredUpdate 307 decode.io.csrCtrl := RegNext(io.csrCtrl) 308 309 310 val jumpInst = dispatch.io.enqIQCtrl(0).bits 311 val ftqOffsetReg = Reg(UInt(log2Up(PredictWidth).W)) 312 ftqOffsetReg := jumpInst.cf.ftqOffset 313 ftq.io.ftqRead(0).ptr := jumpInst.cf.ftqPtr // jump 314 io.jumpPc := GetPcByFtq( 315 ftq.io.ftqRead(0).entry.ftqPC, ftqOffsetReg, 316 ftq.io.ftqRead(0).entry.lastPacketPC.valid, 317 ftq.io.ftqRead(0).entry.lastPacketPC.bits 318 ) 319 io.jalr_target := ftq.io.ftqRead(0).entry.target 320 321 // pipeline between decode and dispatch 322 for (i <- 0 until RenameWidth) { 323 PipelineConnect(decode.io.out(i), rename.io.in(i), rename.io.in(i).ready, 324 flushReg || io.frontend.redirect_cfiUpdate.valid) 325 } 326 327 rename.io.redirect <> backendRedirect 328 rename.io.flush := flushReg 329 rename.io.roqCommits <> roq.io.commits 330 rename.io.out <> dispatch.io.fromRename 331 rename.io.renameBypass <> dispatch.io.renameBypass 332 rename.io.dispatchInfo <> dispatch.io.preDpInfo 333 rename.io.csrCtrl <> RegNext(io.csrCtrl) 334 335 dispatch.io.redirect <> backendRedirect 336 dispatch.io.flush := flushReg 337 dispatch.io.enqRoq <> roq.io.enq 338 dispatch.io.enqLsq <> io.enqLsq 339 dispatch.io.allocPregs.zipWithIndex.foreach { case (preg, i) => 340 intBusyTable.io.allocPregs(i).valid := preg.isInt 341 fpBusyTable.io.allocPregs(i).valid := preg.isFp 342 intBusyTable.io.allocPregs(i).bits := preg.preg 343 fpBusyTable.io.allocPregs(i).bits := preg.preg 344 } 345 dispatch.io.enqIQCtrl := DontCare 346 io.enqIQ <> dispatch.io.enqIQCtrl 347 dispatch.io.csrCtrl <> io.csrCtrl 348 dispatch.io.storeIssue <> io.stIn 349 dispatch.io.readIntRf <> io.readIntRf 350 dispatch.io.readFpRf <> io.readFpRf 351 352 fpBusyTable.io.flush := flushReg 353 intBusyTable.io.flush := flushReg 354 for((wb, setPhyRegRdy) <- io.writeback.take(NRIntWritePorts).zip(intBusyTable.io.wbPregs)){ 355 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.rfWen 356 setPhyRegRdy.bits := wb.bits.uop.pdest 357 } 358 for((wb, setPhyRegRdy) <- io.writeback.drop(NRIntWritePorts).zip(fpBusyTable.io.wbPregs)){ 359 setPhyRegRdy.valid := wb.valid && wb.bits.uop.ctrl.fpWen 360 setPhyRegRdy.bits := wb.bits.uop.pdest 361 } 362 intBusyTable.io.read <> dispatch.io.readIntState 363 fpBusyTable.io.read <> dispatch.io.readFpState 364 365 roq.io.redirect <> backendRedirect 366 val exeWbResults = VecInit(io.writeback ++ io.stOut) 367 for((roq_wb, wb) <- roq.io.exeWbResults.zip(exeWbResults)) { 368 roq_wb.valid := RegNext(wb.valid && !wb.bits.uop.roqIdx.needFlush(backendRedirect, flushReg)) 369 roq_wb.bits := RegNext(wb.bits) 370 } 371 372 // TODO: is 'backendRedirect' necesscary? 373 io.redirect <> backendRedirect 374 io.flush <> flushReg 375 io.debug_int_rat <> rename.io.debug_int_rat 376 io.debug_fp_rat <> rename.io.debug_fp_rat 377 378// dispatch.io.readPortIndex.intIndex <> io.toIntBlock.readPortIndex 379// dispatch.io.readPortIndex.fpIndex <> io.toFpBlock.readPortIndex 380 381 // roq to int block 382 io.roqio.toCSR <> roq.io.csr 383 io.roqio.toCSR.perfinfo.retiredInstr <> RegNext(roq.io.csr.perfinfo.retiredInstr) 384 io.roqio.exception := roq.io.exception 385 io.roqio.exception.bits.uop.cf.pc := flushPC 386 // roq to mem block 387 io.roqio.lsq <> roq.io.lsq 388 389 io.perfInfo.ctrlInfo.roqFull := RegNext(roq.io.roqFull) 390 io.perfInfo.ctrlInfo.intdqFull := RegNext(dispatch.io.ctrlInfo.intdqFull) 391 io.perfInfo.ctrlInfo.fpdqFull := RegNext(dispatch.io.ctrlInfo.fpdqFull) 392 io.perfInfo.ctrlInfo.lsdqFull := RegNext(dispatch.io.ctrlInfo.lsdqFull) 393 io.perfInfo.bpuInfo <> RegNext(ftq.io.bpuInfo) 394} 395