xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision 8a00ff566bcba2487c171ffd13c225a25e8ff441) 
1package xiangshan
2
3import chipsalliance.rocketchip.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.DCacheBundle
8import xiangshan.backend.fu.FuType
9
10/** Mem */
11class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
12  val timeCnt = UInt(XLEN.W)
13  val robIdx = UInt(log2Ceil(RobSize).W)
14  val paddr = UInt(PAddrBits.W)
15  val vaddr = UInt(VAddrBits.W)
16  // 1:first hit, 2:first miss, 3:second miss
17  val missState = UInt(3.W)
18}
19
20class InstInfoEntry(implicit p: Parameters) extends XSBundle{
21  val globalID = UInt(XLEN.W)
22  val robIdx = UInt(log2Ceil(RobSize).W)
23  val instType = FuType()
24  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
25  val ivaddr = UInt(VAddrBits.W)
26  val dvaddr = UInt(VAddrBits.W) // the l/s access address
27  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
28  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
29  val accessLatency = UInt(XLEN.W)  // RS out time --> write back time
30  val executeLatency = UInt(XLEN.W)
31  val issueLatency = UInt(XLEN.W)
32  val lsInfo = new DebugLsInfo
33  val mdpInfo = new DebugMdpInfo
34  val issueTime = UInt(XLEN.W)
35  val writebackTime = UInt(XLEN.W)
36}