xref: /XiangShan/src/main/scala/xiangshan/DbEntry.scala (revision 4daa5bf3c3f27e7fd090866d52405b21e107eb8d) 
1package xiangshan
2
3import org.chipsalliance.cde.config.Parameters
4import chisel3._
5import chisel3.util.log2Ceil
6import xiangshan.backend.ctrlblock.{DebugLsInfo, DebugMdpInfo}
7import xiangshan.cache.{DCacheBundle, HasDCacheParameters}
8import xiangshan.backend.fu.FuType
9import utility.MemReqSource
10import xiangshan.mem.prefetch.HasL1PrefetchHelper
11
12/** Mem */
13class LoadMissEntry(implicit p: Parameters) extends DCacheBundle {
14  val timeCnt = UInt(XLEN.W)
15  val robIdx = UInt(log2Ceil(RobSize).W)
16  val paddr = UInt(PAddrBits.W)
17  val vaddr = UInt(VAddrBits.W)
18  // 1:first hit, 2:first miss, 3:second miss
19  val missState = UInt(3.W)
20}
21
22class LoadAccessEntry(implicit p: Parameters) extends LoadMissEntry{
23  val pred_way_num = UInt(XLEN.W)
24  val dm_way_num = UInt(XLEN.W)
25  val real_way_num = UInt(XLEN.W)
26}
27
28class InstInfoEntry(implicit p: Parameters) extends XSBundle{
29  val globalID = UInt(XLEN.W)
30  val robIdx = UInt(log2Ceil(RobSize).W)
31  val instType = FuType()
32  val exceptType = UInt(ExceptionVec.ExceptionVecSize.W)
33  val ivaddr = UInt(VAddrBits.W)
34  val dvaddr = UInt(VAddrBits.W) // the l/s access address
35  val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid
36  val tlbLatency = UInt(XLEN.W)  // original requirements is L1toL2TlbLatency
37  val accessLatency = UInt(XLEN.W)  // RS out time --> write back time
38  val executeLatency = UInt(XLEN.W)
39  val issueLatency = UInt(XLEN.W)
40  val lsInfo = new DebugLsInfo
41  val mdpInfo = new DebugMdpInfo
42  val issueTime = UInt(XLEN.W)
43  val writebackTime = UInt(XLEN.W)
44}
45
46class LoadInfoEntry(implicit p: Parameters) extends XSBundle{
47  val pc = UInt(VAddrBits.W)
48  val vaddr = UInt(VAddrBits.W)
49  val paddr = UInt(PAddrBits.W)
50  val cacheMiss = Bool()
51  val tlbQueryLatency = UInt(64.W)
52  val exeLatency = UInt(64.W)
53}
54
55class StreamPFTraceInEntry(implicit p: Parameters) extends XSBundle with HasL1PrefetchHelper{
56  val TriggerPC = UInt(VAddrBits.W)
57  val TriggerVaddr = UInt(VAddrBits.W)
58  val PFVaddr = UInt(VAddrBits.W)
59  val PFSink = UInt(SINK_BITS.W)
60}
61
62class StreamTrainTraceEntry(implicit p: Parameters) extends XSBundle with HasDCacheParameters{
63  val Type = UInt(MemReqSource.reqSourceBits.W)
64  val OldAddr = UInt(VAddrBits.W)
65  val CurAddr = UInt(VAddrBits.W)
66  val Offset = UInt(32.W)
67  val Score = UInt(32.W)
68  val Miss = Bool()
69}
70
71class StreamPFTraceOutEntry(implicit p: Parameters) extends XSBundle with HasL1PrefetchHelper{
72  val PFVaddr = UInt(VAddrBits.W)
73  val PFSink = UInt(SINK_BITS.W)
74}