1*da3bf434SMaxpicca-Lipackage xiangshan 2*da3bf434SMaxpicca-Li 3*da3bf434SMaxpicca-Liimport chipsalliance.rocketchip.config.Parameters 4*da3bf434SMaxpicca-Liimport chisel3._ 5*da3bf434SMaxpicca-Liimport chisel3.util.log2Ceil 6*da3bf434SMaxpicca-Liimport xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo} 7*da3bf434SMaxpicca-Liimport xiangshan.cache.DCacheBundle 8*da3bf434SMaxpicca-Li 9*da3bf434SMaxpicca-Li/** Mem */ 10*da3bf434SMaxpicca-Liclass LoadMissEntry(implicit p: Parameters) extends DCacheBundle { 11*da3bf434SMaxpicca-Li val timeCnt = UInt(XLEN.W) 12*da3bf434SMaxpicca-Li val robIdx = UInt(log2Ceil(RobSize).W) 13*da3bf434SMaxpicca-Li val paddr = UInt(PAddrBits.W) 14*da3bf434SMaxpicca-Li val vaddr = UInt(VAddrBits.W) 15*da3bf434SMaxpicca-Li // 1:first hit, 2:first miss, 3:second miss 16*da3bf434SMaxpicca-Li val missState = UInt(3.W) 17*da3bf434SMaxpicca-Li} 18*da3bf434SMaxpicca-Li 19*da3bf434SMaxpicca-Liclass InstInfoEntry(implicit p: Parameters) extends XSBundle{ 20*da3bf434SMaxpicca-Li val globalID = UInt(XLEN.W) 21*da3bf434SMaxpicca-Li val robIdx = UInt(log2Ceil(RobSize).W) 22*da3bf434SMaxpicca-Li val instType = FuType() 23*da3bf434SMaxpicca-Li val exceptType = UInt(ExceptionVec.ExceptionVecSize.W) 24*da3bf434SMaxpicca-Li val ivaddr = UInt(VAddrBits.W) 25*da3bf434SMaxpicca-Li val dvaddr = UInt(VAddrBits.W) // the l/s access address 26*da3bf434SMaxpicca-Li val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid 27*da3bf434SMaxpicca-Li val tlbLatency = UInt(XLEN.W) // original requirements is L1toL2TlbLatency 28*da3bf434SMaxpicca-Li val accessLatency = UInt(XLEN.W) // RS out time --> write back time 29*da3bf434SMaxpicca-Li val executeLatency = UInt(XLEN.W) 30*da3bf434SMaxpicca-Li val issueLatency = UInt(XLEN.W) 31*da3bf434SMaxpicca-Li val lsInfo = new DebugLsInfo 32*da3bf434SMaxpicca-Li val mdpInfo = new DebugMdpInfo 33*da3bf434SMaxpicca-Li val issueTime = UInt(XLEN.W) 34*da3bf434SMaxpicca-Li val writebackTime = UInt(XLEN.W) 35*da3bf434SMaxpicca-Li}