1da3bf434SMaxpicca-Lipackage xiangshan 2da3bf434SMaxpicca-Li 3da3bf434SMaxpicca-Liimport chipsalliance.rocketchip.config.Parameters 4da3bf434SMaxpicca-Liimport chisel3._ 5da3bf434SMaxpicca-Liimport chisel3.util.log2Ceil 6da3bf434SMaxpicca-Liimport xiangshan.backend.rob.{DebugLsInfo, DebugMdpInfo} 7da3bf434SMaxpicca-Liimport xiangshan.cache.DCacheBundle 8*8a00ff56SXuan Huimport xiangshan.backend.fu.FuType 9da3bf434SMaxpicca-Li 10da3bf434SMaxpicca-Li/** Mem */ 11da3bf434SMaxpicca-Liclass LoadMissEntry(implicit p: Parameters) extends DCacheBundle { 12da3bf434SMaxpicca-Li val timeCnt = UInt(XLEN.W) 13da3bf434SMaxpicca-Li val robIdx = UInt(log2Ceil(RobSize).W) 14da3bf434SMaxpicca-Li val paddr = UInt(PAddrBits.W) 15da3bf434SMaxpicca-Li val vaddr = UInt(VAddrBits.W) 16da3bf434SMaxpicca-Li // 1:first hit, 2:first miss, 3:second miss 17da3bf434SMaxpicca-Li val missState = UInt(3.W) 18da3bf434SMaxpicca-Li} 19da3bf434SMaxpicca-Li 20da3bf434SMaxpicca-Liclass InstInfoEntry(implicit p: Parameters) extends XSBundle{ 21da3bf434SMaxpicca-Li val globalID = UInt(XLEN.W) 22da3bf434SMaxpicca-Li val robIdx = UInt(log2Ceil(RobSize).W) 23da3bf434SMaxpicca-Li val instType = FuType() 24da3bf434SMaxpicca-Li val exceptType = UInt(ExceptionVec.ExceptionVecSize.W) 25da3bf434SMaxpicca-Li val ivaddr = UInt(VAddrBits.W) 26da3bf434SMaxpicca-Li val dvaddr = UInt(VAddrBits.W) // the l/s access address 27da3bf434SMaxpicca-Li val dpaddr = UInt(VAddrBits.W) // need the physical address when the TLB is valid 28da3bf434SMaxpicca-Li val tlbLatency = UInt(XLEN.W) // original requirements is L1toL2TlbLatency 29da3bf434SMaxpicca-Li val accessLatency = UInt(XLEN.W) // RS out time --> write back time 30da3bf434SMaxpicca-Li val executeLatency = UInt(XLEN.W) 31da3bf434SMaxpicca-Li val issueLatency = UInt(XLEN.W) 32da3bf434SMaxpicca-Li val lsInfo = new DebugLsInfo 33da3bf434SMaxpicca-Li val mdpInfo = new DebugMdpInfo 34da3bf434SMaxpicca-Li val issueTime = UInt(XLEN.W) 35da3bf434SMaxpicca-Li val writebackTime = UInt(XLEN.W) 36da3bf434SMaxpicca-Li}