xref: /XiangShan/src/main/scala/utils/VerilogAXI4LiteRecord.scala (revision 720dd6218ef4045360a23b552db1137cbb6e6e59) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package utils
18
19import chisel3._
20import chisel3.util._
21import chisel3.experimental.dataview._
22import scala.collection.immutable._
23
24class VerilogAXI4LiteRecord(val addrWidth: Int, val dataWidth: Int, val idWidth: Int = 0) extends Record {
25  private val axi4LiteBundle = new AXI4LiteBundle(addrWidth, dataWidth, idWidth)
26  private def traverseAndMap(data: (String, Data)): SeqMap[String, Data] = {
27    data match {
28      case (name: String, node: Bundle) => SeqMap.from(
29        node.elements.map(x => traverseAndMap(x)).flatten.map {
30          case (nodeName, node) => (s"${name.replace("bits", "")}${nodeName}", node)
31        }
32      )
33      case (name: String, node: Data) => SeqMap(name -> node)
34    }
35  }
36  private val outputPattern = "^(aw|w|ar).*".r
37  private val elems = traverseAndMap("", axi4LiteBundle) map { case (name, node) => name match {
38    case outputPattern(_) => (name, Output(node))
39    case _: String        => (name, Input (node))
40  }} map { case (name, node) => name match {
41    case s"${_}ready" => (name, Flipped(node))
42    case _: String    => (name, node)
43  }}
44  def elements: SeqMap[String, Data] = elems
45}
46
47object VerilogAXI4LiteRecord {
48  private val elementsMap: Seq[(VerilogAXI4LiteRecord, AXI4LiteBundle) => (Data, Data)] = {
49    val names = (new VerilogAXI4LiteRecord(1, 1, 0)).elements.map(_._1)
50    val pattern = "^(aw|w|b|ar|r)(.*)".r
51    names.map { name => { (verilog: VerilogAXI4LiteRecord, chisel: AXI4LiteBundle) => {
52      val (channel: Record, signal: String) = name match {
53        case pattern(prefix, signal) =>
54          (chisel.elements(prefix).asInstanceOf[Record], signal)
55        case _: String => require(false, "unexpected prefix"); null
56      }
57      verilog.elements(name) -> channel.elements.applyOrElse(signal,
58        channel.elements("bits").asInstanceOf[Record].elements)
59    }}}.toSeq
60  }
61  implicit val axi4View: DataView[VerilogAXI4LiteRecord, AXI4LiteBundle] = DataView[VerilogAXI4LiteRecord, AXI4LiteBundle](
62    vab => new AXI4LiteBundle(vab.addrWidth, vab.dataWidth, vab.idWidth), elementsMap: _*
63  )
64  implicit val axi4View2: DataView[AXI4LiteBundle, VerilogAXI4LiteRecord] =
65    axi4View.invert(ab => new VerilogAXI4LiteRecord(ab.addrWidth, ab.dataWidth, ab.idWidth))
66}
67