xref: /XiangShan/src/main/scala/utils/AXI4Lite.scala (revision 03df898aac434d7e1caa346314a13c44961e7489) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package utils
18
19import chisel3._
20import chisel3.util._
21import freechips.rocketchip.amba.axi4.AXI4Bundle
22
23class AXI4LiteBundleA(addrWidth: Int, idWidth: Int = 0) extends Bundle {
24  val id = UInt(idWidth.W)
25  val addr = UInt(addrWidth.W)
26}
27
28class AXI4LiteBundleAR(addrWidth: Int, idWidth: Int = 0) extends AXI4LiteBundleA(addrWidth, idWidth)
29
30class AXI4LiteBundleAW(addrWidth: Int, idWidth: Int = 0) extends AXI4LiteBundleA(addrWidth, idWidth)
31
32class AXI4LiteBundleW(dataWidth: Int) extends Bundle {
33  val data = UInt(dataWidth.W)
34}
35
36class AXI4LiteBundleR(dataWidth: Int, idWidth: Int = 0) extends Bundle {
37  val id = UInt(idWidth.W)
38  val data = UInt(dataWidth.W)
39  val resp = UInt(2.W)
40}
41
42class AXI4LiteBundleB(idWidth: Int = 0) extends Bundle {
43  val id = UInt(idWidth.W)
44  val resp = UInt(2.W)
45}
46
47class AXI4LiteBundle(val addrWidth: Int, val dataWidth: Int, val idWidth: Int = 0) extends Bundle {
48  val aw = Irrevocable(new AXI4LiteBundleAW(addrWidth, idWidth))
49  val w  = Irrevocable(new AXI4LiteBundleW(dataWidth))
50  val b  = Flipped(Irrevocable(new AXI4LiteBundleB(idWidth)))
51  val ar = Irrevocable(new AXI4LiteBundleAR(addrWidth, idWidth))
52  val r  = Flipped(Irrevocable(new AXI4LiteBundleR(dataWidth, idWidth)))
53
54  private def connectExisting(left: Bundle, right: Bundle): Unit = {
55    for ((name, data) <- left.elements)
56      if (right.elements.contains(name))
57        data := right.elements(name)
58      else
59        data := (name match {
60          case "size" => log2Ceil(dataWidth/8).U
61          case "strb" => ((1L<<(dataWidth/8)) - 1).U
62          case "last" => true.B.asTypeOf(data)
63          case _: String => 0.U.asTypeOf(data)
64        })
65  }
66
67  def connectToAXI4(axi4: AXI4Bundle): Unit = {
68    axi4.aw.valid := aw.valid
69    aw.ready := axi4.aw.ready
70    connectExisting(axi4.aw.bits, aw.bits)
71
72    axi4.w.valid := w.valid
73    w.ready := axi4.w.ready
74    connectExisting(axi4.w.bits, w.bits)
75
76    axi4.ar.valid := ar.valid
77    ar.ready := axi4.ar.ready
78    connectExisting(axi4.ar.bits, ar.bits)
79
80    b.valid := axi4.b.valid
81    axi4.b.ready := b.ready
82    connectExisting(b.bits, axi4.b.bits)
83
84    r.valid := axi4.r.valid
85    axi4.r.ready := r.ready
86    connectExisting(r.bits, axi4.r.bits)
87  }
88
89  def connectFromAXI4(axi4: AXI4Bundle): Unit = {
90    aw.valid := axi4.aw.valid
91    axi4.aw.ready := aw.ready
92    connectExisting(aw.bits, axi4.aw.bits)
93
94    w.valid := axi4.w.valid
95    axi4.w.ready := w.ready
96    connectExisting(w.bits, axi4.w.bits)
97
98    ar.valid := axi4.ar.valid
99    axi4.ar.ready := ar.ready
100    connectExisting(ar.bits, axi4.ar.bits)
101
102    axi4.b.valid := b.valid
103    b.ready := axi4.b.ready
104    connectExisting(axi4.b.bits, b.bits)
105
106    axi4.r.valid := r.valid
107    r.ready := axi4.r.ready
108    connectExisting(axi4.r.bits, r.bits)
109  }
110}
111