15bd65c56STang Haojin/*************************************************************************************** 25bd65c56STang Haojin* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 35bd65c56STang Haojin* Copyright (c) 2025 Institute of Computing Technology, Chinese Academy of Sciences 45bd65c56STang Haojin* 55bd65c56STang Haojin* XiangShan is licensed under Mulan PSL v2. 65bd65c56STang Haojin* You can use this software according to the terms and conditions of the Mulan PSL v2. 75bd65c56STang Haojin* You may obtain a copy of Mulan PSL v2 at: 85bd65c56STang Haojin* http://license.coscl.org.cn/MulanPSL2 95bd65c56STang Haojin* 105bd65c56STang Haojin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 115bd65c56STang Haojin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 125bd65c56STang Haojin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 135bd65c56STang Haojin* 145bd65c56STang Haojin* See the Mulan PSL v2 for more details. 155bd65c56STang Haojin***************************************************************************************/ 165bd65c56STang Haojin 175bd65c56STang Haojinpackage top 185bd65c56STang Haojin 195bd65c56STang Haojinimport io.circe.generic.extras.Configuration 205bd65c56STang Haojinimport io.circe.generic.extras.auto._ 215bd65c56STang Haojin 225bd65c56STang Haojinimport org.chipsalliance.cde.config.Parameters 235bd65c56STang Haojinimport system.SoCParamsKey 245bd65c56STang Haojinimport xiangshan.backend.fu.{MemoryRange, PMAConfigEntry} 25*4c0658aeSTang Haojinimport xiangshan.XSTileKey 265bd65c56STang Haojinimport freechips.rocketchip.devices.debug.DebugModuleKey 2716ae9ddcSTang Haojinimport freechips.rocketchip.diplomacy.AddressSet 28*4c0658aeSTang Haojinimport freechips.rocketchip.util.AsyncQueueParams 295bd65c56STang Haojin 305bd65c56STang Haojincase class YamlConfig( 315bd65c56STang Haojin PmemRanges: Option[List[MemoryRange]], 325bd65c56STang Haojin PMAConfigs: Option[List[PMAConfigEntry]], 330964a977STang Haojin EnableCHIAsyncBridge: Option[Boolean], 345bd65c56STang Haojin L2CacheConfig: Option[L2CacheConfig], 355bd65c56STang Haojin L3CacheConfig: Option[L3CacheConfig], 3616ae9ddcSTang Haojin DebugModuleBaseAddr: Option[BigInt], 37*4c0658aeSTang Haojin WFIResume: Option[Boolean], 3816ae9ddcSTang Haojin SeperateDM: Option[Boolean], 3916ae9ddcSTang Haojin SeperateTLBus: Option[Boolean], 4016ae9ddcSTang Haojin SeperateTLBusRanges: Option[List[AddressSet]] 415bd65c56STang Haojin) 425bd65c56STang Haojin 435bd65c56STang Haojinobject YamlParser { 445bd65c56STang Haojin implicit val customParserConfig: Configuration = Configuration.default.withDefaults 455bd65c56STang Haojin def parseYaml(config: Parameters, yamlFile: String): Parameters = { 465bd65c56STang Haojin val yaml = scala.io.Source.fromFile(yamlFile).mkString 475bd65c56STang Haojin val json = io.circe.yaml.parser.parse(yaml) match { 485bd65c56STang Haojin case Left(value) => throw value 495bd65c56STang Haojin case Right(value) => value 505bd65c56STang Haojin } 515bd65c56STang Haojin val yamlConfig = json.as[YamlConfig] match { 525bd65c56STang Haojin case Left(value) => throw value 535bd65c56STang Haojin case Right(value) => value 545bd65c56STang Haojin } 555bd65c56STang Haojin var newConfig = config 565bd65c56STang Haojin yamlConfig.PmemRanges.foreach { ranges => 575bd65c56STang Haojin newConfig = newConfig.alter((site, here, up) => { 585bd65c56STang Haojin case SoCParamsKey => up(SoCParamsKey).copy(PmemRanges = ranges) 595bd65c56STang Haojin }) 605bd65c56STang Haojin } 615bd65c56STang Haojin yamlConfig.PMAConfigs.foreach { pmaConfigs => 625bd65c56STang Haojin newConfig = newConfig.alter((site, here, up) => { 635bd65c56STang Haojin case SoCParamsKey => up(SoCParamsKey).copy(PMAConfigs = pmaConfigs) 645bd65c56STang Haojin }) 655bd65c56STang Haojin } 660964a977STang Haojin yamlConfig.EnableCHIAsyncBridge.foreach { enable => 675bd65c56STang Haojin newConfig = newConfig.alter((site, here, up) => { 685bd65c56STang Haojin case SoCParamsKey => up(SoCParamsKey).copy( 690964a977STang Haojin EnableCHIAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 16, sync = 3, safe = false)) 705bd65c56STang Haojin ) 715bd65c56STang Haojin }) 725bd65c56STang Haojin } 735bd65c56STang Haojin yamlConfig.L2CacheConfig.foreach(l2 => newConfig = newConfig.alter(l2)) 745bd65c56STang Haojin yamlConfig.L3CacheConfig.foreach(l3 => newConfig = newConfig.alter(l3)) 755bd65c56STang Haojin yamlConfig.DebugModuleBaseAddr.foreach { addr => 765bd65c56STang Haojin newConfig = newConfig.alter((site, here, up) => { 775bd65c56STang Haojin case DebugModuleKey => up(DebugModuleKey).map(_.copy(baseAddress = addr)) 785bd65c56STang Haojin }) 795bd65c56STang Haojin } 80*4c0658aeSTang Haojin yamlConfig.WFIResume.foreach { enable => 81*4c0658aeSTang Haojin newConfig = newConfig.alter((site, here, up) => { 82*4c0658aeSTang Haojin case XSTileKey => up(XSTileKey).map(_.copy(wfiResume = enable)) 83*4c0658aeSTang Haojin }) 84*4c0658aeSTang Haojin } 8516ae9ddcSTang Haojin yamlConfig.SeperateDM.foreach { enable => 8616ae9ddcSTang Haojin newConfig = newConfig.alter((site, here, up) => { 8716ae9ddcSTang Haojin case SoCParamsKey => up(SoCParamsKey).copy(SeperateDM = enable) 8816ae9ddcSTang Haojin }) 8916ae9ddcSTang Haojin } 9016ae9ddcSTang Haojin yamlConfig.SeperateTLBus.foreach { enable => 9116ae9ddcSTang Haojin newConfig = newConfig.alter((site, here, up) => { 9216ae9ddcSTang Haojin case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBus = enable) 9316ae9ddcSTang Haojin }) 9416ae9ddcSTang Haojin } 9516ae9ddcSTang Haojin yamlConfig.SeperateTLBusRanges.foreach { ranges => 9616ae9ddcSTang Haojin newConfig = newConfig.alter((site, here, up) => { 9716ae9ddcSTang Haojin case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBusRanges = ranges) 9816ae9ddcSTang Haojin }) 9916ae9ddcSTang Haojin } 1005bd65c56STang Haojin newConfig 1015bd65c56STang Haojin } 1025bd65c56STang Haojin} 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