1/*************************************************************************************** 2* Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 3* Copyright (c) 2025 Institute of Computing Technology, Chinese Academy of Sciences 4* 5* XiangShan is licensed under Mulan PSL v2. 6* You can use this software according to the terms and conditions of the Mulan PSL v2. 7* You may obtain a copy of Mulan PSL v2 at: 8* http://license.coscl.org.cn/MulanPSL2 9* 10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13* 14* See the Mulan PSL v2 for more details. 15***************************************************************************************/ 16 17package top 18 19import io.circe.generic.extras.Configuration 20import io.circe.generic.extras.auto._ 21 22import aia.IMSICParams 23import org.chipsalliance.cde.config.Parameters 24import system.SoCParamsKey 25import xiangshan.backend.fu.{MemoryRange, PMAConfigEntry} 26import xiangshan.XSTileKey 27import freechips.rocketchip.devices.debug.{DebugAttachParams, ExportDebug} 28import freechips.rocketchip.devices.debug.{DMI, JTAG, CJTAG, APB} 29import freechips.rocketchip.devices.debug.{DebugModuleKey, DebugModuleParams} 30import freechips.rocketchip.diplomacy.AddressSet 31import freechips.rocketchip.tile.MaxHartIdBits 32import freechips.rocketchip.util.AsyncQueueParams 33import device.IMSICBusType 34 35case class YamlConfig( 36 Config: Option[String], 37 PmemRanges: Option[List[MemoryRange]], 38 PMAConfigs: Option[List[PMAConfigEntry]], 39 EnableCHIAsyncBridge: Option[Boolean], 40 L2CacheConfig: Option[L2CacheConfig], 41 L3CacheConfig: Option[L3CacheConfig], 42 HartIDBits: Option[Int], 43 DebugAttachProtocals: Option[List[String]], 44 DebugModuleParams: Option[DebugModuleParams], 45 WFIResume: Option[Boolean], 46 SeperateDM: Option[Boolean], 47 SeperateTLBus: Option[Boolean], 48 SeperateTLBusRanges: Option[List[AddressSet]], 49 EnableSeperateTLBusAsyncBridge: Option[Boolean], 50 IMSICBusType: Option[String], 51 IMSICParams: Option[IMSICParams], 52 CHIIssue: Option[String], 53 WFIClockGate: Option[Boolean], 54 EnablePowerDown: Option[Boolean], 55 XSTopPrefix: Option[String], 56 EnableDFX: Option[Boolean], 57 EnableSramCtl: Option[Boolean], 58 EnableCHINS: Option[Boolean], 59 CHIAddrWidth: Option[Int], 60) 61 62object YamlParser { 63 implicit val customParserConfig: Configuration = Configuration.default.withDefaults 64 def parseYaml(config: Parameters, yamlFile: String): Parameters = { 65 val yaml = scala.io.Source.fromFile(yamlFile).mkString 66 val json = io.circe.yaml.parser.parse(yaml) match { 67 case Left(value) => throw value 68 case Right(value) => value 69 } 70 val yamlConfig = json.as[YamlConfig] match { 71 case Left(value) => throw value 72 case Right(value) => value 73 } 74 var newConfig = config 75 yamlConfig.Config.foreach { config => 76 newConfig = ArgParser.getConfigByName(config) 77 } 78 yamlConfig.PmemRanges.foreach { ranges => 79 newConfig = newConfig.alter((site, here, up) => { 80 case SoCParamsKey => up(SoCParamsKey).copy(PmemRanges = ranges) 81 }) 82 } 83 yamlConfig.PMAConfigs.foreach { pmaConfigs => 84 newConfig = newConfig.alter((site, here, up) => { 85 case SoCParamsKey => up(SoCParamsKey).copy(PMAConfigs = pmaConfigs) 86 }) 87 } 88 yamlConfig.EnableCHIAsyncBridge.foreach { enable => 89 newConfig = newConfig.alter((site, here, up) => { 90 case SoCParamsKey => up(SoCParamsKey).copy( 91 EnableCHIAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 16, sync = 3, safe = false)) 92 ) 93 }) 94 } 95 yamlConfig.L2CacheConfig.foreach(l2 => newConfig = newConfig.alter(l2)) 96 yamlConfig.L3CacheConfig.foreach(l3 => newConfig = newConfig.alter(l3)) 97 yamlConfig.DebugAttachProtocals.foreach { protocols => 98 newConfig = newConfig.alter((site, here, up) => { 99 case ExportDebug => DebugAttachParams(protocols = protocols.map { 100 case "DMI" => DMI 101 case "JTAG" => JTAG 102 case "CJTAG" => CJTAG 103 case "APB" => APB 104 }.toSet) 105 }) 106 } 107 yamlConfig.HartIDBits.foreach { bits => 108 newConfig = newConfig.alter((site, here, up) => { 109 case MaxHartIdBits => bits 110 }) 111 } 112 yamlConfig.DebugModuleParams.foreach { params => 113 newConfig = newConfig.alter((site, here, up) => { 114 case DebugModuleKey => Some(params) 115 }) 116 } 117 yamlConfig.WFIResume.foreach { enable => 118 newConfig = newConfig.alter((site, here, up) => { 119 case XSTileKey => up(XSTileKey).map(_.copy(wfiResume = enable)) 120 }) 121 } 122 yamlConfig.SeperateDM.foreach { enable => 123 newConfig = newConfig.alter((site, here, up) => { 124 case SoCParamsKey => up(SoCParamsKey).copy(SeperateDM = enable) 125 }) 126 } 127 yamlConfig.SeperateTLBus.foreach { enable => 128 newConfig = newConfig.alter((site, here, up) => { 129 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBus = enable) 130 }) 131 } 132 yamlConfig.SeperateTLBusRanges.foreach { ranges => 133 newConfig = newConfig.alter((site, here, up) => { 134 case SoCParamsKey => up(SoCParamsKey).copy(SeperateTLBusRanges = ranges) 135 }) 136 } 137 yamlConfig.EnableSeperateTLBusAsyncBridge.foreach { enable => 138 newConfig = newConfig.alter((site, here, up) => { 139 case SoCParamsKey => up(SoCParamsKey).copy( 140 SeperateTLAsyncBridge = Option.when(enable)(AsyncQueueParams(depth = 1, sync = 3, safe = false)) 141 ) 142 }) 143 } 144 yamlConfig.IMSICBusType.foreach { busType => 145 newConfig = newConfig.alter((site, here, up) => { 146 case SoCParamsKey => up(SoCParamsKey).copy(IMSICBusType = device.IMSICBusType.withName(busType)) 147 }) 148 } 149 yamlConfig.IMSICParams.foreach { params => 150 newConfig = newConfig.alter((site, here, up) => { 151 case SoCParamsKey => up(SoCParamsKey).copy(IMSICParams = params) 152 }) 153 } 154 yamlConfig.CHIIssue.foreach { issue => 155 newConfig = newConfig.alter((site, here, up) => { 156 case coupledL2.tl2chi.CHIIssue => issue 157 }) 158 } 159 yamlConfig.WFIClockGate.foreach { enable => 160 newConfig = newConfig.alter((site, here, up) => { 161 case SoCParamsKey => up(SoCParamsKey).copy(WFIClockGate = enable) 162 }) 163 } 164 yamlConfig.EnablePowerDown.foreach { enable => 165 newConfig = newConfig.alter((site, here, up) => { 166 case SoCParamsKey => up(SoCParamsKey).copy(EnablePowerDown = enable) 167 }) 168 } 169 yamlConfig.XSTopPrefix.foreach { prefix => 170 newConfig = newConfig.alter((site, here, up) => { 171 case SoCParamsKey => up(SoCParamsKey).copy(XSTopPrefix = Option.when(prefix.nonEmpty)(prefix)) 172 }) 173 } 174 yamlConfig.EnableDFX.foreach { enable => 175 newConfig = newConfig.alter((site, here, up) => { 176 case XSTileKey => up(XSTileKey).map(_.copy(hasMbist = enable)) 177 }) 178 } 179 yamlConfig.EnableSramCtl.foreach { enable => 180 newConfig = newConfig.alter((site, here, up) => { 181 case XSTileKey => up(XSTileKey).map(_.copy(hasSramCtl = enable)) 182 }) 183 } 184 yamlConfig.EnableCHINS.foreach { enable => 185 newConfig = newConfig.alter((site, here, up) => { 186 case coupledL2.tl2chi.NonSecureKey => enable 187 }) 188 } 189 yamlConfig.CHIAddrWidth.foreach { width => 190 newConfig = newConfig.alter((site, here, up) => { 191 case coupledL2.tl2chi.CHIAddrWidthKey => width 192 }) 193 } 194 newConfig 195 } 196} 197