xref: /XiangShan/src/main/scala/top/XSNoCTop.scala (revision 24bb726d80e7b0ea2ad2c685838b3a749ec0178d) 
1/***************************************************************************************
2* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
3* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences
4*
5* XiangShan is licensed under Mulan PSL v2.
6* You can use this software according to the terms and conditions of the Mulan PSL v2.
7* You may obtain a copy of Mulan PSL v2 at:
8*          http://license.coscl.org.cn/MulanPSL2
9*
10* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13*
14* See the Mulan PSL v2 for more details.
15***************************************************************************************/
16
17package top
18
19import chisel3._
20import chisel3.util._
21import xiangshan._
22import utils._
23import utility._
24import system._
25import device._
26import org.chipsalliance.cde.config._
27import freechips.rocketchip.amba.axi4._
28import freechips.rocketchip.diplomacy._
29import freechips.rocketchip.interrupts._
30import freechips.rocketchip.tilelink._
31import coupledL2.tl2chi.{PortIO, CHIAsyncBridgeSink}
32import freechips.rocketchip.tile.MaxHartIdBits
33import freechips.rocketchip.util.{AsyncQueueSource, AsyncQueueParams}
34
35class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
36{
37  override lazy val desiredName: String = "XSTop"
38
39  ResourceBinding {
40    val width = ResourceInt(2)
41    val model = "freechips,rocketchip-unknown"
42    Resource(ResourceAnchors.root, "model").bind(ResourceString(model))
43    Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev"))
44    Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc"))
45    Resource(ResourceAnchors.root, "width").bind(width)
46    Resource(ResourceAnchors.soc, "width").bind(width)
47    Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1))
48    def bindManagers(xbar: TLNexusNode) = {
49      ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager =>
50        manager.resources.foreach(r => r.bind(manager.toResource))
51      }
52    }
53  }
54
55  require(enableCHI)
56
57  // xstile
58  val core_with_l2 = LazyModule(new XSTileWrap()(p.alter((site, here, up) => {
59    case XSCoreParamsKey => tiles.head
60    case PerfCounterOptionsKey => up(PerfCounterOptionsKey).copy(perfDBHartID = tiles.head.HartId)
61  })))
62
63  // imsic bus top
64  val u_imsic_bus_top = LazyModule(new imsic_bus_top(
65    useTL = soc.IMSICUseTL,
66    baseAddress = (0x3A800000, 0x3B000000)
67  ))
68
69  // interrupts
70  val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2))
71  val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1))
72  val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1))
73  val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1))
74  core_with_l2.clintIntNode := clintIntNode
75  core_with_l2.debugIntNode := debugIntNode
76  core_with_l2.plicIntNode :*= plicIntNode
77  beuIntNode := IntBuffer(2) := core_with_l2.tile.beu_int_source
78  val clint = InModuleBody(clintIntNode.makeIOs())
79  val debug = InModuleBody(debugIntNode.makeIOs())
80  val plic = InModuleBody(plicIntNode.makeIOs())
81  val beu = InModuleBody(beuIntNode.makeIOs())
82
83  // reset nodes
84  val core_rst_node = BundleBridgeSource(() => Reset())
85  core_with_l2.tile.core_reset_sink := core_rst_node
86
87  class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) {
88    FileRegisters.add("dts", dts)
89    FileRegisters.add("graphml", graphML)
90    FileRegisters.add("json", json)
91    FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader())
92
93    val clock = IO(Input(Clock()))
94    val reset = IO(Input(AsyncReset()))
95    val noc_clock = EnableCHIAsyncBridge.map(_ => IO(Input(Clock())))
96    val noc_reset = EnableCHIAsyncBridge.map(_ => IO(Input(AsyncReset())))
97    val soc_clock = IO(Input(Clock()))
98    val soc_reset = IO(Input(AsyncReset()))
99    val io = IO(new Bundle {
100      val hartId = Input(UInt(p(MaxHartIdBits).W))
101      val riscv_halt = Output(Bool())
102      val hartIsInReset = Output(Bool())
103      val riscv_rst_vec = Input(UInt(soc.PAddrBits.W))
104      val chi = new PortIO
105      val nodeID = Input(UInt(soc.NodeIDWidthList(issue).W))
106      val clintTime = Input(ValidIO(UInt(64.W)))
107    })
108    // imsic axi4lite io
109    val imsic_axi4lite = wrapper.u_imsic_bus_top.module.axi4lite.map(x => IO(chiselTypeOf(x)))
110    // imsic tl io
111    val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue)))
112    val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue)))
113
114    val reset_sync = withClockAndReset(clock, reset) { ResetGen() }
115    val noc_reset_sync = withClockAndReset(noc_clock, noc_reset) { ResetGen() }
116    val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen() }
117
118    // override LazyRawModuleImp's clock and reset
119    childClock := clock
120    childReset := reset_sync
121
122    // device clock and reset
123    wrapper.u_imsic_bus_top.module.clock := soc_clock
124    wrapper.u_imsic_bus_top.module.reset := soc_reset_sync
125
126    // imsic axi4lite io connection
127    wrapper.u_imsic_bus_top.module.axi4lite.foreach(_ <> imsic_axi4lite.get)
128
129    // imsic tl io connection
130    wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get)
131    wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get)
132
133    // input
134    dontTouch(io)
135
136    core_with_l2.module.io.hartId := io.hartId
137    core_with_l2.module.io.nodeID.get := io.nodeID
138    io.riscv_halt := core_with_l2.module.io.cpu_halt
139    io.hartIsInReset := core_with_l2.module.io.hartIsInReset
140    core_with_l2.module.io.reset_vector := io.riscv_rst_vec
141
142    EnableClintAsyncBridge match {
143      case Some(param) =>
144        val source = withClockAndReset(soc_clock, soc_reset_sync) {
145          Module(new AsyncQueueSource(UInt(64.W), param))
146        }
147        source.io.enq.valid := io.clintTime.valid
148        source.io.enq.bits := io.clintTime.bits
149        core_with_l2.module.io.clintTime.get <> source.io.async
150      case None =>
151        core_with_l2.module.io.clintTime.get <> io.clintTime
152    }
153
154    EnableCHIAsyncBridge match {
155      case Some(param) =>
156        val sink = withClockAndReset(noc_clock.get, noc_reset_sync) {
157          Module(new CHIAsyncBridgeSink(param))
158        }
159        sink.io.async <> core_with_l2.module.io.chi.get
160        io.chi <> sink.io.deq
161      case None =>
162        io.chi <> core_with_l2.module.io.chi.get
163    }
164
165    core_with_l2.module.io.msiInfo.valid := wrapper.u_imsic_bus_top.module.o_msi_info_vld
166    core_with_l2.module.io.msiInfo.bits.info := wrapper.u_imsic_bus_top.module.o_msi_info
167    // tie off core soft reset
168    core_rst_node.out.head._1 := false.B.asAsyncReset
169
170    core_with_l2.module.io.debugTopDown.l3MissMatch := false.B
171
172    withClockAndReset(clock, reset_sync) {
173      // Modules are reset one by one
174      // reset ----> SYNC --> Core
175      val resetChain = Seq(Seq(core_with_l2.module))
176      ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform)
177    }
178
179  }
180
181  lazy val module = new XSNoCTopImp(this)
182}
183