1*720dd621STang Haojin/*************************************************************************************** 2*720dd621STang Haojin* Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC) 3*720dd621STang Haojin* Copyright (c) 2024 Institute of Computing Technology, Chinese Academy of Sciences 4*720dd621STang Haojin* 5*720dd621STang Haojin* XiangShan is licensed under Mulan PSL v2. 6*720dd621STang Haojin* You can use this software according to the terms and conditions of the Mulan PSL v2. 7*720dd621STang Haojin* You may obtain a copy of Mulan PSL v2 at: 8*720dd621STang Haojin* http://license.coscl.org.cn/MulanPSL2 9*720dd621STang Haojin* 10*720dd621STang Haojin* THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND, 11*720dd621STang Haojin* EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT, 12*720dd621STang Haojin* MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE. 13*720dd621STang Haojin* 14*720dd621STang Haojin* See the Mulan PSL v2 for more details. 15*720dd621STang Haojin***************************************************************************************/ 16*720dd621STang Haojin 17*720dd621STang Haojinpackage top 18*720dd621STang Haojin 19*720dd621STang Haojinimport chisel3._ 20*720dd621STang Haojinimport chisel3.util._ 21*720dd621STang Haojinimport xiangshan._ 22*720dd621STang Haojinimport utils._ 23*720dd621STang Haojinimport utility._ 24*720dd621STang Haojinimport system._ 25*720dd621STang Haojinimport device._ 26*720dd621STang Haojinimport org.chipsalliance.cde.config._ 27*720dd621STang Haojinimport freechips.rocketchip.amba.axi4._ 28*720dd621STang Haojinimport freechips.rocketchip.diplomacy._ 29*720dd621STang Haojinimport freechips.rocketchip.interrupts._ 30*720dd621STang Haojinimport freechips.rocketchip.tilelink._ 31*720dd621STang Haojinimport coupledL2.tl2chi.PortIO 32*720dd621STang Haojinimport freechips.rocketchip.tile.MaxHartIdBits 33*720dd621STang Haojin 34*720dd621STang Haojinclass XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter 35*720dd621STang Haojin{ 36*720dd621STang Haojin override lazy val desiredName: String = "XSTop" 37*720dd621STang Haojin 38*720dd621STang Haojin ResourceBinding { 39*720dd621STang Haojin val width = ResourceInt(2) 40*720dd621STang Haojin val model = "freechips,rocketchip-unknown" 41*720dd621STang Haojin Resource(ResourceAnchors.root, "model").bind(ResourceString(model)) 42*720dd621STang Haojin Resource(ResourceAnchors.root, "compat").bind(ResourceString(model + "-dev")) 43*720dd621STang Haojin Resource(ResourceAnchors.soc, "compat").bind(ResourceString(model + "-soc")) 44*720dd621STang Haojin Resource(ResourceAnchors.root, "width").bind(width) 45*720dd621STang Haojin Resource(ResourceAnchors.soc, "width").bind(width) 46*720dd621STang Haojin Resource(ResourceAnchors.cpus, "width").bind(ResourceInt(1)) 47*720dd621STang Haojin def bindManagers(xbar: TLNexusNode) = { 48*720dd621STang Haojin ManagerUnification(xbar.edges.in.head.manager.managers).foreach{ manager => 49*720dd621STang Haojin manager.resources.foreach(r => r.bind(manager.toResource)) 50*720dd621STang Haojin } 51*720dd621STang Haojin } 52*720dd621STang Haojin } 53*720dd621STang Haojin 54*720dd621STang Haojin // xstile 55*720dd621STang Haojin val core_with_l2 = LazyModule(new XSTile()(p.alterPartial({ 56*720dd621STang Haojin case XSCoreParamsKey => tiles.head 57*720dd621STang Haojin }))) 58*720dd621STang Haojin 59*720dd621STang Haojin // imsic bus top 60*720dd621STang Haojin val u_imsic_bus_top = LazyModule(new imsic_bus_top(soc.IMSICUseTL)) 61*720dd621STang Haojin 62*720dd621STang Haojin // interrupts 63*720dd621STang Haojin val clintIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 2)) 64*720dd621STang Haojin val debugIntNode = IntSourceNode(IntSourcePortSimple(1, 1, 1)) 65*720dd621STang Haojin val plicIntNode = IntSourceNode(IntSourcePortSimple(1, 2, 1)) 66*720dd621STang Haojin val beuIntNode = IntSinkNode(IntSinkPortSimple(1, 1)) 67*720dd621STang Haojin core_with_l2.clint_int_node := IntBuffer() := clintIntNode 68*720dd621STang Haojin core_with_l2.debug_int_node := IntBuffer() := debugIntNode 69*720dd621STang Haojin core_with_l2.plic_int_node :*= IntBuffer() :*= plicIntNode 70*720dd621STang Haojin beuIntNode := IntBuffer() := core_with_l2.beu_int_source 71*720dd621STang Haojin val clint = InModuleBody(clintIntNode.makeIOs()) 72*720dd621STang Haojin val debug = InModuleBody(debugIntNode.makeIOs()) 73*720dd621STang Haojin val plic = InModuleBody(plicIntNode.makeIOs()) 74*720dd621STang Haojin val beu = InModuleBody(beuIntNode.makeIOs()) 75*720dd621STang Haojin 76*720dd621STang Haojin // reset nodes 77*720dd621STang Haojin val core_rst_node = BundleBridgeSource(() => Reset()) 78*720dd621STang Haojin core_with_l2.core_reset_sink := core_rst_node 79*720dd621STang Haojin 80*720dd621STang Haojin class XSNoCTopImp(wrapper: XSNoCTop) extends LazyRawModuleImp(wrapper) { 81*720dd621STang Haojin FileRegisters.add("dts", dts) 82*720dd621STang Haojin FileRegisters.add("graphml", graphML) 83*720dd621STang Haojin FileRegisters.add("json", json) 84*720dd621STang Haojin FileRegisters.add("plusArgs", freechips.rocketchip.util.PlusArgArtefacts.serialize_cHeader()) 85*720dd621STang Haojin 86*720dd621STang Haojin val clock = IO(Input(Clock())) 87*720dd621STang Haojin val reset = IO(Input(AsyncReset())) 88*720dd621STang Haojin val bus_clock = IO(Input(Clock())) 89*720dd621STang Haojin val bus_reset = IO(Input(AsyncReset())) 90*720dd621STang Haojin val io = IO(new Bundle { 91*720dd621STang Haojin val hartId = Input(UInt(p(MaxHartIdBits).W)) 92*720dd621STang Haojin val riscv_halt = Output(Bool()) 93*720dd621STang Haojin val riscv_rst_vec = Input(UInt(38.W)) 94*720dd621STang Haojin val chi = new PortIO 95*720dd621STang Haojin val nodeID = Input(UInt(p(SoCParamsKey).NodeIDWidth.W)) 96*720dd621STang Haojin }) 97*720dd621STang Haojin // imsic axi4lite io 98*720dd621STang Haojin val imsic_m_s = wrapper.u_imsic_bus_top.module.m_s.map(x => IO(chiselTypeOf(x))) 99*720dd621STang Haojin val imsic_s_s = wrapper.u_imsic_bus_top.module.s_s.map(x => IO(chiselTypeOf(x))) 100*720dd621STang Haojin // imsic tl io 101*720dd621STang Haojin val imsic_m_tl = wrapper.u_imsic_bus_top.tl_m.map(x => IO(chiselTypeOf(x.getWrappedValue))) 102*720dd621STang Haojin val imsic_s_tl = wrapper.u_imsic_bus_top.tl_s.map(x => IO(chiselTypeOf(x.getWrappedValue))) 103*720dd621STang Haojin 104*720dd621STang Haojin val reset_sync = withClockAndReset(clock, reset) { ResetGen() } 105*720dd621STang Haojin val bus_reset_sync = withClockAndReset(bus_clock, bus_reset) { ResetGen() } 106*720dd621STang Haojin 107*720dd621STang Haojin // override LazyRawModuleImp's clock and reset 108*720dd621STang Haojin childClock := clock 109*720dd621STang Haojin childReset := reset_sync 110*720dd621STang Haojin 111*720dd621STang Haojin // bus clock and reset 112*720dd621STang Haojin wrapper.u_imsic_bus_top.module.clock := bus_clock 113*720dd621STang Haojin wrapper.u_imsic_bus_top.module.reset := bus_reset_sync 114*720dd621STang Haojin 115*720dd621STang Haojin // imsic axi4lite io connection 116*720dd621STang Haojin wrapper.u_imsic_bus_top.module.m_s.foreach(_ <> imsic_m_s.get) 117*720dd621STang Haojin wrapper.u_imsic_bus_top.module.s_s.foreach(_ <> imsic_s_s.get) 118*720dd621STang Haojin 119*720dd621STang Haojin // imsic tl io connection 120*720dd621STang Haojin wrapper.u_imsic_bus_top.tl_m.foreach(_ <> imsic_m_tl.get) 121*720dd621STang Haojin wrapper.u_imsic_bus_top.tl_s.foreach(_ <> imsic_s_tl.get) 122*720dd621STang Haojin 123*720dd621STang Haojin // input 124*720dd621STang Haojin dontTouch(io) 125*720dd621STang Haojin 126*720dd621STang Haojin core_with_l2.module.io.hartId := io.hartId 127*720dd621STang Haojin core_with_l2.module.io.nodeID.get := io.nodeID 128*720dd621STang Haojin core_with_l2.module.io.chi.get <> io.chi 129*720dd621STang Haojin io.riscv_halt := core_with_l2.module.io.cpu_halt 130*720dd621STang Haojin core_with_l2.module.io.reset_vector := io.riscv_rst_vec 131*720dd621STang Haojin // tie off core soft reset 132*720dd621STang Haojin core_rst_node.out.head._1 := false.B.asAsyncReset 133*720dd621STang Haojin 134*720dd621STang Haojin core_with_l2.module.io.debugTopDown.l3MissMatch := false.B 135*720dd621STang Haojin 136*720dd621STang Haojin withClockAndReset(clock, reset_sync) { 137*720dd621STang Haojin // Modules are reset one by one 138*720dd621STang Haojin // reset ----> SYNC --> Core 139*720dd621STang Haojin val resetChain = Seq(Seq(core_with_l2.module)) 140*720dd621STang Haojin ResetGen(resetChain, reset_sync, !debugOpts.FPGAPlatform) 141*720dd621STang Haojin } 142*720dd621STang Haojin 143*720dd621STang Haojin } 144*720dd621STang Haojin 145*720dd621STang Haojin lazy val module = new XSNoCTopImp(this) 146*720dd621STang Haojin} 147