1// See LICENSE.SiFive for license details. 2 3package device 4 5import chisel3._ 6import chisel3.util._ 7import chisel3.util.experimental.loadMemoryFromFile 8 9import bus.axi4._ 10import utils._ 11 12class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, 13 memByte: Int, beatBytes: Int = 4, dataFile: String = "") extends AXI4SlaveModule(_type) { 14 val mem = Mem(memByte / beatBytes, Vec(beatBytes, UInt(8.W))) 15 if (dataFile != "") loadMemoryFromFile(mem, dataFile) 16 17 def index(addr: UInt) = addr >> log2Ceil(beatBytes) 18 19 val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) } 20 when (in.w.fire()) { 21 mem.write(index(waddr) + writeBeatCnt, wdata, in.w.bits.strb.toBools) 22 } 23 in.b.valid := BoolStopWatch(in.w.fire() && wLast, in.b.fire(), startHighPriority = true) 24 25 val ren = in.ar.fire() || (in.r.fire() && !rLast) 26 in.r.bits.data := RegEnable(Cat(mem.read(index(raddr) + readBeatCnt).reverse), ren) 27 in.r.valid := BoolStopWatch(ren && (in.ar.fire() || r_busy), in.r.fire(), startHighPriority = true) 28} 29