1// See LICENSE.SiFive for license details. 2 3package device 4 5import chisel3._ 6import chisel3.util._ 7import chisel3.util.experimental.loadMemoryFromFile 8 9import bus.axi4._ 10import utils._ 11 12class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4, 13 memByte: Int, beatBytes: Int = 4, dataFile: String = "") extends AXI4SlaveModule(_type) { 14 val mem = Mem(memByte / beatBytes, Vec(beatBytes, UInt(8.W))) 15 if (dataFile != "") loadMemoryFromFile(mem, dataFile) 16 17 val offsetBits = log2Up(memByte) 18 val offsetMask = (1 << offsetBits) - 1 19 def index(addr: UInt) = (addr & offsetMask.U) >> log2Ceil(beatBytes) 20 def inRange(idx: UInt) = idx < (memByte / 4).U 21 22 val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) } 23 val wIdx = index(waddr) + writeBeatCnt 24 when (in.w.fire() && inRange(wIdx)) { 25 mem.write(wIdx, wdata, in.w.bits.strb.toBools) 26 } 27 28 in.r.bits.data := RegEnable(Cat(mem.read(index(raddr) + readBeatCnt).reverse), ren) 29} 30