1package device 2 3import chisel3._ 4import chisel3.util._ 5 6import bus.axi4._ 7import utils._ 8 9class AXI4Flash extends AXI4SlaveModule(new AXI4Lite) { 10 val jmpToDramInstr1 = "h0010029b".U // addiw t0,zero,1 11 val jmpToDramInstr2 = "h01f29293".U // slli t0,t0,0x1f 12 val jmpToDramInstr3 = "h00028067".U // jr t0 13 14 val mapping = Map( 15 RegMap(0x0, jmpToDramInstr1, RegMap.Unwritable), 16 RegMap(0x4, jmpToDramInstr2, RegMap.Unwritable), 17 RegMap(0x8, jmpToDramInstr3, RegMap.Unwritable) 18 ) 19 def getOffset(addr: UInt) = addr(12,0) 20 21 val rdata = Wire(UInt()) 22 RegMap.generate(mapping, getOffset(raddr), rdata, 23 getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb)) 24 25 in.r.bits.data := RegEnable(RegNext(rdata), ren) 26} 27