xref: /XiangShan/src/main/scala/device/AXI4Flash.scala (revision bfa9f4f22671af26138b635eae78350b4a9db25c)

package device

import chisel3._
import chisel3.util._

import bus.axi4._
import utils._

class AXI4Flash extends AXI4SlaveModule(new AXI4Lite) {
  val jmpToDramInstr1 = "h0010029b".U  // addiw t0,zero,1
  val jmpToDramInstr2 = "h01f29293".U  // slli  t0,t0,0x1f
  val jmpToDramInstr3 = "h00028067".U  // jr t0

  val mapping = Map(
    RegMap(0x0, jmpToDramInstr1, RegMap.Unwritable),
    RegMap(0x4, jmpToDramInstr2, RegMap.Unwritable),
    RegMap(0x8, jmpToDramInstr3, RegMap.Unwritable)
  )
  def getOffset(addr: UInt) = addr(12,0)

  val rdata = Wire(UInt(64.W))
  RegMap.generate(mapping, getOffset(raddr), rdata,
    getOffset(waddr), in.w.fire(), in.w.bits.data, MaskExpand(in.w.bits.strb))

  in.r.bits.data := RegEnable(RegNext(Fill(2, rdata(31,0))), ren)
}