xref: /XiangShan/Makefile (revision c157cf71dbae342b87f99a960fd2b10e5b5e3b7c) 
1#***************************************************************************************
2# Copyright (c) 2020-2021 Institute of Computing Technology, Chinese Academy of Sciences
3# Copyright (c) 2020-2021 Peng Cheng Laboratory
4#
5# XiangShan is licensed under Mulan PSL v2.
6# You can use this software according to the terms and conditions of the Mulan PSL v2.
7# You may obtain a copy of Mulan PSL v2 at:
8#          http://license.coscl.org.cn/MulanPSL2
9#
10# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
11# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
12# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
13#
14# See the Mulan PSL v2 for more details.
15#***************************************************************************************
16
17BUILD_DIR = ./build
18
19TOP = XSTop
20SIM_TOP = SimTop
21
22FPGATOP = top.TopMain
23SIMTOP  = top.SimTop
24
25TOP_V = $(BUILD_DIR)/$(TOP).v
26SIM_TOP_V = $(BUILD_DIR)/$(SIM_TOP).v
27
28SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
29TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
30
31MEM_GEN = ./scripts/vlsi_mem_gen
32MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
33SPLIT_VERILOG = ./scripts/split_verilog.sh
34
35IMAGE  ?= temp
36CONFIG ?= DefaultConfig
37NUM_CORES ?= 1
38MFC ?= 0
39
40# firtool check and download
41FIRTOOL_VERSION = 1.57.1
42FIRTOOL_URL = https://github.com/llvm/circt/releases/download/firtool-$(FIRTOOL_VERSION)/firrtl-bin-linux-x64.tar.gz
43FIRTOOL_PATH = $(shell which firtool 2>/dev/null)
44CACHE_FIRTOOL_PATH = $(HOME)/.cache/xiangshan/firtool-$(FIRTOOL_VERSION)/bin/firtool
45ifeq ($(MFC),1)
46ifeq ($(FIRTOOL_PATH),)
47ifeq ($(wildcard $(CACHE_FIRTOOL_PATH)),)
48$(info [INFO] Firtool not found in your PATH.)
49$(info [INFO] Downloading from $(FIRTOOL_URL))
50$(shell mkdir -p $(HOME)/.cache/xiangshan && curl -L $(FIRTOOL_URL) | tar -xzC $(HOME)/.cache/xiangshan)
51endif
52FIRTOOL_ARGS = --firtool-binary-path $(CACHE_FIRTOOL_PATH)
53endif
54endif
55
56# common chisel args
57ifeq ($(MFC),1)
58CHISEL_VERSION = chisel
59FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).v.conf"
60SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).v.conf"
61MFC_ARGS = --dump-fir $(FIRTOOL_ARGS) \
62           --firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing"
63RELEASE_ARGS += $(MFC_ARGS)
64DEBUG_ARGS += $(MFC_ARGS)
65else
66CHISEL_VERSION = chisel3
67FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
68SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
69endif
70
71# co-simulation with DRAMsim3
72ifeq ($(WITH_DRAMSIM3),1)
73ifndef DRAMSIM3_HOME
74$(error DRAMSIM3_HOME is not set)
75endif
76override SIM_ARGS += --with-dramsim3
77endif
78
79# run emu with chisel-db
80ifeq ($(WITH_CHISELDB),1)
81override SIM_ARGS += --with-chiseldb
82endif
83
84# run emu with chisel-db
85ifeq ($(WITH_ROLLINGDB),1)
86override SIM_ARGS += --with-rollingdb
87endif
88
89# dynamic switch CONSTANTIN
90ifeq ($(WITH_CONSTANTIN),0)
91$(info disable WITH_CONSTANTIN)
92else
93override SIM_ARGS += --with-constantin
94endif
95
96# emu for the release version
97ifneq ($(MFC),1)
98RELEASE_ARGS += --disable-all --remove-assert
99endif
100RELEASE_ARGS += --fpga-platform
101DEBUG_ARGS   += --enable-difftest
102ifeq ($(RELEASE),1)
103override SIM_ARGS += $(RELEASE_ARGS)
104else
105override SIM_ARGS += $(DEBUG_ARGS)
106endif
107
108TIMELOG = $(BUILD_DIR)/time.log
109TIME_CMD = time -a -o $(TIMELOG)
110
111SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
112
113.DEFAULT_GOAL = verilog
114
115help:
116	mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP) --help
117
118$(TOP_V): $(SCALA_FILE)
119	mkdir -p $(@D)
120	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].runMain $(FPGATOP)   \
121		-td $(@D) --config $(CONFIG) $(FPGA_MEM_ARGS)                    \
122		--num-cores $(NUM_CORES) $(RELEASE_ARGS)
123ifeq ($(MFC),1)
124	$(SPLIT_VERILOG) $(BUILD_DIR) $(TOP).v
125	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(TOP_V).conf" "$(BUILD_DIR)"
126endif
127	$(SED_CMD) $@
128	@git log -n 1 >> .__head__
129	@git diff >> .__diff__
130	@sed -i 's/^/\/\// ' .__head__
131	@sed -i 's/^/\/\//' .__diff__
132	@cat .__head__ .__diff__ $@ > .__out__
133	@mv .__out__ $@
134	@rm .__head__ .__diff__
135
136verilog: $(TOP_V)
137
138$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
139	mkdir -p $(@D)
140	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
141	@date -R | tee -a $(TIMELOG)
142	$(TIME_CMD) mill -i xiangshan[$(CHISEL_VERSION)].test.runMain $(SIMTOP)    \
143		-td $(@D) --config $(CONFIG) $(SIM_MEM_ARGS)                          \
144		--num-cores $(NUM_CORES) $(SIM_ARGS)
145ifeq ($(MFC),1)
146	$(SPLIT_VERILOG) $(BUILD_DIR) $(SIM_TOP).v
147	$(MEM_GEN_SEP) "$(MEM_GEN)" "$(SIM_TOP_V).conf" "$(BUILD_DIR)"
148endif
149	$(SED_CMD) $@
150	@git log -n 1 >> .__head__
151	@git diff >> .__diff__
152	@sed -i 's/^/\/\// ' .__head__
153	@sed -i 's/^/\/\//' .__diff__
154	@cat .__head__ .__diff__ $@ > .__out__
155	@mv .__out__ $@
156	@rm .__head__ .__diff__
157	sed -i -e 's/$$fatal/xs_assert(`__LINE__)/g' $(SIM_TOP_V)
158ifeq ($(MFC),1)
159	sed -i -e 's/__PERCENTAGE_M__/%m/g' $(SIM_TOP_V)
160	sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(SIM_TOP_V)
161endif
162
163sim-verilog: $(SIM_TOP_V)
164
165clean:
166	$(MAKE) -C ./difftest clean
167	rm -rf $(BUILD_DIR)
168
169init:
170	git submodule update --init
171	cd rocket-chip && git submodule update --init cde hardfloat
172
173bump:
174	git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
175
176bsp:
177	mill -i mill.bsp.BSP/install
178
179idea:
180	mill -i mill.scalalib.GenIdea/idea
181
182# verilator simulation
183emu: sim-verilog
184	$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
185
186emu-run: emu
187	$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
188
189# vcs simulation
190simv:
191	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
192
193include Makefile.test
194
195.PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
196