1# only generate a small module: example 2verilog-decode: 3 mill -i XiangShan.test.runMain xiangshan.DecodeMain -td build --output-file DecodeUnit.v 4 5# chiseltest 6# autorun all the chiselTest case 7test: 8 mill -i XiangShan.test.test 9 10# only run DecodeUnitTest 11test-DecodeUnit: 12 mill -i XiangShan.test.testOnly xiangshan.DecodeUnitTest 13