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/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dmv-xor.txt1 * Marvell XOR engines
4 - compatible: Should be one of the following:
5 - "marvell,orion-xor"
6 - "marvell,armada-380-xor"
7 - "marvell,armada-3700-xor".
8 - reg: Should contain registers location and length (two sets)
11 - clocks: pointer to the reference clock
13 The DT node must also contains sub-nodes for each XOR channel that the
14 XOR engine has. Those sub-nodes have the following required
16 - interrupts: interrupt of the XOR channel
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/linux-6.14.4/include/uapi/drm/
Dxe_drm.h1 /* SPDX-License-Identifier: MIT */
17 * subject to backwards-compatibility constraints.
28 * The diagram below represents a high-level simplification of a discrete
56 * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
72 * - &DRM_IOCTL_XE_DEVICE_QUERY
73 * - &DRM_IOCTL_XE_GEM_CREATE
74 * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
75 * - &DRM_IOCTL_XE_VM_CREATE
76 * - &DRM_IOCTL_XE_VM_DESTROY
77 * - &DRM_IOCTL_XE_VM_BIND
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Di915_drm.h9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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Dhabanalabs_accel.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
3 * Copyright 2016-2023 HabanaLabs, Ltd.
14 * Defines that are asic-specific but constitutes as ABI between kernel driver
195 * stream id is a running number from 0 up to (N-1), where N is the number
656 * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
683 * enum hl_device_status - Device status information.
715 * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
717 * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
718 * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
719 * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
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/linux-6.14.4/Documentation/userspace-api/media/v4l/
Ddev-subdev.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
6 Sub-device Interface
13 components as software blocks called sub-devices.
15 V4L2 sub-devices are usually kernel-only objects. If the V4L2 driver
17 media entities. Applications will be able to enumerate the sub-devices
21 In addition to make sub-devices discoverable, drivers can also choose to
23 sub-device driver and the V4L2 device driver support this, sub-devices
26 - query, read and write sub-devices controls
28 - subscribe and unsubscribe to events and retrieve them
30 - negotiate image formats on individual pads
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/linux-6.14.4/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra194-cbb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sumit Gupta <[email protected]>
15 multiple hierarchical sub-NOCs (Network-on-Chip) and connects various
20 "AON-NOC, SCE-NOC, RCE-NOC, BPMP-NOC, CV-NOC" and "CBB Central NOC"
28 - For CCPLEX (CPU Complex) initiator, the driver sets ERD bit. So, the
31 - For other initiators, the ERD is disabled. So, the access issuing
34 include all engines using Cortex-R5 (which is ARMv7 CPU cluster) and
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/linux-6.14.4/drivers/gpu/drm/sun4i/
Dsun8i_mixer.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 #define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
111 /* format 12 is semi-planar YUV411 UVUV */
112 /* format 13 is semi-planar YUV411 VUVU */
119 /* format 20 is packed YVU444 10-bit */
120 /* format 21 is packed YUV444 10-bit */
123 * Sub-engines listed bellow are unused for now. The EN registers are here only
124 * to be used to disable these sub-engines.
155 * struct sun8i_mixer_cfg - mixer HW configuration
217 return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE; in sun8i_blender_base()
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/linux-6.14.4/drivers/dma/idxd/
Dinit.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
25 MODULE_DESCRIPTION("Intel Data Streaming Accelerator and In-Memory Analytics Accelerator common dri…
51 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
62 .user_submission_safe = false, /* See INTEL-SA-01084 security advisory */
72 /* DSA on GNR-D platforms */
89 struct pci_dev *pdev = idxd->pdev; in idxd_setup_interrupts()
90 struct device *dev = &pdev->dev; in idxd_setup_interrupts()
97 dev_err(dev, "Not MSI-X interrupt capable.\n"); in idxd_setup_interrupts()
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Dregisters.h1 /* SPDX-License-Identifier: GPL-2.0 */
359 u64 engines; member
365 /* bytes 0-3 */
369 /* bytes 4-7 */
373 /* bytes 8-11 */
384 /* bytes 12-15 */
389 /* bytes 16-19 */
394 /* bytes 20-23 */
399 /* bytes 24-27 */
406 /* bytes 28-31 */
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/linux-6.14.4/tools/include/uapi/drm/
Di915_drm.h9 * distribute, sub license, and/or sell copies of the Software, and to
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
37 * subject to backwards-compatibility constraints.
43 * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
46 * track of these events, and if a specific cache-line seems to have a
48 * intel-gpu-tools. The value supplied with the event is always 1.
50 * I915_ERROR_UEVENT - Generated upon error detection, currently only via
57 * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
66 * struct i915_user_extension - Base class for defining a chain of extensions
82 * .. code-block:: C
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/linux-6.14.4/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
133 * | DATA IN | 16 * x (max ->max_req_size)
134 * |-----------| 0x80 (inplace operation)
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/linux-6.14.4/drivers/gpu/drm/xe/
Dxe_rtp.h1 /* SPDX-License-Identifier: MIT */
29 * Shouldn't be used directly - see XE_RTP_RULES()
51 * XE_RTP_RULE_PLATFORM - Create rule matching platform
60 * XE_RTP_RULE_SUBPLATFORM - Create rule matching platform and sub-platform
62 * @sub_: sub-platform to match
70 * XE_RTP_RULE_GRAPHICS_STEP - Create rule matching graphics stepping
83 * XE_RTP_RULE_MEDIA_STEP - Create rule matching media stepping
96 * XE_RTP_RULE_ENGINE_CLASS - Create rule matching an engine class
105 * XE_RTP_RULE_FUNC - Create rule using callback function for match
119 * XE_RTP_RULE_GRAPHICS_VERSION - Create rule matching graphics version
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/linux-6.14.4/drivers/gpu/drm/i915/gt/uc/
Dguc_capture_fwif.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2021-2022 Intel Corporation
18 * Book-keeping structure used to track read and write pointers
19 * as we extract error capture data from the GuC-log-buffer's
20 * error-capture region as a stream of dwords.
30 * struct __guc_capture_parsed_output - extracted error capture node
32 * A single unit of extracted error-capture output data grouped together
33 * at an engine-instance level. We keep these nodes in a linked list.
38 * A single set of 3 capture lists: a global-list
39 * an engine-class-list and an engine-instance list.
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Dintel_guc.h1 /* SPDX-License-Identifier: MIT */
3 * Copyright © 2014-2019 Intel Corporation
10 #include <linux/iosys-map.h>
28 * struct intel_guc - Top level structure of GuC.
36 /** @log: sub-structure containing GuC log related data and objects */
40 /** @slpc: sub-structure containing SLPC related data and objects */
42 /** @capture: the error-state-capture module's data and objects */
94 /** @interrupts: pointers to GuC interrupt-managing functions. */
103 * @submission_state: sub-structure for submission state protected by
109 * submission_state, ce->guc_id.id, and ce->guc_id.ref
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/linux-6.14.4/Documentation/devicetree/bindings/net/
Dfsl,fman.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <[email protected]>
13 Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
19 - fsl,fman
26 cell-index:
31 The cell-index value may be used by the SoC, to identify the
33 there's a description of the cell-index use in each SoC:
35 - P1023:
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/linux-6.14.4/drivers/gpu/drm/i915/gem/selftests/
Di915_gem_context.c2 * SPDX-License-Identifier: MIT
42 int err = -ENODEV; in live_nop_switch()
52 if (!DRIVER_CAPS(i915)->has_logical_contexts) in live_nop_switch()
61 err = -ENOMEM; in live_nop_switch()
88 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch()
96 intel_gt_set_wedged(engine->gt); in live_nop_switch()
98 err = -EIO; in live_nop_switch()
106 nctx, engine->name, ktime_to_ns(times[1] - times[0])); in live_nop_switch()
108 err = igt_live_test_begin(&t, i915, __func__, engine->name); in live_nop_switch()
127 i915_request_await_dma_fence(this, &rq->fence); in live_nop_switch()
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/linux-6.14.4/drivers/gpu/drm/i915/gt/
Dintel_context_types.h1 /* SPDX-License-Identifier: MIT */
71 struct intel_context *(*create_parallel)(struct intel_engine_cs **engines,
95 __intel_context_inflight(READ_ONCE((ce)->inflight))
97 __intel_context_inflight_count(READ_ONCE((ce)->inflight))
166 unsigned int active_count; /* protected by timeline->mutex */
169 struct mutex pin_mutex; /* guards pinning and associated on-gpuing */
184 * This is only used if this is a perma-pinned kernel context and
229 * with the GuC, protected by guc->submission_state.lock
235 * guc->submission_state.lock
239 * @link: in guc->guc_id_list when the guc_id has no refs but is
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/linux-6.14.4/drivers/media/platform/ti/omap3isp/
Dispstat.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - Statistics core
15 #include <linux/dma-mapping.h>
22 #define ISP_STAT_USES_DMAENGINE(stat) ((stat)->dma_ch != NULL)
56 #define IS_H3A_AF(stat) ((stat) == &(stat)->isp->isp_af)
57 #define IS_H3A_AEWB(stat) ((stat) == &(stat)->isp->isp_aewb)
68 dma_sync(stat->isp->dev, buf->dma_addr, 0, MAGIC_SIZE, dir); in __isp_stat_buf_sync_magic()
69 dma_sync(stat->isp->dev, buf->dma_addr + (buf_size & PAGE_MASK), in __isp_stat_buf_sync_magic()
101 buf->buf_size + AF_EXTRA_DATA : buf->buf_size; in isp_stat_buf_check_magic()
104 int ret = -EINVAL; in isp_stat_buf_check_magic()
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/linux-6.14.4/Documentation/admin-guide/media/
Dipu3.rst1 .. SPDX-License-Identifier: GPL-2.0
24 ImgU). The CIO2 driver is available as drivers/media/pci/intel/ipu3/ipu3-cio2*
36 Both of the drivers implement V4L2, Media Controller and V4L2 sub-device
38 MIPI CSI-2 interfaces through V4L2 sub-device sensor drivers.
44 interface to the user space. There is a video node for each CSI-2 receiver,
47 The CIO2 contains four independent capture channel, each with its own MIPI CSI-2
48 receiver and DMA engine. Each channel is modelled as a V4L2 sub-device exposed
49 to userspace as a V4L2 sub-device node and has two pads:
53 .. flat-table::
54 :header-rows: 1
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/linux-6.14.4/drivers/net/wireless/ath/ath10k/
Dhw.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
131 #define ATH10K_FW_API2_FILE "firmware-2.bin"
132 #define ATH10K_FW_API3_FILE "firmware-3.bin"
135 #define ATH10K_FW_API4_FILE "firmware-4.bin"
138 #define ATH10K_FW_API5_FILE "firmware-5.bin"
140 /* the firmware-6.bin blob */
141 #define ATH10K_FW_API6_FILE "firmware-6.bin"
144 #define ATH10K_FW_UTF_API2_FILE "utf-2.bin"
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/linux-6.14.4/drivers/soc/qcom/
Dqcom-geni-se.c1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
10 #include <linux/dma-mapping.h>
17 #include <linux/soc/qcom/geni-se.h>
31 * GENI based QUP is a highly-flexible and programmable module for supporting
34 * serial engines. The actual configuration is determined by the target
37 * of a DMA Engine and GENI sub modules which enable serial engines to
41 * +-----------------------------------------+
43 * | +----------------------------+ |
44 * --QUP & SE Clocks--> | Serial Engine N | +-IO------>
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/linux-6.14.4/drivers/ata/
Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
55 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
59 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
61 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
65 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
67 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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/linux-6.14.4/drivers/accel/habanalabs/common/
Dhabanalabs.h1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2016-2023 HabanaLabs, Ltd.
19 #include <linux/dma-direction.h>
28 #include <linux/io-64-nonatomic-lo-hi.h>
30 #include <linux/dma-buf.h>
45 * bits[63:59] - Encode mmap type
46 * bits[45:0] - mmap offset value
51 #define HL_MMAP_TYPE_SHIFT (59 - PAGE_SHIFT)
110 * enum hl_mmu_page_table_location - mmu page table location
111 * @MMU_DR_PGT: page-table is located on device DRAM.
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/linux-6.14.4/drivers/base/
Dcomponent.c1 // SPDX-License-Identifier: GPL-2.0
16 * The component helper allows drivers to collect a pile of sub-devices,
20 * subsystem-specific way to find a device is not available: The component
24 * the SoC on various components (scanout engines, blending blocks, transcoders
85 struct aggregate_device *m = s->private; in component_devices_show()
86 struct component_match *match = m->match; in component_devices_show()
90 seq_printf(s, "%-40s %20s\n", "aggregate_device name", "status"); in component_devices_show()
91 seq_puts(s, "-------------------------------------------------------------\n"); in component_devices_show()
92 seq_printf(s, "%-40s %20s\n\n", in component_devices_show()
93 dev_name(m->parent), m->bound ? "bound" : "not bound"); in component_devices_show()
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/linux-6.14.4/include/linux/mtd/
Drawnand.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2000-2010 David Woodhouse <[email protected]>
75 #define NAND_CMD_NONE -1
84 #define NAND_DATA_IFACE_CHECK_ONLY -1
98 * ecc.correct() returns -EBADMSG.
124 * Chip requires ready check on read (for auto-incremented sequential read).
142 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
174 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
175 * on the default ->cmdfunc() implementation, you may want to let the core
208 * Some controllers with pipelined ECC engines override the BBM marker with
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