Home
last modified time | relevance | path

Searched +full:edma +full:- +full:err (Results 1 – 25 of 39) sorted by relevance

12

/linux-6.14.4/drivers/dma/
Dmcf-edma-main.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
10 #include <linux/platform_data/dma-mcf-edma.h>
12 #include "fsl-edma-common.h"
20 struct edma_regs *regs = &mcf_edma->regs; in mcf_edma_tx_handler()
24 intmap = ioread32(regs->inth); in mcf_edma_tx_handler()
26 intmap |= ioread32(regs->intl); in mcf_edma_tx_handler()
30 for (ch = 0; ch < mcf_edma->n_chans; ch++) { in mcf_edma_tx_handler()
32 iowrite8(EDMA_MASK_CH(ch), regs->cint); in mcf_edma_tx_handler()
33 fsl_edma_tx_chan_handler(&mcf_edma->chans[ch]); in mcf_edma_tx_handler()
[all …]
Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
8 * Driver for the Freescale eDMA engine with flexible channel multiplexing
9 * capability for DMA request sources. The eDMA block can be found on some
13 #include <dt-bindings/dma/fsl-edma.h>
20 #include <linux/dma-mapping.h>
25 #include "fsl-edma-common.h"
31 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
38 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
[all …]
Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/dma/
Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <[email protected]>
21 - enum:
22 - fsl,vf610-edma
[all …]
/linux-6.14.4/drivers/dma/dw-edma/
Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
[all …]
Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
13 #include <linux/err.h>
16 #include <linux/dma/edma.h>
17 #include <linux/dma-mapping.h>
19 #include "dw-edma-core.h"
20 #include "dw-edma-v0-core.h"
21 #include "dw-hdma-v0-core.h"
23 #include "../virt-dma.h"
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pci/
Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
[all …]
Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <[email protected]>
22 - description: AHB clock for PCIe master
23 - description: AHB clock for PCIe slave
24 - description: AHB clock for PCIe dbi
[all …]
Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <[email protected]>
11 - Gustavo Pimentel <[email protected]>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
[all …]
/linux-6.14.4/drivers/ata/
Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-[email protected] on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
[all …]
/linux-6.14.4/arch/m68k/coldfire/
Ddevice.c2 * device.c -- common ColdFire SoC device support
23 #include <linux/platform_data/edma.h>
24 #include <linux/platform_data/dma-mcf-edma.h>
25 #include <linux/platform_data/mmc-esdhc-mcf.h>
99 #define FEC_NAME "enet-fec"
117 .end = MCFFEC_BASE0 + MCFFEC_SIZE0 - 1,
154 .end = MCFFEC_BASE1 + MCFFEC_SIZE1 - 1,
195 .end = MCFQSPI_BASE + MCFQSPI_SIZE - 1,
346 .end = MCFI2C_BASE0 + MCFI2C_SIZE0 - 1,
357 .name = "imx1-i2c",
[all …]
/linux-6.14.4/drivers/dma/ti/
Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
25 #include <linux/platform_data/edma.h>
28 #include "../virt-dma.h"
42 /* Offsets for EDMA CC global channel registers and their shadows */
66 /* Offsets for EDMA CC global registers */
70 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
100 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
[all …]
Ddma-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/err.h>
25 .compatible = "ti,dra7-dma-crossbar",
29 .compatible = "ti,am335x-edma-crossbar",
44 u32 dma_requests; /* number of DMA requests on eDMA */
60 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
71 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
73 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
80 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/vf/
Dvfxxx.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 #include "vf610-pinfunc.h"
6 #include <dt-bindings/clock/vf610-clock.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/gpio/gpio.h>
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <24000000>;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/iommu/
Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
[all …]
/linux-6.14.4/drivers/net/wireless/ath/ath9k/
Drecv.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include <linux/dma-mapping.h>
21 #define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
25 return sc->ps_enabled && in ath9k_check_auto_sleep()
26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP); in ath9k_check_auto_sleep()
35 * to a sender if last desc is self-linked.
40 struct ath_hw *ah = sc->sc_ah; in ath_rx_buf_link()
45 ds = bf->bf_desc; in ath_rx_buf_link()
46 ds->ds_link = 0; /* link to null */ in ath_rx_buf_link()
47 ds->ds_data = bf->bf_buf_addr; in ath_rx_buf_link()
[all …]
/linux-6.14.4/arch/arm64/boot/dts/freescale/
Dfsl-ls1012a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1012A family SoC.
6 * Copyright 2019-2020 NXP
10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
23 rtic-a = &rtic_a;
[all …]
Dfsl-ls1043a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
[all …]
Dfsl-ls1046a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1046A family SoC.
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/gpio/gpio.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
37 #address-cells = <1>;
[all …]
/linux-6.14.4/drivers/spi/
Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <linux/dma-mapping.h>
13 #include <linux/err.h>
22 #include <linux/dma/imx-dma.h>
33 /* The maximum bytes that edma can transfer once.*/
34 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
144 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
145 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
153 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
155 if (fsl_lpspi->rx_buf) { \
[all …]
/linux-6.14.4/drivers/staging/gpib/uapi/
Dgpib_user.h1 /* SPDX-License-Identifier: GPL-2.0 */
39 CIC = (1 << CIC_NUM), /* GPIB interface is Controller-in-Charge */
49 ERR = (1 << ERR_NUM), /* Function call terminated on error */ enumerator
51 device_status_mask = ERR | TIMO | END | CMPL | RQS,
52 board_status_mask = ERR | TIMO | END | CMPL | SPOLL |
65 ENEB = 7, /* non-existent board (GPIB interface offline) */
66 EDMA = 8, /* DMA hardware error detected */ enumerator
98 /* End-of-string (EOS) modes for use with ibeos */
104 BIN = 0x1000 /* Do 8-bit compare on EOS */
202 cmd |= (dio_line - 1) & 0x7; in PPE_byte()
[all …]
/linux-6.14.4/drivers/dma/sf-pdma/
Dsf-pdma.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * - drivers/dma/fsl-edma.c
8 * - drivers/dma/dw-edma/
9 * - drivers/dma/pxa-dma.c
12 * - Chapter 12 "Platform DMA Engine (PDMA)" of
13 * SiFive FU540-C000 v1.0
14 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
21 #include <linux/dma-mapping.h>
26 #include "sf-pdma.h"
63 desc->chan = chan; in sf_pdma_alloc_desc()
[all …]
/linux-6.14.4/drivers/pci/controller/dwc/
Dpcie-rcar-gen4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
24 #include "pcie-designware.h"
26 /* Renesas-specific */
95 val = readl(rcar->base + PCIEINTSTS0); in rcar_gen4_pcie_link_up()
103 * -ETIMEDOUT.
125 return -ETIMEDOUT; in rcar_gen4_pcie_speed_change()
137 if (rcar->drvdata->ltssm_control) { in rcar_gen4_pcie_start_link()
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/ls/
Dls1021a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/thermal/thermal.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
12 interrupt-parent = <&gic>;
30 #address-cells = <1>;
31 #size-cells = <0>;
34 compatible = "arm,cortex-a7";
[all …]
/linux-6.14.4/drivers/mmc/host/
Ddavinci_mmc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
13 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
22 #include <linux/mmc/slot-gpio.h>
24 #include <linux/platform_data/mmc-davinci.h>
36 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
37 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
141 * EDMA transfer linkage instead of spending CPU time copying pages.
143 #define MAX_CCNT ((1 << 16) - 1)
[all …]

12