| /linux-6.14.4/arch/riscv/boot/dts/sifive/ |
| D | fu540-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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| D | fu740-c000.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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| /linux-6.14.4/arch/loongarch/mm/ |
| D | tlbex.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
14 #define PTRS_PER_PGD_BITS (PAGE_SHIFT - 3)
15 #define PTRS_PER_PUD_BITS (PAGE_SHIFT - 3)
16 #define PTRS_PER_PMD_BITS (PAGE_SHIFT - 3)
17 #define PTRS_PER_PTE_BITS (PAGE_SHIFT - 3)
63 bstrpick.d ra, t0, PTRS_PER_PGD_BITS + PGDIR_SHIFT - 1, PGDIR_SHIFT
64 alsl.d t1, ra, t1, 3
66 ld.d t1, t1, 0
67 bstrpick.d ra, t0, PTRS_PER_PUD_BITS + PUD_SHIFT - 1, PUD_SHIFT
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| /linux-6.14.4/arch/riscv/boot/dts/microchip/ |
| D | mpfs.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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| /linux-6.14.4/arch/riscv/boot/dts/starfive/ |
| D | jh7100.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive-jh7100.h>
9 #include <dt-bindings/reset/starfive-jh7100.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sifive,u74-mc", "riscv";
23 d-cache-block-size = <64>;
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| D | jh7110.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
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| /linux-6.14.4/arch/powerpc/boot/dts/ |
| D | microwatt.dts | 1 /dts-v1/;
4 #size-cells = <0x02>;
5 #address-cells = <0x02>;
6 model-name = "microwatt";
7 compatible = "microwatt-soc";
13 reserved-memory {
14 #size-cells = <0x02>;
15 #address-cells = <0x02>;
26 #clock-cells = <0>;
27 compatible = "fixed-clock";
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| /linux-6.14.4/Documentation/core-api/ |
| D | cachetlb.rst | 2 Cache and TLB Flushing Under Linux
7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
24 "TLB" is abstracted under Linux as something the cpu uses to cache
25 virtual-->physical address translations obtained from the software
27 possible for stale translations to exist in this "TLB" cache.
44 the TLB. After running, this interface must make sure that
47 there will be no entries in the TLB for 'mm'.
57 address translations from the TLB. After running, this
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| /linux-6.14.4/arch/parisc/kernel/ |
| D | cache.c | 6 * Copyright (C) 1999-2006 Helge Deller <[email protected]> (07-13-1999)
10 * Cache and TLB management
55 void flush_data_cache_local(void *); /* flushes local data-cache only */
56 void flush_instruction_cache_local(void); /* flushes local code-cache only */
62 * by software. We need a spinlock around all TLB flushes to ensure
125 test_bit(PG_dcache_dirty, &folio->flags)) { in __update_cache()
126 while (nr--) in __update_cache()
128 clear_bit(PG_dcache_dirty, &folio->flags); in __update_cache()
130 while (nr--) in __update_cache()
139 seq_printf(m, "I-cache\t\t: %ld KB\n", in show_cache_info()
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| /linux-6.14.4/arch/arc/mm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * TLB Management (flush/create/diagnostics) for MMUv3 and MMUv4
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
26 * Utility Routine to erase a J-TLB entry
63 /* Locate the TLB entry for this vaddr + ASID */ in tlb_entry_erase()
89 * with existing location. This will cause Write CMD to over-write in tlb_entry_insert()
95 /* setup the other half of TLB entry (pfn, rwx..) */ in tlb_entry_insert()
101 * which doesn't flush uTLBs. I'd rather be safe than sorry. in tlb_entry_insert()
131 * Un-conditionally (without lookup) erase the entire MMU contents
139 int num_tlb = mmu->sets * mmu->ways; in local_flush_tlb_all()
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| D | tlbex.S | 1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
8 * -MMU v1: moved out legacy code into a separate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * -For MMU V2, we need not do heuristics at the time of committing a D-TLB
14 * entry, so that it doesn't knock out its I-TLB entry
15 * -Some more fine tuning:
19 * -Practically rewrote the I/D TLB Miss handlers
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
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| /linux-6.14.4/Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V CPUs
10 - Paul Walmsley <[email protected]>
11 - Palmer Dabbelt <[email protected]>
12 - Conor Dooley <[email protected]>
15 This document uses some terminology common to the RISC-V community
19 mandated by the RISC-V ISA: a PC and some registers. This
27 - $ref: /schemas/cpu.yaml#
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| /linux-6.14.4/include/asm-generic/ |
| D | tlb.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* include/asm-generic/tlb.h
4 * Generic TLB shootdown code
32 * Generic MMU-gather implementation.
35 * correct and efficient ordering of freeing pages and TLB invalidations.
40 * 2) TLB invalidate page
49 * - tlb_gather_mmu() / tlb_gather_mmu_fullmm() / tlb_finish_mmu()
53 * Finish in particular will issue a (final) TLB invalidate and free
56 * - tlb_start_vma() / tlb_end_vma(); marks the start / end of a VMA
61 * - tlb_remove_table()
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| /linux-6.14.4/Documentation/arch/loongarch/ |
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
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| /linux-6.14.4/drivers/parisc/ |
| D | ccio-dma.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 ** ccio-dma.c:
4 ** DMA management routines for first generation cache-coherent machines.
9 ** (c) Copyright 2000 Hewlett-Packard Company
13 ** the I/O MMU - basically what x86 does.
16 ** o outbound DMA is slower - U2 won't prefetch data (GSC+ XQL signal).
17 ** o Inbound DMA less efficient - U2 can't use DMA_FAST attribute.
19 ** o Doesn't work under PCX-U/U+ machines since they didn't follow
20 ** the coherency design originally worked out. Only PCX-W does.
34 #include <linux/dma-map-ops.h>
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| /linux-6.14.4/arch/parisc/include/uapi/asm/ |
| D | pdc.h | 1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
14 #define PDC_BAD_PROC -1 /* Called non-existent procedure*/
15 #define PDC_BAD_OPTION -2 /* Called with non-existent option */
16 #define PDC_ERROR -3 /* Call could not complete without an error */
17 #define PDC_NE_MOD -5 /* Module not found */
18 #define PDC_NE_CELL_MOD -7 /* Cell module not found */
19 #define PDC_NE_BOOTDEV -9 /* Cannot locate a console device or boot device */
20 #define PDC_INVALID_ARG -10 /* Called with an invalid argument */
21 #define PDC_BUS_POW_WARN -12 /* Call could not complete in allowed power budget */
22 #define PDC_NOT_NARROW -17 /* Narrow mode not supported */
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| /linux-6.14.4/arch/sparc/kernel/ |
| D | tsb.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
17 /* Invoked from TLB miss handler, we are in the
23 * %g3: FAULT_CODE_{D,I}TLB
46 * %g1 -- PAGE_SIZE TSB entry address
47 * %g3 -- FAULT_CODE_{D,I}TLB
48 * %g4 -- missing virtual address
49 * %g6 -- TAG TARGET (vaddr >> 22)
67 cmp %g5, -1
106 * %g1 -- TSB entry address
107 * %g3 -- FAULT_CODE_{D,I}TLB
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| D | ktlb.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
57 /* fallthrough to TLB load */
70 * instruction get nop'd out and we get here to branch
71 * to the sun4v tlb load code. The registers are setup
78 * The sun4v TLB load wants the PTE in %g3 so we fix that
148 /* Index through the base page size TSB even for linear
169 /* fallthrough to TLB load */
173 661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
182 * instruction get nop'd out and we get here to branch
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| /linux-6.14.4/arch/powerpc/mm/nohash/ |
| D | 44x.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * -- paulus
11 * Copyright (C) 1995-1996 Gary Thomas ([email protected])
27 #include <asm/text-patching.h>
32 /* Used by the 44x TLB replacement exception handler.
36 unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
43 /* The TLB miss handlers hard codes the watermark in a cmpli in ppc44x_update_tlb_hwater()
46 * in the 2 TLB miss handlers when updating the value in ppc44x_update_tlb_hwater()
53 * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
57 unsigned int entry = tlb_44x_hwater--; in ppc44x_pin_tlb()
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| /linux-6.14.4/tools/perf/Documentation/ |
| D | perf-mem.txt | 1 perf-mem(1)
5 ----
6 perf-mem - Profile memory accesses
9 --------
14 -----------
20 and stores are sampled. Use the -t option to limit to loads or stores.
22 Note that on Intel systems the memory latency reported is the use-latency,
27 and kernel support is required. See linkperf:perf-arm-spe[1] for a setup guide.
32 --------------
33 -f::
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| /linux-6.14.4/arch/riscv/mm/ |
| D | tlbflush.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Flush entire TLB if number of entries to be flushed is greater
17 unsigned long size, in local_flush_tlb_range_threshold_asid() argument
21 unsigned long nr_ptes_in_range = DIV_ROUND_UP(size, stride); in local_flush_tlb_range_threshold_asid()
36 unsigned long size, unsigned long stride, unsigned long asid) in local_flush_tlb_range_asid() argument
38 if (size <= stride) in local_flush_tlb_range_asid()
40 else if (size == FLUSH_TLB_MAX_SIZE) in local_flush_tlb_range_asid()
43 local_flush_tlb_range_threshold_asid(start, size, stride, asid); in local_flush_tlb_range_asid()
49 local_flush_tlb_range_asid(start, end - start, PAGE_SIZE, FLUSH_TLB_NO_ASID); in local_flush_tlb_kernel_range()
70 unsigned long size; member
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| /linux-6.14.4/arch/riscv/kvm/ |
| D | tlb.c | 1 // SPDX-License-Identifier: GPL-2.0
16 #include <asm/insn-def.h>
164 vcpu->arch.last_exit_cpu == vcpu->cpu) in kvm_riscv_local_tlb_sanitize()
168 * On RISC-V platforms with hardware VMID support, we share same in kvm_riscv_local_tlb_sanitize()
170 * have stale G-stage TLB entries on the current Host CPU due to in kvm_riscv_local_tlb_sanitize()
174 * To cleanup stale TLB entries, we simply flush all G-stage TLB in kvm_riscv_local_tlb_sanitize()
178 vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid); in kvm_riscv_local_tlb_sanitize()
190 struct kvm_vmid *v = &vcpu->kvm->arch.vmid; in kvm_riscv_hfence_gvma_vmid_all_process()
191 unsigned long vmid = READ_ONCE(v->vmid); in kvm_riscv_hfence_gvma_vmid_all_process()
201 struct kvm_vmid *v = &vcpu->kvm->arch.vmid; in kvm_riscv_hfence_vvma_all_process()
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| /linux-6.14.4/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
24 const struct iommu_flush_ops *tlb; member
38 size_t size, size_t *count) in calc_pgsize() argument
45 /* Page sizes supported by the hardware and small enough for @size */ in calc_pgsize()
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
52 /* Make sure we have at least one suitable page size */ in calc_pgsize()
55 /* Pick the biggest page size remaining */ in calc_pgsize()
61 /* Find the next biggest support page size, if it exists */ in calc_pgsize()
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| /linux-6.14.4/drivers/firmware/efi/ |
| D | cper-arm.c | 1 // SPDX-License-Identifier: GPL-2.0
70 …"Local management operation (processor initiated a TLB management operation that resulted in an er…
71 …al management operation (processor raised a TLB error caused by another processor or device broadc…
146 printk("%scache level: %d\n", pfx, level); in cper_print_arm_err_info()
149 printk("%sTLB level: %d\n", pfx, level); in cper_print_arm_err_info()
152 printk("%saffinity level at which the bus error occurred: %d\n", in cper_print_arm_err_info()
245 printk("%sMIDR: 0x%016llx\n", pfx, proc->midr); in cper_print_proc_arm()
247 len = proc->section_length - (sizeof(*proc) + in cper_print_proc_arm()
248 proc->err_info_num * (sizeof(*err_info))); in cper_print_proc_arm()
250 printk("%ssection length: %d\n", pfx, proc->section_length); in cper_print_proc_arm()
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| /linux-6.14.4/tools/testing/selftests/kvm/ |
| D | access_tracking_perf_test.c | 1 // SPDX-License-Identifier: GPL-2.0
22 * 1. page_idle only issues clear_young notifiers, which lack a TLB flush. This
33 * the TLB and the number of pages held in pagevecs are a small fraction of the
35 * in nesting, where TLB size is unlimited) this test will print a warning
93 #define PAGEMAP_PFN_MASK ((1ULL << 55) - 1)
129 int vcpu_idx = vcpu_args->vcpu_idx; in mark_vcpu_memory_idle()
130 uint64_t base_gva = vcpu_args->gva; in mark_vcpu_memory_idle()
131 uint64_t pages = vcpu_args->pages; in mark_vcpu_memory_idle()
170 "vCPU %d: No PFN for %" PRIu64 " out of %" PRIu64 " pages.", in mark_vcpu_memory_idle()
176 * LRU list or the translations are still cached in the TLB). 90% is in mark_vcpu_memory_idle()
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