/linux-6.14.4/Documentation/devicetree/bindings/clock/ |
D | armada3700-xtal-clock.txt | 1 * Xtal Clock bindings for Marvell Armada 37xx SoCs 3 Marvell Armada 37xx SoCs allow to determine the xtal clock frequencies by 8 See Documentation/devicetree/bindings/pinctrl/marvell,armada-37xx-pinctrl.txt 11 - compatible : shall be one of the following: 12 "marvell,armada-3700-xtal-clock" 13 - #clock-cells : from common clock binding; shall be set to 0 16 - clock-output-names : from common clock binding; allows overwrite default clock 17 output names ("xtal") 20 pinctrl_nb: pinctrl-nb@13800 { 21 compatible = "armada3710-nb-pinctrl", "syscon", "simple-mfd"; [all …]
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D | silabs,si5351.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Silicon Labs Si5351A/B/C programmable I2C clock generators 10 The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to 11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 12 output clocks are accessible. The internal structure of the clock generators 16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf 19 - Alvin Šipraga <alsi@bang-olufsen.dk> [all …]
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D | marvell,armada-3700-uart-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/marvell,armada-3700-uart-clock.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 9 - Pali Rohár <[email protected]> 13 const: marvell,armada-3700-uart-clock 17 - description: UART Clock Control Register 18 - description: UART 2 Baud Rate Divisor Register 23 "TBG-A-P", "TBG-B-P", "TBG-A-S", "TBG-B-S", "xtal" 24 UART clock can use one from this set and when more are provided [all …]
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D | amlogic,meson8-ddr-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/amlogic,meson8-ddr-clkc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Amlogic DDR Clock Controller 10 - Martin Blumenstingl <[email protected]> 15 - amlogic,meson8-ddr-clkc 16 - amlogic,meson8b-ddr-clkc 24 clock-names: 26 - const: xtal [all …]
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D | amlogic,s4-pll-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved 4 --- 5 $id: http://devicetree.org/schemas/clock/amlogic,s4-pll-clkc.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Amlogic S4 PLL Clock Controller 11 - Yu Tu <[email protected]> 15 const: amlogic,s4-pll-clkc 23 clock-names: 25 - const: xtal [all …]
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D | nxp,lpc3220-clk.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/nxp,lpc3220-clk.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP LPC32xx Clock Controller 10 - Animesh Agarwal <[email protected]> 14 const: nxp,lpc3220-clk 19 '#clock-cells': 25 - description: External 32768 Hz oscillator. 26 - description: Optional high frequency oscillator. [all …]
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D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU) 4 peripheral blocks of the LPC18xx. Each independent clock is called 5 a base clock and itself is one of the inputs to the two Clock 9 The CGU selects the inputs to the clock generators from multiple 10 clock sources, controls the clock generation, and routes the outputs 11 of the clock generators through the clock source bus to the output 12 stages. Each output stage provides an independent clock source and 15 - Above text taken from NXP LPC1850 User Manual. 18 This binding uses the common clock binding: 19 Documentation/devicetree/bindings/clock/clock-bindings.txt [all …]
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D | amlogic,a1-peripherals-clkc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/clock/amlogic,a1-peripherals-clkc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Amlogic A1 Peripherals Clock Control Unit 10 - Neil Armstrong <[email protected]> 11 - Jerome Brunet <[email protected]> 12 - Jian Hu <[email protected]> 13 - Dmitry Rokosov <[email protected]> 17 const: amlogic,a1-peripherals-clkc [all …]
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D | pistachio-clock.txt | 1 Imagination Technologies Pistachio SoC clock controllers 4 Pistachio has four clock controllers (core clock, peripheral clock, peripheral 6 from the device-tree. 9 ---------------- 11 There are three external inputs to the clock controllers which should be 12 defined with the following clock-output-names: 13 - "xtal": External 52Mhz oscillator (required) 14 - "audio_clk_in": Alternate audio reference clock (optional) 15 - "enet_clk_in": Alternate ethernet PHY clock (optional) 17 Core clock controller: [all …]
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D | silabs,si5341.txt | 2 i2c clock generator. 6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf 8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf 10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf 12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output 15 The internal structure of the clock generators can be found in [2]. 21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not 33 - compatible: shall be one of the following: 34 "silabs,si5340" - Si5340 A/B/C/D 35 "silabs,si5341" - Si5341 A/B/C/D [all …]
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D | amlogic,s4-peripherals-clkc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 # Copyright (C) 2022-2023 Amlogic, Inc. All rights reserved 4 --- 5 $id: http://devicetree.org/schemas/clock/amlogic,s4-peripherals-clkc.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 8 title: Amlogic S4 Peripherals Clock Controller 11 - Yu Tu <[email protected]> 15 const: amlogic,s4-peripherals-clkc 23 - description: input fixed pll div2 24 - description: input fixed pll div2p5 [all …]
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/linux-6.14.4/arch/arm64/boot/dts/amlogic/ |
D | amlogic-t7-a311d2-an400.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include "amlogic-t7.dtsi" 13 interrupt-parent = <&gic>; 14 #address-cells = <2>; 15 #size-cells = <2>; 27 xtal: xtal-clk { label 28 compatible = "fixed-clock"; 29 clock-frequency = <24000000>; 30 clock-output-names = "xtal"; [all …]
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D | amlogic-t7-a311d2-khadas-vim4.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 /dts-v1/; 8 #include "amlogic-t7.dtsi" 23 reserved-memory { 24 #address-cells = <2>; 25 #size-cells = <2>; 31 no-map; 37 no-map; 41 xtal: xtal-clk { label 42 compatible = "fixed-clock"; [all …]
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D | meson-gxbb.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "meson-gx.dtsi" 7 #include "meson-gx-mali450.dtsi" 8 #include <dt-bindings/gpio/meson-gxbb-gpio.h> 9 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 10 #include <dt-bindings/clock/gxbb-clkc.h> 11 #include <dt-bindings/clock/gxbb-aoclkc.h> 12 #include <dt-bindings/reset/gxbb-aoclkc.h> 15 compatible = "amlogic,meson-gxbb"; 19 compatible = "amlogic,meson-gxbb-usb2-phy"; [all …]
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D | meson-gxl.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 7 #include "meson-gx.dtsi" 8 #include <dt-bindings/clock/gxbb-clkc.h> 9 #include <dt-bindings/clock/gxbb-aoclkc.h> 10 #include <dt-bindings/gpio/meson-gxl-gpio.h> 11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 14 compatible = "amlogic,meson-gxl"; 18 compatible = "amlogic,meson-gxl-usb-ctrl"; 21 #address-cells = <2>; 22 #size-cells = <2>; [all …]
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D | amlogic-a4-common.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/gpio/gpio.h> 11 compatible = "arm,armv8-timer"; 19 compatible = "arm,psci-1.0"; 23 xtal: xtal-clk { label 24 compatible = "fixed-clock"; 25 clock-frequency = <24000000>; 26 clock-output-names = "xtal"; [all …]
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D | meson-a1.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 7 #include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 8 #include <dt-bindings/gpio/meson-a1-gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/power/meson-a1-power.h> 12 #include <dt-bindings/reset/amlogic,meson-a1-reset.h> 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; [all …]
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D | meson-s4.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/interrupt-controller/irq.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/meson-s4-gpio.h> 10 #include <dt-bindings/clock/amlogic,s4-pll-clkc.h> 11 #include <dt-bindings/clock/amlogic,s4-peripherals-clkc.h> 12 #include <dt-bindings/power/meson-s4-power.h> 13 #include <dt-bindings/reset/amlogic,meson-s4-reset.h> 17 #address-cells = <2>; [all …]
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/linux-6.14.4/arch/mips/boot/dts/mobileye/ |
D | eyeq6h.dtsi | 1 // SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 6 #include <dt-bindings/interrupt-controller/mips-gic.h> 8 #include <dt-bindings/clock/mobileye,eyeq5-clk.h> 11 #address-cells = <2>; 12 #size-cells = <2>; 14 #address-cells = <1>; 15 #size-cells = <0>; 28 cpu_intc: interrupt-controller { 29 compatible = "mti,cpu-interrupt-controller"; 30 interrupt-controller; [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/serial/ |
D | amlogic,meson-uart.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/serial/amlogic,meson-uart.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Neil Armstrong <[email protected]> 15 of SoCs, and can be present either in the "Always-On" power domain or the 16 "Everything-Else" power domain. 18 The particularity of the "Always-On" Serial Interface is that the hardware 19 is active since power-on and does not need any clock gating and is usable 23 - $ref: serial.yaml# [all …]
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/linux-6.14.4/arch/arm/boot/dts/amlogic/ |
D | meson8.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 6 #include <dt-bindings/clock/meson8-ddr-clkc.h> 7 #include <dt-bindings/clock/meson8b-clkc.h> 8 #include <dt-bindings/gpio/meson8-gpio.h> 9 #include <dt-bindings/power/meson8-power.h> 10 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 11 #include <dt-bindings/reset/amlogic,meson8b-reset.h> 12 #include <dt-bindings/thermal/thermal.h> 20 #address-cells = <1>; 21 #size-cells = <0>; [all …]
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D | meson8b.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT 7 #include <dt-bindings/clock/meson8-ddr-clkc.h> 8 #include <dt-bindings/clock/meson8b-clkc.h> 9 #include <dt-bindings/gpio/meson8b-gpio.h> 10 #include <dt-bindings/power/meson8-power.h> 11 #include <dt-bindings/reset/amlogic,meson8b-reset.h> 12 #include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h> 13 #include <dt-bindings/thermal/thermal.h> 18 #address-cells = <1>; 19 #size-cells = <0>; [all …]
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/linux-6.14.4/Documentation/devicetree/bindings/soc/amlogic/ |
D | amlogic,meson-gx-hhi-sysctrl.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-hhi-sysctrl.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Neil Armstrong <[email protected]> 15 - enum: 16 - amlogic,meson-hhi-sysctrl 17 - amlogic,meson-gx-hhi-sysctrl 18 - amlogic,meson-gx-ao-sysctrl 19 - amlogic,meson-axg-hhi-sysctrl [all …]
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/linux-6.14.4/drivers/clk/mvebu/ |
D | armada-37xx-xtal.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Marvell Armada 37xx SoC xtal clocks 7 * Gregory CLEMENT <gregory.clement@free-electrons.com> 11 #include <linux/clk-provider.h> 21 struct device_node *np = pdev->dev.of_node; in armada_3700_xtal_clock_probe() 22 const char *xtal_name = "xtal"; in armada_3700_xtal_clock_probe() 30 xtal_hw = devm_kzalloc(&pdev->dev, sizeof(*xtal_hw), GFP_KERNEL); in armada_3700_xtal_clock_probe() 32 return -ENOMEM; in armada_3700_xtal_clock_probe() 36 parent = np->parent; in armada_3700_xtal_clock_probe() 38 dev_err(&pdev->dev, "no parent\n"); in armada_3700_xtal_clock_probe() [all …]
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/linux-6.14.4/include/linux/platform_data/ |
D | si5351.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Si5351A/B/C programmable clock generator platform_data. 10 * enum si5351_pll_src - Si5351 pll clock source 12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input 13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only) 22 * enum si5351_multisynth_src - Si5351 multisynth clock source 24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0 25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO 34 * enum si5351_clkout_src - Si5351 clock output clock source 36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N [all …]
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